ETC B9948CA

B9948
3.3V, 160-MHz, 1:12 Clock Distribution Buffer
Product Features
•
•
•
•
•
•
•
•
•
•
Description
160-MHz Clock Support
LVPECL or LVCMOS/LVTTL Clock Input
LVCMOS/LVTTL Compatible Inputs
12 Clock Outputs: Drive up to 24 Clock Lines
Synchronous Output Enable
Output Three-state Control
350-ps Maximum Output-to-Output Skew
Pin Compatible with MPC948
Industrial Temp. Range: –40°C to +85°C
32-Pin TQFP Package
The B9948 is a low-voltage clock distribution buffer with the
capability to select either a differential LVPECL or a LVCMOS/LVTTL compatible input clock. The two clock sources
can be used to provide for a test clock as well as the primary
system clock. All other control inputs are LVCMOS/LVTTL
compatible. The twelve outputs are 3.3V LVCMOS or LVTTL
compatible and can drive two series terminated 50Ω transmission lines. With this capability the B9948 has an effective
fan-out of 1:24. The outputs can also be three-stated via the
three-state input TS#. Low output-to-output skews make the
B9948 an ideal clock distribution buffer for nested clock trees
in the most demanding of synchronous systems.
The B9948 also provides a synchronous output enable input
for enabling or disabling the output clocks. Since this input is
internally synchronized to the input clock, potential output
glitching or runt pulse generation is eliminated.
Block Diagram
PECL_CLK
PECL_CLK#
0
TCLK
1
VDDC
12
32
31
30
29
28
27
26
25
VDD
VSS
Q0
VDDC
Q1
VSS
Q2
VDDC
Q3
Pin Configuration
Q0-Q11
TCLK_SEL
TCLK
PECL_CLK
PECL_CLK#
SYNC_OE
TS#
VDD
VSS
TCLK_SEL
SYNC_OE
B9948
24
23
22
21
20
19
18
17
VSS
Q4
VDDC
Q5
VSS
Q6
VDDC
Q7
Q11
VDDC
Q10
VSS
Q9
VDDC
Q8
VSS
9
10
11
12
13
14
15
16
TS#
1
2
3
4
5
6
7
8
Cypress Semiconductor Corporation
Document #: 38-07079 Rev. *B
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised January 14, 2002
B9948
Pin Description[1]
Pin
Name
PWR
I/O
Description
3
PECL_CLK
I, PU
PECL Input Clock
4
PECL_CLK#
I, PD
PECL Input Clock
2
TCLK
I, PU
External Reference/Test Clock Input
9, 11, 13, 15, 17,
19, 21, 23, 25, 27,
29, 31
Q(11:0)
1
TCLK_SEL
I, PU
Clock Select Input. When LOW, PECL clock is selected and
when HIGH TCLK is selected.
5
SYNC_OE
I, PU
Output Enable Input. When asserted HIGH, the outputs are
enabled and when set LOW the outputs are disabled in a LOW
state.
6
TS#
I, PU
Three-state Control Input. When asserted LOW, the output
buffers are three-stated. When set HIGH, the output buffers
are enabled.
10, 14, 18, 22, 26,
30
VDDC
3.3V Power Supply for Output Clock Buffers
7
VDD
3.3V Power Supply
8, 12, 16, 20, 24,
28, 32
VSS
Common Ground
VDDC
O
Clock Outputs
Note:
1. PD = Internal Pull-Down, PU = Internal Pull-Up.
Output Enable/ Disable
The B9948 features a control input to enable or disable the
outputs. This data is latched on the falling edge of the input
clock. When SYNC_OE is asserted LOW, the outputs are disabled in a LOW state. When SYNC_OE is set HIGH, the outputs are enabled as shown in Figure 1.
TCLK
SYNC_OE
Q
Figure 1. SYNC_OE Timing Diagram
Document #: 38-07079 Rev. *B
Page 2 of 6
B9948
Maximum Ratings
Storage Temperature: .................................-65°C to + 150°C
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For
proper operation, Vin and Vout should be constrained to the
range:
Operating Temperature: .................................-40°C to +85°C
VSS < (Vin or Vout) < VDD
Maximum ESD Protection.............................................. 2 KV
Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD).
Maximum Input Voltage Relative to VSS: ............ VSS – 0.3V
Maximum Input Voltage Relative to VDD:............. VDD + 0.3V
Maximum Power Supply: ................................................5.5V
Maximum Input Current:..................................................±20 mA
DC Parameters: VDDC = 3.3V ±10%, VDD = 3.3V ±10%, TA = –40°C to +85°C
Parameter
VIL
VIH
Description
Input Low Voltage
Input High Voltage
Conditions
Min.
Typ.
Max.
Unit
V
PECL_CLK, Single Ended
1.49
1.825
All other inputs
VSS
0.8
PECL_CLK, Single Ended
2.135
2.42
2.0
VDD
All other inputs
IIL
Input Low Current (@VIL = VSS)
Note 2
IIH
Input High Current (@VIL =VDD)
VPP
Peak-to-Peak Input Voltage
PECL_CLK
VCMR
Common Mode Range PECL_CLK
VOL
Output Low Voltage
IOL = 20 mA, Note 4
VOH
Output High Voltage
IOH = –20 mA, VDDC = 3.3V, Note 4
IDD
Quiescent Supply Current
All VDDC and VDD
Note 3
V
–100
µA
100
µA
300
1000
mV
VDD – 2.0
VDD – 0.6
V
0.4
V
2.5
V
1
2
mA
Cin
Input Capacitance
4
pF
Notes:
2. Inputs have pull-up resistors that effect input current, PECL_CLK# has a pull-down resistor.
3. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the VCMR
range and the input lies within the VPP specification.
4. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines.
Document #: 38-07079 Rev. *B
Page 3 of 6
B9948
AC Parameters[5]: VDDC = 3.3V ±10%, VDD = 3.3V ±10%, TA = –40°C to +85°C
Parameter
Fmax
Description
Conditions
Min.
[6]
Maximum Input Frequency
Max.
Unit
160
[6]
Tpd
Typ.
4.0
8.0
4.4
8.9
TCYCLE/2 – 800
TCYCLE/2 + 800
ps
PECL_CLK to Q Delay
[6]
TCLK to Q Delay
Cycle[6,7]
MHz
ns
FoutDC
Output Duty
tpZL, tpZH
Output enable time (all outputs)
2
10
ns
tpLZ, tpHZ
Output disable time (all outputs)
2
10
ns
350
ps
PECL_CLK to Q
1.5
ns
TCLK to Q
2.0
Tskew
Tskew (pp)
Ts
Output-to-Output
Measured at VDDC/2
Skew[6,8]
[9]
Part-to-Part Skew
Set-up
Time[6,10]
[6,10]
Th
Hold Time
[8]
Tr/Tf
Output Clocks Rise/Fall Time
SYNC_OE to PECL_CLK
1.0
SYNC_OE to TCLK
0.0
PECL_CLK to SYNC_OE
0.0
TCLK to SYNC_OE
1.0
0.8V to 2.0V
0.2
ns
ns
1.0
ns
Notes:
5. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
6. Outputs driving 50Ω transmission lines.
7. 50% input duty cycle.
8. Outputs loaded with 30 pF each
9. Part-to-Part Skew at a given temperature and voltage
10. Set-up and Hold times are relative to the falling edge of the input clock
Ordering Information
Part Number
B9948CA
Package Type
32-Pin TQFP
Production Flow
Industrial, –40°C to +85°C
Note:The ordering part number is formed by a combination of device number, device revision, package style, and screening as
shown below.
Marking: Example:
Cypress
B9948CA
Date Code, Lot #
B9948CA
Package
A = TQFP
Revision
Device Number
Document #: 38-07079 Rev. *B
Page 4 of 6
B9948
Package Drawing and Dimensions
32-Pin TQFP Outline Dimensions
Inches
D
D1
Millimeters
Symbol
Min.
Nom.
Max.
Min.
Nom.
Max.
A
-
-
0.047
-
-
1.20
A1
0.002
-
0.006
0.05
-
0.15
A2
0.037
-
0.041
0.95
-
1.05
D
-
0.354
-
-
9.00
-
D1
-
0.276
-
-
7.00
-
b
0.012
-
0.018
0.30
-
0.45
12°
A1
e
L
L
Document #: 38-07079 Rev. *B
e
0.031 BSC
0.018
-
0.80 BSC
0.030
0.45
-
0.75
b
Page 5 of 6
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
B9948
Document Title: B9948 3.3V, 160 MHz, 1:12 Clock Distribution Buffer
Document Number: 38-07079
Rev.
ECN No.
Issue
Date
Orig. of
Change
**
107115
06/06/01
IKA
Convert from IMI to Cypress
*A
108060
07/03/01
NDP
Changed Commercial to Industrial (See page 6)
*B
109805
01/31/02
DSG
Convert from Word to Frame (Cypress format)
Document #: 38-07079 Rev. *B
Description of Change
Page 6 of 6