NSC DP8482A

DP8482A 100k ECL to TTL Level Translator with Latch
General Description
Features
This circuit translates ECL input levels to TTL output levels
and provides a fall-through latch. The TRI-STATEÉ outputs
are designed to drive standard 50 pF loads. The strobe and
chip select inputs operate at ECL levels.
Y
Y
Y
Y
Y
Y
Logic and Connection Diagram
16-pin DIP or S.O.
TRI-STATE outputs
ECL control inputs
8 ns typical propagation delay with 50 pF load
Outputs are TRI-STATE during power up/down for
glitch free operation
100k ECL input compatible
Truth Table
Dual-In-Line Package
D
Q
STR
CS
H
L
L
L
L
H
L
L
X
Q
H
L
X
Hi-Z
X
H
H e high level (most positive)
L e low level (most negative)
X e don’t care
Order Number DP8482AJ, DP8482AM or DP8482AN
See NS Package Number J16A, N16A or M16B
TL/F/5863 – 1
Top View
TRI-STATEÉ is a registered trademark of National Semiconductor Corp.
C1995 National Semiconductor Corporation
TL/F/5863
RRD-B30M115/Printed in U. S. A.
DP8482A 100k ECL to TTL Level Translator with Latch
April 1990
Absolute Maximum Ratings (Note 1)
Storage Temperature
b 65§ C to a 150§ C
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
*Derate molded package 11.8 mW/§ C above 25§ C.
VEE Supply Voltage
Recommended Operating Conditions
b 8V
VCC Supply Voltage
Input Voltage
Output Voltage
Maximum Power Dissipation* at 25§ C
Molded Package
7V
GND to VEE
5.5V
VEE Supply Voltage
VCC Supply Voltage
TA, Ambient Temperature
b 4.5V g 7%
5.0V g 10%
0§ C to 85§ C
1476 mW
Electrical Characteristics (TTL Logic) (Notes 2, 3 and 4)
Symbol
Parameter
Conditions
VOL
Output Low Voltage
IOL e 12 mA
VOH
Output High Voltage
IOH eb10 mA
IAV
Output Low Drive Current
Force 2.5V
IOS
Output High Drive Current
Force 0V
IOZ
TRI-STATE Output Current
ICC
Supply Current
Min
Typ
Max
0.5
VCCb2V
Units
V
V
70
150
b 70
b 150
b 350
mA
b 50
1
a 50
mA
35
mA
mA
Electrical Characteristics (ECL Logic) (Notes 2 and 3)
Max
Units
VIL
Symbol
Input Low Voltage
Parameter
VEE eb4.5V
Conditions
TA
b 1810
Min
Typ
b 1475
mV
VIH
Input High Voltage
VEE eb4.5V
b 1165
b 880
mV
IIL
Input Low Current
VIN e VIL Max
50
100
mA
IIH
Input High Current
VIN e VIH Max
75
750
mA
IEE
Supply Current
b 55
mA
Switching Characteristics (Notes 2 and 5)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
ns
tPD1
Strobe to Output Delay
CL e 50 pF
4
9
15
tPD2
Data to Output Delay
CL e 50 pF
3.5
8
15
tS
Data Set-Up Time
(Note 6)
3.0
1.0
ns
tH
Data Hold Time
(Note 6)
3.0
1.0
ns
tPW
Strobe Pulse Width
(Note 6)
5.0
3.0
tZE
Delay from Chip Select to
Active State from Hi-Z State
CL e 50 pF
6
15
25
ns
tEZ
Delay from Chip Select to Hi-Z
State from Active State
CL e 50 pF
4.5
12
22
ns
ns
ns
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation.
Note 2: Unless otherwise specified, min/max limits apply across the 0§ C to 85§ C ambient temperature range in still air and across the specified supply variations.
All typical values are for TA e 25§ C and nominal supply. Maximum propagation delays are specified with all outputs switching simultaneously.
Note 3: All currents into device pins are shown as positive; all currents out of device pins are shown as negative. All voltages are referenced to ground, unless
otherwise specified.
Note 4: When DC testing IAV or IOS, only one output should be tested at a time and the current limited to 120 mA max.
Note 5: Unless otherwise specified, all AC measurements are referenced from the 50% level of the ECL input to the 0.8V level on negative transitions or the 2.4V
level on positive transitions of the output. ECL input rise and fall times are 0.7 ns g 0.1 ns from 20% to 80%.
Note 6: Caution should be used when latching data while the outputs are switching. TTL outputs generate severe ground noise when switching. This noise can be
sufficient to cause the ECL latch to lose data. Board mounting and good supply decoupling are desirable. The worst case conditions are with all outputs switching
low simultaneously, the maximum capacitive loading on the outputs and the maximum VCC supply voltage applied.
2
Switching Time Waveforms
TL/F/5863 – 2
S1 open
TL/F/5863 – 3
Test Load
TL/F/5863 – 4
Typical Performance Versus CL
TL/F/5863 – 5
TL/F/5863 – 6
3
Physical Dimensions inches (millimeters)
Cavity Dual-In-Line Package (J)
Order Number DP8482AJ
NS Package Number J16A
4
Physical Dimensions inches (millimeters) (Continued)
Order Number DP8482AM
NS Package Number M16B
5
DP8482A 100k ECL to TTL Level Translator with Latch
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number DP8482AN
NS Package Number N16A
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