Order this document by J112/D SEMICONDUCTOR TECHNICAL DATA N–Channel — Depletion 1 DRAIN 3 GATE 2 SOURCE MAXIMUM RATINGS Rating Symbol Value Unit Drain – Gate Voltage VDG – 35 Vdc Gate – Source Voltage VGS – 35 Vdc Gate Current IG 50 mAdc Total Device Dissipation @ TA = 25°C Derate above 25°C PD 350 2.8 mW mW/°C TL 300 °C TJ, Tstg – 65 to +150 °C Lead Temperature Operating and Storage Junction Temperature Range 1 2 3 CASE 29–04, STYLE 5 TO–92 (TO–226AA) ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Characteristic Symbol Min Max Unit V(BR)GSS 35 — Vdc IGSS — – 1.0 nAdc VGS(off) – 1.0 – 5.0 Vdc ID(off) — 1.0 nAdc Zero–Gate–Voltage Drain Current(1) (VDS = 15 Vdc) IDSS 5.0 — mAdc Static Drain–Source On Resistance (VDS = 0.1 Vdc) rDS(on) — 50 Ω Drain Gate and Source Gate On–Capacitance (VDS = VGS = 0, f = 1.0 MHz) Cdg(on) + Csg(on) — 28 pF Drain Gate Off–Capacitance (VGS = –10 Vdc, f = 1.0 MHz) Cdg(off) — 5.0 pF Source Gate Off–Capacitance (VGS = –10 Vdc, f = 1.0 MHz) Csg(off) — 5.0 pF OFF CHARACTERISTICS Gate – Source Breakdown Voltage (IG = –1.0 µAdc) Gate Reverse Current (VGS = –15 Vdc) Gate Source Cutoff Voltage (VDS = 5.0 Vdc, ID = 1.0 µAdc) Drain–Cutoff Current (VDS = 5.0 Vdc, VGS = –10 Vdc) ON CHARACTERISTICS 1. Pulse Width = 300 µs, Duty Cycle = 3.0%. (Replaces J111/D) Motorola Small–Signal Transistors, FETs and Diodes Device Data Motorola, Inc. 1997 1 J112 TYPICAL SWITCHING CHARACTERISTICS 1000 500 TJ = 25°C 200 VGS(off) = 7.0 V 200 RK = RD′ 100 TJ = 25°C 500 t r , RISE TIME (ns) t d(on), TURN–ON DELAY TIME (ns) 1000 50 20 10 5.0 100 50 20 10 5.0 RK = 0 2.0 RK = 0 2.0 1.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) 20 30 1.0 0.5 0.7 1.0 50 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) Figure 1. Turn–On Delay Time 1000 1000 TJ = 25°C 500 200 100 RK = RD′ 50 20 10 RK = 0 20 2.0 30 50 Figure 3. Turn–Off Delay Time RK = 0 10 2.0 20 VGS(off) = 7.0 V RK = RD′ 50 5.0 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) 50 100 5.0 1.0 0.5 0.7 1.0 30 TJ = 25°C 500 VGS(off) = 7.0 V 200 20 Figure 2. Rise Time t f , FALL TIME (ns) t d(off) , TURN–OFF DELAY TIME (ns) VGS(off) = 7.0 V RK = RD′ 1.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) 20 30 50 Figure 4. Fall Time NOTE 1 +VDD RD SET VDS(off) = 10 V INPUT RK RT RGEN 50 Ω OUTPUT RGG 50 Ω VGEN INPUT PULSE tr ≤ 0.25 ns tf ≤ 0.5 ns PULSE WIDTH = 2.0 µs DUTY CYCLE ≤ 2.0% 50 Ω VGG RGG & RK Ȁ + RRDD)(RTRT))50)50 RD Figure 5. Switching Time Test Circuit 2 The switching characteristics shown above were measured using a test circuit similar to Figure 5. At the beginning of the switching interval, the gate voltage is at Gate Supply Voltage (–VGG). The Drain–Source Voltage (VDS) is slightly lower than Drain Supply Voltage (VDD) due to the voltage divider. Thus Reverse Transfer Capacitance (Crss) or Gate–Drain Capacitance (Cgd) is charged to VGG + VDS. During the turn–on interval, Gate–Source Capacitance (C gs) discharges through the series combination of RGen and RK. Cgd must discharge to VDS(on) through RG and RK in series with the parallel combination of effective load impedance (R′ D ) and Drain–Source Resistance (rds). During the turn–off, this charge flow is reversed. Predicting turn–on time is somewhat difficult as the channel resistance rds is a function of the gate–source voltage. While Cgs discharges, VGS approaches zero and rds decreases. Since Cgd discharges through rds, turn–on time is non–linear. During turn–off, the situation is reversed with rds increasing as Cgd charges. The above switching curves show two impedance conditions; 1) RK is equal to RD, which simulates the switching behavior of cascaded stages where the driving source impedance is normally the load impedance of the previous stage, and 2) RK = 0 (low impedance) the driving source impedance is that of the generator. Motorola Small–Signal Transistors, FETs and Diodes Device Data 15 20 10 C, CAPACITANCE (pF) y fs, FORWARD TRANSFER ADMITTANCE (mmhos) J112 10 7.0 5.0 Tchannel = 25°C VDS = 15 V 3.0 Cgs 7.0 5.0 Cgd 3.0 2.0 Tchannel = 25°C (Cds IS NEGLIGIBLE) 1.5 2.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) 20 30 1.0 0.03 0.05 0.1 50 Figure 6. Typical Forward Transfer Admittance IDSS = 10 160 mA 25 mA 50 mA 75 mA 100 mA 80 0 Tchannel = 25°C 0 1.0 2.0 3.0 4.0 5.0 6.0 VGS, GATE–SOURCE VOLTAGE (VOLTS) 7.0 9.0 8.0 7.0 rDS(on) @ VGS = 0 60 50 1.6 1.4 1.2 1.0 0.8 0.6 – 40 – 10 20 50 80 110 Tchannel, CHANNEL TEMPERATURE (°C) 140 170 10 Tchannel = 25°C 80 70 ID = 1.0 mA VGS = 0 Figure 9. Effect of Temperature On Drain–Source On–State Resistance 6.0 VGS(off) 5.0 40 4.0 30 3.0 20 2.0 10 1.0 VGS, GATE–SOURCE VOLTAGE (VOLTS) rds(on), DRAIN–SOURCE ON–STATE RESISTANCE (OHMS) 90 1.8 0.4 – 70 8.0 Figure 8. Effect of Gate–Source Voltage On Drain–Source Resistance 100 30 2.0 125 mA 120 40 10 Figure 7. Typical Capacitance rds(on), DRAIN–SOURCE ON–STATE RESISTANCE (NORMALIZED) rds(on), DRAIN–SOURCE ON–STATE RESISTANCE (OHMS) 200 0.3 0.5 1.0 3.0 5.0 VR, REVERSE VOLTAGE (VOLTS) 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 IDSS, ZERO–GATE–VOLTAGE DRAIN CURRENT (mA) NOTE 2 The Zero–Gate–Voltage Drain Current (IDSS), is the principle determinant of other J-FET characteristics. Figure 10 shows the relationship of Gate–Source Off Voltage (VGS(off) and Drain–Source On Resistance (rds(on)) to IDSS. Most of the devices will be within ±10% of the values shown in Figure 10. This data will be useful in predicting the characteristic variations for a given part number. For example: Unknown rds(on) and VGS range for an J112 The electrical characteristics table indicates that an J112 has an IDSS range of 25 to 75 mA. Figure 10, shows rds(on) = 52 Ohms for IDSS = 25 mA and 30 Ohms for IDSS = 75 mA. The corresponding VGS values are 2.2 volts and 4.8 volts. Figure 10. Effect of IDSS On Drain–Source Resistance and Gate–Source Voltage Motorola Small–Signal Transistors, FETs and Diodes Device Data 3 J112 PACKAGE DIMENSIONS A NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. CONTOUR OF PACKAGE BEYOND DIMENSION R IS UNCONTROLLED. 4. DIMENSION F APPLIES BETWEEN P AND L. DIMENSION D AND J APPLY BETWEEN L AND K MINIMUM. LEAD DIMENSION IS UNCONTROLLED IN P AND BEYOND DIMENSION K MINIMUM. B R P L F SEATING PLANE K DIM A B C D F G H J K L N P R V D X X G J H V C SECTION X–X 1 N N CASE 029–04 (TO–226AA) ISSUE AD INCHES MIN MAX 0.175 0.205 0.170 0.210 0.125 0.165 0.016 0.022 0.016 0.019 0.045 0.055 0.095 0.105 0.015 0.020 0.500 ––– 0.250 ––– 0.080 0.105 ––– 0.100 0.115 ––– 0.135 ––– MILLIMETERS MIN MAX 4.45 5.20 4.32 5.33 3.18 4.19 0.41 0.55 0.41 0.48 1.15 1.39 2.42 2.66 0.39 0.50 12.70 ––– 6.35 ––– 2.04 2.66 ––– 2.54 2.93 ––– 3.43 ––– STYLE 5: PIN 1. DRAIN 2. SOURCE 3. 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