MPF4392, MPF4393 Preferred Devices JFET Switching Transistors N−Channel − Depletion Features • Pb−Free Packages are Available* http://onsemi.com 2 SOURCE MAXIMUM RATINGS Rating Symbol Value Unit Drain −Source Voltage VDS 30 Vdc Drain −Gate Voltag VDG 30 Vdc Gate−Source Voltage VGS 30 Vdc Forward Gate Current IG(f) 50 mAdc Total Device Dissipation @ TA = 25°C Derate above 25°C PD 350 2.8 mW mW/°C −65 to +150 °C Operating and Storage Channel Temperature Range Tchannel, Tstg 3 GATE 1 DRAIN TO−92 (TO−226AA) CASE 29−11 STYLE 5 1 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 2 3 MARKING DIAGRAM MPF 439x AYWW G G MPF439x = Device Code x = 2 or 3 A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device MPF4392 MPF4392G MPF4393 MPF4393G MPF4393RLRP MPF4393RLRPG *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 January, 2006 − Rev. 5 1 Package Shipping † TO−92 1000 Units / Bulk TO−92 (Pb−Free) 1000 Units / Bulk TO−92 1000 Units / Bulk TO−92 (Pb−Free) 1000 Units / Bulk TO−92 1000 / Ammo Box TO−92 (Pb−Free) 1000 / Ammo Box Preferred devices are recommended choices for future use and best overall value. Publication Order Number: MPF4392/D MPF4392, MPF4393 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 30 − − Vdc − − − − 1.0 0.2 nAdc mAdc − − − − 1.0 0.1 nAdc mAdc −2.0 −0.5 − − −5.0 −3.0 25 5.0 − − 75 30 − − − − 0.4 0.4 − − − − 60 100 − − 17 12 − − − − − − 60 100 − 6.0 10 − − 2.5 3.2 3.5 − − − 2.0 2.5 5.0 5.0 − − 15 29 20 35 − − 4.0 6.5 15 15 − − 20 37 35 55 OFF CHARACTERISTICS Gate −Source Breakdown Voltage (IG = 1.0 mAdc, VDS = 0) V(BR)GSS Gate Reverse Current (VGS = 15 Vdc, VDS = 0) (VGS = 15 Vdc, VDS = 0, TA = 100°C) IGSS Drain−Cutoff Current (VDS = 15 Vdc, VGS = 12 Vdc) (VDS = 15 Vdc, VGS = 12 Vdc, TA = 100°C) ID(off) Gate Source Voltage (VDS = 15 Vdc, ID = 10 nAdc) VGS MPF4392 MPF4393 Vdc ON CHARACTERISTICS Zero −Gate −Voltage Drain Current (Note 1) (VDS = 15 Vdc, VGS = 0) IDSS MPF4392 MPF4393 Drain−Source On−Voltage (ID = 6.0 mAdc, VGS = 0) (ID = 3.0 mAdc, VGS = 0) mAdc VDS(on) MPF4392 MPF4393 Static Drain−Source On Resistance (ID = 1.0 mAdc, VGS = 0) Vdc W rDS(on) MPF4392 MPF4393 SMALL− SIGNAL CHARACTERISTICS Forward Transfer Admittance (VDS = 15 Vdc, ID = 25 mAdc, f = 1.0 kHz) (VDS = 15 Vdc, ID = 5.0 mAdc, f = 1.0 kHz) |yfs| MPF4392 MPF4393 Drain−Source “ON” Resistance (VGS = 0, ID = 0, f = 1.0 kHz) mmhos W rds(on) MPF4392 MPF4393 Input Capacitance (VGS = 15 Vdc, VDS = 0, f = 1.0 MHz) Ciss Reverse Transfer Capacitance (VGS = 12 Vdc, VDS = 0, f = 1.0 MHz) (VDS = 15 Vdc, ID = 10 mAdc, f = 1.0 MHz) Crss pF pF SWITCHING CHARACTERISTICS Rise Time (See Figure 2) (ID(on) = 6.0 mAdc) (ID(on) = 3.0 mAdc) MPF4392 MPF4393 tr Fall Time (See Figure 4) (VGS(off) = 7.0 Vdc) (VGS(off) = 5.0 Vdc) MPF4392 MPF4393 Turn−On Time (See Figures 1 and 2) (ID(on) = 6.0 mAdc) (ID(on) = 3.0 mAdc) MPF4392 MPF4393 Turn−Off Time (See Figures 3 and 4) (VGS(off) = 7.0 Vdc) (VGS(off) = 5.0 Vdc) MPF4392 MPF4393 ns tf ns ton ns toff 1. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 3.0%. http://onsemi.com 2 ns MPF4392, MPF4393 TYPICAL SWITCHING CHARACTERISTICS 1000 500 200 RK = RD′ TJ = 25°C 500 MPF4392 VGS(off) = 7.0 V MPF4393 = 5.0 V 200 t r , RISE TIME (ns) t d(on), TURN−ON DELAY TIME (ns) 1000 100 50 20 10 5.0 RK = 0 50 20 10 5.0 7.0 10 2.0 3.0 ID, DRAIN CURRENT (mA) 20 30 1.0 0.5 0.7 1.0 50 20 30 50 1000 500 MPF4392 VGS(off) = 7.0 V MPF4393 = 5.0 V 200 TJ = 25°C RK = RD′ 200 t f , FALL TIME (ns) t d(off) , TURN−OFF DELAY TIME (ns) 5.0 7.0 10 2.0 3.0 ID, DRAIN CURRENT (mA) Figure 2. Rise Time TJ = 25°C 500 100 RK = RD′ 20 10 RK = 0 MPF4392 VGS(off) = 7.0 V MPF4393 = 5.0 V 100 50 20 RK = 0 10 5.0 2.0 2.0 1.0 0.5 0.7 1.0 RK = 0 2.0 1000 5.0 MPF4392 VGS(off) = 7.0 V MPF4393 = 5.0 V 100 Figure 1. Turn−On Delay Time 50 TJ = 25°C 5.0 2.0 1.0 0.5 0.7 1.0 RK = RD′ 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) 20 30 1.0 0.5 0.7 1.0 50 Figure 3. Turn−Off Delay Time 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) Figure 4. Fall Time http://onsemi.com 3 20 30 50 MPF4392, MPF4393 NOTE 1 The switching characteristics shown above were measured using a test circuit similar to Figure 5. At the beginning of the switching interval, the gate voltage is at Gate Supply Voltage (−VGG). The Drain−Source Voltage (VDS) is slightly lower than Drain Supply Voltage (VDD) due to the voltage divider. Thus Reverse Transfer Capacitance (Crss) or Gate−Drain Capacitance (Cgd) is charged to VGG + VDS. During the turn−on interval, Gate−Source Capacitance (Cgs) OUTPUT discharges through the series combination of RGen and RK. Cgd must discharge to VDS(on) through RG and RK in series with the parallel combination of effective load impedance (R′D) and Drain−Source Resistance (rds). During the turn−off, this charge flow is reversed. Predicting turn−on time is somewhat difficult as the channel resistance rds is a function of the gate−source voltage. While Cgs discharges, VGS approaches zero and rds decreases. Since Cgd discharges through rds, turn−on time is non−linear. During turn−off, the situation is reversed with rds increasing as Cgd charges. The above switching curves show two impedance conditions: 1) RK is equal to RD′ which simulates the switching behavior of cascaded stages where the driving source impedance is normally the load impedance of the previous stage, and 2) RK = 0 (low impedance) the driving source impedance is that of the generator. VDD RD SET VDS(off) = 10 V INPUT RK RT RGEN 50 W RGG 50 W VGEN 50 W VGG INPUT PULSE tr ≤ 0.25 ns tf ≤ 0.5 ns PULSE WIDTH = 2.0 ms DUTY CYCLE ≤ 2.0% RGG & RK RD′ = RD(RT + 50) RD + RT + 50 15 20 MPF4392 10 C, CAPACITANCE (pF) y fs , FORWARD TRANSFER ADMITTANCE (mmhos) Figure 5. Switching Time Test Circuit 10 MPF4393 7.0 5.0 Tchannel = 25°C VDS = 15 V 3.0 Cgs 7.0 5.0 Cgd Tchannel = 25°C (Cds IS NEGLIGIBLE) 3.0 2.0 1.5 2.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) 20 30 1.0 0.03 0.05 50 0.1 30 2.0 200 IDSS = 10 160 mA 25 mA 50 mA 75 mA 100 mA 125 mA rds(on) , DRAIN−SOURCE ON−STATE RESISTANCE (NORMALIZED) rds(on) , DRAIN−SOURCE ON−STATE RESISTANCE (OHMS) 10 Figure 7. Typical Capacitance Figure 6. Typical Forward Transfer Admittance 120 80 40 Tchannel = 25°C 0 0.3 0.5 1.0 3.0 5.0 VR, REVERSE VOLTAGE (VOLTS) 0 1.0 2.0 3.0 4.0 5.0 6.0 VGS, GATE−SOURCE VOLTAGE (VOLTS) 7.0 8.0 1.8 ID = 1.0 mA VGS = 0 1.6 1.4 1.2 1.0 0.8 0.6 0.4 −70 −40 −10 20 50 80 110 Tchannel, CHANNEL TEMPERATURE (°C) 140 Figure 9. Effect of Temperature On Drain−Source On−State Resistance Figure 8. Effect of Gate−Source Voltage On Drain−Source Resistance http://onsemi.com 4 170 MPF4392, MPF4393 90 10 Tchannel = 25°C 80 70 8.0 7.0 rDS(on) @ VGS = 0 60 50 6.0 VGS(off) 5.0 40 4.0 30 3.0 20 2.0 10 1.0 0 NOTE 2 9.0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 IDSS, ZERO−GATE VOLTAGE DRAIN CURRENT (mA) Figure 10. Effect of IDSS On Drain−Source Resistance and Gate−Source Voltage V GS , GATE−SOURCE VOLTAGE (VOLTS) r ds(on), DRAIN−SOURCE ON−STATE RESISTANCE (OHMS) 100 The Zero−Gate−Voltage Drain Current (IDSS), is the principle determinant of other J−FET characteristics. Figure 10 shows the relationship of Gate−Source Off Voltage (VGS(off)) and Drain−Source On Resistance (rds(on)) to IDSS. Most of the devices will be within ±10% of the values shown in Figure 10. This data will be useful in predicting the characteristic variations for a given part number. For example: Unknown rds(on) and VGS range for an MPF4392 The electrical characteristics table indicates that an MPF4392 has an IDSS range of 25 to 75 mA. Figure 10 shows rds(on) = 52 W for IDSS = 25 mA and 30 W for IDSS 75 mA. The corresponding VGS values are 2.2 V and 4.8 V. http://onsemi.com 5 MPF4392, MPF4393 PACKAGE DIMENSIONS TO−92 (TO−226) CASE 29−11 ISSUE AL A NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. CONTOUR OF PACKAGE BEYOND DIMENSION R IS UNCONTROLLED. 4. LEAD DIMENSION IS UNCONTROLLED IN P AND BEYOND DIMENSION K MINIMUM. B R P L SEATING PLANE DIM A B C D G H J K L N P R V K D X X G J H V C SECTION X−X 1 N INCHES MIN MAX 0.175 0.205 0.170 0.210 0.125 0.165 0.016 0.021 0.045 0.055 0.095 0.105 0.015 0.020 0.500 −−− 0.250 −−− 0.080 0.105 −−− 0.100 0.115 −−− 0.135 −−− MILLIMETERS MIN MAX 4.45 5.20 4.32 5.33 3.18 4.19 0.407 0.533 1.15 1.39 2.42 2.66 0.39 0.50 12.70 −−− 6.35 −−− 2.04 2.66 −−− 2.54 2.93 −−− 3.43 −−− STYLE 5: PIN 1. DRAIN 2. SOURCE 3. GATE N ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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