Order this document by MMBF4391LT1/D SEMICONDUCTOR TECHNICAL DATA N–Channel 2 SOURCE 3 GATE 3 1 DRAIN MAXIMUM RATINGS 1 Rating Symbol Value Unit Drain–Source Voltage VDS 30 Vdc Drain–Gate Voltage VDG 30 Vdc Gate–Source Voltage VGS 30 Vdc Forward Gate Current IG(f) 50 mAdc Symbol Max Unit Total Device Dissipation FR– 5 Board(1) TA = 25°C Derate above 25°C PD 225 mW 1.8 mW/°C Thermal Resistance, Junction to Ambient RqJA 556 °C/W TJ, Tstg – 55 to +150 °C 2 CASE 318 – 08, STYLE 10 SOT– 23 (TO – 236AB) THERMAL CHARACTERISTICS Characteristic Junction and Storage Temperature DEVICE MARKING MMBF4391LT1 = 6J; MMBF4392LT1 = 6K; MMBF4393LT1 = 6G ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Characteristic Symbol Min Max Unit V(BR)GSS 30 — Vdc — — 1.0 0.20 nAdc µAdc –4.0 –2.0 –0.5 –10 –5.0 –3.0 — — 1.0 1.0 OFF CHARACTERISTICS Gate–Source Breakdown Voltage (IG = 1.0 µAdc, VDS = 0) Gate Reverse Current (VGS = 15 Vdc, VDS = 0, TA = 25°C) (VGS = 15 Vdc, VDS = 0, TA = 100°C) Gate–Source Cutoff Voltage (VDS = 15 Vdc, ID = 10 nAdc) IGSS VGS(off) MMBF4391LT1 MMBF4392LT1 MMBF4393LT1 Off–State Drain Current (VDS = 15 Vdc, VGS = –12 Vdc) (VDS = 15 Vdc, VGS = –12 Vdc, TA = 100°C) 1. FR– 5 = 1.0 0.75 0.062 in. Vdc ID(off) nAdc µAdc Thermal Clad is a trademark of the Bergquist Company Motorola Small–Signal Transistors, FETs and Diodes Device Data Motorola, Inc. 1997 1 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Continued) Characteristic Symbol Min Max 50 25 5.0 150 75 30 — — — 0.4 0.4 0.4 — — — 30 60 100 Unit ON CHARACTERISTICS Zero–Gate–Voltage Drain Current (VDS = 15 Vdc, VGS = 0) IDSS MMBF4391LT1 MMBF4392LT1 MMBF4393LT1 Drain–Source On–Voltage (ID = 12 mAdc, VGS = 0) (ID = 6.0 mAdc, VGS = 0) (ID = 3.0 mAdc, VGS = 0) mAdc VDS(on) MMBF4391LT1 MMBF4392LT1 MMBF4393LT1 Static Drain–Source On–Resistance (ID = 1.0 mAdc, VGS = 0) Vdc Ω rDS(on) MMBF4391LT1 MMBF4392LT1 MMBF4393LT1 SMALL– SIGNAL CHARACTERISTICS Input Capacitance (VDS = 15 Vdc, VGS = 0, f = 1.0 MHz) Ciss — 14 pF Reverse Transfer Capacitance (VDS = 0, VGS = 12 Vdc, f = 1.0 MHz) Crss — 3.5 pF TYPICAL CHARACTERISTICS 1000 TJ = 25°C 500 MMBF4391 VGS(off) = 12 V MMBF4392 = 7.0 V MMBF4393 = 5.0 V RK = RD’ 200 500 100 50 20 10 RK = 0 5.0 2.0 1.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) 20 30 RK = RD’ 200 t r , RISE TIME (ns) t d(on) , TURN–ON DELAY TIME (ns) 1000 100 50 20 10 5.0 2.0 1.0 0.5 0.7 1.0 50 RK = 0 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) Figure 1. Turn–On Delay Time MMBF4391 VGS(off) = 12 V = 7.0 V MMBF4392 = 5.0 V MMBF4393 RK = RD’ 50 20 10 5.0 RK = 0 2.0 1.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) Figure 3. Turn–Off Delay Time 2 1000 500 TJ = 25°C 200 100 20 30 50 Figure 2. Rise Time t f , FALL TIME (ns) t d(off) , TURN–OFF DELAY TIME (ns) 1000 500 TJ = 25°C MMBF4391 VGS(off) = 12 V MMBF4392 = 7.0 V MMBF4393 = 5.0 V 20 30 50 RK = RD’ 200 100 TJ = 25°C MMBF4391 VGS(off) = 12 V MMBF4392 = 7.0 V MMBF4393 = 5.0 V 50 20 RK = 0 10 5.0 2.0 1.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 ID, DRAIN CURRENT (mA) 30 50 Figure 4. Fall Time Motorola Small–Signal Transistors, FETs and Diodes Device Data NOTE 1 –VDD RD SET VDS(off) = –10 V INPUT RK RT OUTPUT RGEN 50 Ω RGG 50 Ω INPUT PULSE tr ≤ 0.25 ns tf ≤ 0.5 ns PULSE WIDTH = 2.0 µs DUTY CYCLE ≤ 2.0% 50 Ω VGG VGEN RGG > RK RD’ = RD(RT + 50) RD + RT + 50 15 20 MMBF4392 10 MMBF4391 C, CAPACITANCE (pF) V fs , FORWARD TRANSFER ADMITTANCE (mmhos) Figure 5. Switching Time Test Circuit The switching characteristics shown above were measured using a test circuit similar to Figure 5. At the beginning of the switching interval, the gate voltage is at Gate Supply Voltage (–VGG). The Drain–Source Voltage (VDS) is slightly lower than Drain Supply Voltage (VDD) due to the voltage divider. Thus Reverse Transfer Capacitance (Crss) of Gate–Drain Capacitance (Cgd) is charged to VGG + VDS. During the turn–on interval, Gate–Source Capacitance (Cgs) discharges through the series combination of RGen and RK. Cgd must discharge to VDS(on) through RG and RK in series with the parallel combination of effective load impedance (R’D) and Drain–Source Resistance (rDS). During the turn–off, this charge flow is reversed. Predicting turn–on time is somewhat difficult as the channel resistance rDS is a function of the gate–source voltage. While Cgs discharges, VGS approaches zero and rDS decreases. Since Cgd discharges through rDS, turn–on time is non–linear. During turn–off, the situation is reversed with rDS increasing as Cgd charges. The above switching curves show two impedance conditions; 1) RK is equal to RD’ which simulates the switching behavior of cascaded stages where the driving source impedance is normally the load impedance of the previous stage, and 2) RK = 0 (low impedance) the driving source impedance is that of the generator. 10 MMBF4393 7.0 Tchannel = 25°C VDS = 15 V 5.0 3.0 2.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 Cgs 7.0 Cgd 5.0 3.0 2.0 1.5 Tchannel = 25°C (Cds is negligible 1.0 0.03 0.05 0.1 50 ID, DRAIN CURRENT (mA) 200 IDSS 25 mA = 10 160 mA 50 mA 75 mA 100 mA 125 mA 120 80 40 Tchannel = 25°C 0 0 1.0 2.0 3.0 5.0 4.0 6.0 7.0 VGS, GATE–SOURCE VOLTAGE (VOLTS) 30 Figure 7. Typical Capacitance r DS(on), DRAIN–SOURCE ON–STATE RESISTANCE (NORMALIZED) r DS(on), DRAIN–SOURCE ON–STATE RESISTANCE (OHMS) Figure 6. Typical Forward Transfer Admittance 0.3 0.5 1.0 3.0 5.0 10 VR, REVERSE VOLTAGE (VOLTS) 8.0 Figure 8. Effect of Gate–Source Voltage on Drain–Source Resistance Motorola Small–Signal Transistors, FETs and Diodes Device Data 2.0 1.8 ID = 1.0 mA VGS = 0 1.6 1.4 1.2 1.0 0.8 0.6 0.4 –70 –40 –10 20 50 80 110 140 170 Tchannel, CHANNEL TEMPERATURE (°C) Figure 9. Effect of Temperature on Drain–Source On–State Resistance 3 100 90 80 70 60 50 40 30 20 10 0 10 Tchannel = 25°C 9.0 8.0 7.0 rDS(on) @ VGS = 0 6.0 VGS(off) 5.0 4.0 3.0 2.0 1.0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 IDSS, ZERO–GATE VOLTAGE DRAIN CURRENT (mA) V GS , GATE–SOURCE VOLTAGE (VOLTS) r DS(on) , DRAIN–SOURCE ON–STATE RESISTANCE (OHMS) NOTE 2 The Zero–Gate–Voltage Drain Current (IDSS) is the principle determinant of other J–FET characteristics. Figure 10 shows the relationship of Gate–Source Off Voltage (VGS(off)) and Drain–Source On Resistance (rDS(on)) to IDSS. Most of the devices will be within ±10% of the values shown in Figure 10. This data will be useful in predicting the characteristic variations for a given part number. For example: Unknown rDS(on) and VGS range for an MMBF4392 The electrical characteristics table indicates that an MMBF4392 has an IDSS range of 25 to 75 mA. Figure 10 shows rDS(on) = 52 Ohms for IDSS = 25 mA and 30 Ohms for IDSS = 75 mA. The corresponding VGS values are 2.2 volts and 4.8 volts. Figure 10. Effect of IDSS on Drain–Source Resistance and Gate–Source Voltage 4 Motorola Small–Signal Transistors, FETs and Diodes Device Data INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.037 0.95 0.037 0.95 0.079 2.0 0.035 0.9 0.031 0.8 inches mm SOT–23 SOT–23 POWER DISSIPATION The power dissipation of the SOT–23 is a function of the pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RθJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA . Using the values provided on the data sheet for the SOT–23 package, PD can be calculated as follows: PD = TJ(max) – TA RθJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device which in this case is 225 milliwatts. PD = 150°C – 25°C 556°C/W = 225 milliwatts The 556°C/W for the SOT–23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 225 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT–23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. • Always preheat the device. • The delta temperature between the preheat and soldering should be 100°C or less.* • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C. • The soldering temperature and time shall not exceed 260°C for more than 10 seconds. • When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less. • After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. • Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. Motorola Small–Signal Transistors, FETs and Diodes Device Data 5 PACKAGE DIMENSIONS A L 3 B S 1 V STYLE 10: PIN 1. DRAIN 2. SOURCE 3. GATE 2 DIM A B C D G H J K L S V G C D H J K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. INCHES MIN MAX 0.1102 0.1197 0.0472 0.0551 0.0350 0.0440 0.0150 0.0200 0.0701 0.0807 0.0005 0.0040 0.0034 0.0070 0.0180 0.0236 0.0350 0.0401 0.0830 0.0984 0.0177 0.0236 MILLIMETERS MIN MAX 2.80 3.04 1.20 1.40 0.89 1.11 0.37 0.50 1.78 2.04 0.013 0.100 0.085 0.177 0.45 0.60 0.89 1.02 2.10 2.50 0.45 0.60 CASE 318–08 ISSUE AE SOT–23 (TO–236AB) Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315 Mfax: [email protected] – TOUCHTONE 602–244–6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, – US & Canada ONLY 1–800–774–1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 INTERNET: http://motorola.com/sps 6 ◊ MMBF4391LT1/D Motorola Small–Signal Transistors, FETs and Diodes Device Data