Product Overview ® Integrated Circuits Group ID242 Series Flash Memory Card (Model Numbers: ID242xxx) Spec No.: CPS0002-002 Issue Date: May, 1998 SHARP ID242 SERIES PRODUCT OVERVIEW l Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. l When using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) The products covered herein are designed and manufactured for the following application areas. When using the products covered herein for the equipment listed in Paragraph (2). even for the following application areas, be sure to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph (3). * Office electronics * Instrumentation and measuring equipment * Machine tools * Audiovisual equipment * Home appliances * Communication equipment other than for trunk lines (2) Those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. * Control and safety devices for airplanes, trains, automobiles, and other transportation equipment * Mainframe computers * Traffic control systems * Gas leak detectors and automatic cutoff devices * Rescue and security equipment * Other safety devices and safety equipment, etc. (3) Do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. * Aerospace equipment * Communications equipment for trunk lines * Control equipment for the nuclear power industry * Medical equipment related to life support, etc. (4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales representative of the company. CPSOOOZ-002 8 May. SHARI= ID242 SERIES PRODUCT OVERVIEW Contents ............................................................................................................... P. 3 2. Features ....................................................................................................................... P. 3 3. Block Diagram ............................................................................................................ P. 4 4. Pin Connections ........... ............................................................................................... P. 5 5. Signal Description ...................................................................................................... P. 6 6. Functions.. ................................................................................................................... P. 7 6. 1 Common Memory.. ......................................................................................... P. 7 6. 2 Attribute ........................................................................................... P. 8 6. 3 Function Table ................................................................................................ P. 9 Structure (CIS) ............................................................................... P. 9 1. Introduction.. Memory 7. Card Information 8. Card Control ............................................................................................................... P. 12 9. 8. 1 Reset ............................................................................................................. P. 12 8. 2 Status Register ................................................................................................ P. 12 8. 3 Write Protect Switch.. ..................................................................................... P. 12 8. 4 Identifier Codes.. ........ .. ................................................................................... P. 12 Register (CMR) ................................................................. P. 14 Management Component 10. Command Definitions.. ............................................................................................... P. 16 11. Electrical Specifications ............................................................................................. P‘ 17 Ratings ........................................................................... P. 17 ........................................................... P. 17 P. 17 P. 17 11. 1 Absolute Maximum 11. 2 Recommended 11. 3 Capacitance Operating Conditions.. ..................................................................................................... 11. 4 AC Input/Output Test Conditions .................................................................. 12. DC Characteristics ...................................................................................................... P. 18 13. AC Characteristics ...................................................................................................... P. 20 P. 20 ........................................ P. 22 13. 1 Common Memory 13. 2 Command Read Operations.. Write Operations ............................................................. : Common Memory.. 13. 3 Attribute Memory Read Operations ............................................................... P. 28 13. 4 Attribute Memory .............................................................. P. 29 Down .................................................................................. P. 30 Changes ................................................................................................ P. 31 15. Other Precautions.. ...................................................................................................... P. 31 16. External Diagrams P. 32 13. 5 Power-Up/Power 14. Specification Write Operations ...................................................................................................... SHARI= ID242 SERIES PRODUCT 3 OVERVIEW - - 1. Introduction This datasheet is for SHARP’s ID242 series flash memory card. This datasheet provides all AC and DC characteristics (including timing waveforms) grated registers(including and a convenient the Flash Memory’s reference for the device command status registers). set and the card’s inte- This datasheet provides description of the meth- ods which are very helpful for customer to use the card. 2. Features 2.1 Type 2.2 Overview Flash Memory Card 250ns(@Vcc=3.3v) 64K word Erase Unit Program/Erase Cycles blocks 100,000cycles/Block External Dimensions PCMCIA Type 1 54.0X 85.6X 3.3mm TlOSO-01 Parallel I/O Interface 2.3 Interface 2.4 Function 2.5 Pin Connections See Pin Connections Type of Connector Conforms 2.6 Table See Function Table in page. 9 to PCMCIA in page. 6 PC Card Standard 95 Card Use Connector (Card connector: JC20-J68S-NB3 2.7 Operating Temperature 2.8 Storage Temperature 2.9 Not designed for rated radiation JAE or FCN-568J068-G/O Fujitsu) 0 to 60°C -20 to 65°C hardened. CPS0002.002BMay,19! SHARP 3. Block 4 ID242 SERIES PRODUCT OVERVIEW Diagram ,r D<15:0> A<25:0> REG# CEl# , CE2# WE# OE# RDpSYk RESET, , 1 1 II,t t’ I t4 :A+ ’ VPPX cl RY/RY# WP VPP2 Data Add RP# RYrBY# *I +---( vcc t Flash Memory Data + CE# Add + WE# RP# + OE# RYiBY# c + -+’ * CE# + WE# + OE# CE# WE# OE# T II, vcc t Flash Memory Flash Memory Data Add RP# Control Logic VPPl t vcc VPPl t vcc t = - . =rLc VPPl b VPP2 b . CDl#, CDL% II. , II VPP2 vcc I I i iI I : i vpp1 vcc I I I I t :lash Memory I RY/BY# I OE# I __*1 Data Add RP# RY/BY# OE# 4 + -- - 4 I I I I I * I EEPROM I I - , I * I 9 I I Figure 1. Block Giagrarn - CE# b WE# OE# Data M Add v , I I I I I I I I I I I I I SHARI= ID242 SERIES PRODUCT OVERVIEW 5 4. Pin Connections Table 1. Pin Connections ;,” SIGNAL I/O FUNCTION 1 35 IGND 1 139 ID,, I I/O I Data Bit 13 ACTIVE IGround LOW I I I 43 IVS,# 0 Voltage Sense 1 I 44 IRFU 1 1Reserved I 45 IRFU 1 1Reserved 1 46 IA,, I I 1Address Bit 17 54 43 I Address Bit 23 55 A74 I Address Bit 24 1 56 IA,, I I 1Address Bit 25 57 VS,# I 58 IRESET I 0 Voltage Sense 2 1 I I Reset HIGH I 62 IBVD, 0 Battery Boltage Detect 2 63 BVD, 0 Battery Boltage Detect 1 64 DR 65 DQ I/O Data Bit 8 66 I/O Data Bit 10 D,Ll 67 ICD,#68 IGND I/O Data Bit 9 0 Card Detect 2 1Ground CPSOOO2-002 @ May.1 998 SHARP ID242 SERIES PRODUCT OVERVIEW 5. Signal Description Table 2. Symbol Signal Description l/O 1 Ao-Azs Du-D15 CEI#,CEZ# 1 OE# 1 WE# Pull-down (250k Q @ Vcc=Sv) 1/o Pull-down (2’0k ’ @VCC=‘V) 1 ADDRESS INPUTS: These are address bus lines which enable direct addressing of memory on the card. Signal AI) is not used in word access mode. The system should NOT access memory beyond the card’s density. because the upper addresses are not decoded. DATA INPUT/OUTPUT: De through Dls constitute the bi-directional significant bit, CARD ENABLE I & 2: CEI# enables Do-D7, CE2# enables Dx-DIG. Pull-up (250k 52 @ Vcc=Sv) WRlTE ENABLE: Active low signal gating write data to the memory c‘ard. OUTPUT ENABLE: Active low signal gating read data from the memory card. READY/BUSY OUTPUT: indicates status of internally timed erase or write activities. lD242 series has two types of Ready/Busy output mode; PCMClA mode and High-Performance mode. In PCMClA mode, a high output indicates the memory card is ready to accept accesses. A low output indicates that a device in the memory c,ard is busy. In High-Performance mode, the card outputs low when the card is in default state. A high output indicates at least one of flash memory devices in the card comes to be ready to accept accesses. CARD DETECT 1 & 2: These signals provide for card insertion detection. The signals are connected to ground internally on the memory card, and will be forced low whenever a card is placed in the socket. The host socket interface circuitry shall supply 10K or larger pull-up resistors on these signal pins. 0 CDt#, CD2# 0 Pull-down o LowPull-down OW High:Pull-up 1OOkw Ow WRlTE PROTECT: Write Protect reflects the status of the Write Protect switch on the memory card. WP set to high = write protected. VPPI, VW2 WRITE/ERASE vcc CARD POWER SUPPLY: GND RESET BVDt, BVD2 RFU POWER SUPPLY 1 & 2: GROUND: REG# VSI#, data bus. DIG is the most Pull-up (250k Q @Vcc=Sv) Pull-up (250k Q @ Vcc=Sv) RDY/BSY# WP Function Electrical interface VS2# 1 Pull-up (250kw @Vcc=Sv) REGlSTER SELECT: Provides access to attribute memory when REG# is low. 1 Pull-up (250kw @Vcc=Sv) RESET: Active high signal for placing card in Power-On 0 Pull-up 1OOkw BATTERY VOLTAGE DETECT 1 & 2: These signals are pulled high to maintain SRAM card compatibility. 0 VSI#: Pull-down N.C. VSB: N.C. or Default State. VOLTAGE SENSE 1 & 2: Notifies the host socket of the ClS’s VCC requirements. VS I# is pulleddown to ground when using the standard ClS, that indicate 3.3V operating is available. And when using the EEPROM for ClS, the VS2# is open. That indicate the available operation voltage is 5V only. RESERVED FOR FUTURE USE [email protected] SHARP ID242 SERIES PRODUCT OVERVIEW 7 - 6. Functions 6.1 Common Memory 6. 1. 1 Common Memory Architecture Figure 2 shows common memory architecture of ID242 series flash memory card. Device pair is consisted of two pieces of flash memory devices. Each device has individually erasable and lockable blocks. All blocks are divided into odd bytes and even bytes. Each device pair and block is selected by address bits. Table 3 shows definitions of address bits. F100'2.0: (a) For 2, 4, 8, 1OMB F10580' (b) For 16MB, 20MB Figure 2. Common Memory Architecture Table 3. Address Difinitions Address Pifinitions 2MB - IOMB Select Even / Odd byte in the byte access mode. 1Select address in the block. Select a block. 1Select a device pair. 16MB ,20MB A0 A16-Al I 1 A20-A17 1 A21-A17 I 1 1 A25-A21 1 1 A25-A22 T1051-01 CPS0002-002OMay.1991 3 SHARP 6. 1. 2 ID242SERIESPRODUCTOVERVIEW 8 Erase Erase is executed one block at a time. Erasable block size is 64K bytes in byte access mode and 128K bytes in word access mode. 6. 1. 3 Address Decoding The higher address area of ID242 series flash memory card which goes beyond common memory area is not decoded in common memory access. It means that the system will access to random memory address of the memory card even if system will try to access to the memory address which exceeds memory capacity of the card. Please do not access to the memory address which goes beyond memory capacity of the card. As an enhanced function, the memory card enables to output invalid data (either of OOOOhor FFFFh) when system will access to the memory address which exceeds memory capacity of the card. Please contact our sales & marketing support to find concrete way of setting. 6.2 Attribute Memory Figure 3 shows attribute memory map of ID242 series flash memory card. Attribute memory is contained within the Card Control Logic. Attribute memory contains the Card Information Structure (CIS) and Component Management Registers (CMRs). The CIS contains tuple information and is located at even byte addresses beginning with address OOOOh(Please refer to section 7). The standard CIS of ID242 series flash memory card is hardwired and is for read only. As an enhanced function, the hardwired CIS area is switchable to EEPROM so that customer can program required CIS. Please contact our sales & marketing support to find concrete way of setting. The CMRs are located at even byte addresses beginning with address 4000h (Please refer to section 9). r-------------, I I I Ir-----I I I Ic------ Address I I ' 004200h COMPONENT MANAGEMENT REGISTERS _ 004000h I I I I I 000200h I r------ I I I ------ODD I CARD INFORMATION STRUCTURE OOOOOOh EVEN F1003-01 Figure 3. Attribute Memory Map CPSOOOZ-002@ May. 1998 SHARI= 6.3 Function 6.3.1 ID242SERIESPRODUCTOVERVIEW Table Common Memory Access Table 4. Common Memory Access 6.3.2 Attribute Memory Access Table 5. Attribute XXX:Output Memory Access data is invalid. The standard CIS is for read only. Write operation 7. Card Information Structure is only for CMRs and CIS on EEPROM (CIS) The CIS is contained within attribute memory (Please refer to section 6.2). Table 6 shows standard CIS tuples, but it is for read only. As an enhanced function, can program the hardwired CIS area is switchable required CIS. Please contact our sales & marketing to EEPROM so that customer support to find concrete way of setting. SHARP ID242 SERIESPRODUCTOVERVIEW 10 Table 6. Standard CIS Address Value 53h 46h 48h 52h Description S :Product Info 48h H 49h 44h I D 54h 56h 58h ah 5Ch 5Eh 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 1 41h 52h 1 50h 20h 43h 4Fh 84h 86h 88h I ooh IEND TEXT FFh End of Tuple 1Ah Configuration Info 32h 2 34h 4 53h S 52h R 20h SPACE OOh END TEXT 53h S :Maker Info 48h H IA R IP SPACE C 0 Last Index of Configuration Table 92h I 40h I ICMRS Base Adress(MSB) Configuration Table Entry 1 [email protected] SHARP ID242 SERIES PRODUCT OVERVIEW Table 8. Standard CIS (Continued) 1 Address I1 Value A4h 1 OCh 06h A6h A8h , 06h AAh 1 23h I ACh 1 79h Description ]Icc Static1.2mA 1I ICC Average lOOmA ICC Peak lOOmA ~ICCPowerdown 5OmA I [Parameter Selection I I AEh BOh B2h I D5h 7Dh 1Bh IVpp Voltage 5V NC OK Ipp Static 15OmA B4h B6h B8h 75h 75h I I 52h Ipp Average 80mA Ipp Peak 80mA I 11ppPowerdown 50mA BAh BCh BEh 1Bh Configuration Table Entry 2 OFh I Tuple Link I I 02h IIndex t t t t 116h t ICCPowerdown 50mA Parameter Selection Vpp Voltage 12V 7Dh 1Bh NCOK Ipp Static 1XhnA 132h 134h D8h DAh DCh DEh EOh I 35h 35h 52h 1Bh 1lh 03h E2h E4h E6h E8h 02h 79h B5h 1Eh F4h F6h FAh FCh FEh IOOh 102h 118h 1lAh 1lCh 1lEh 120h 122h 23h 79h 8Eh I B5h 9Eh 1Bh 75h 75h 52h 1Bh 11pp Average 30mA Ipp Peak 30mA Ipp Powerdown 50mA Configuration Table Entry 3 Tuple Link Index I 136h Voltage 7Dh IICC Average 90mA 7Dh 1Bh 79h I 8Eh 7Dh 1Bh 35h 35h ~ICCPeak 90mA ICC Powerdown 15OmA Parameter Selection lvpp Voltage 12V NC OK Ipp Static 15OmA Ipp Average 30mA Ipp Peak 30mA 52h OOh OOh 1Eh 06h 02h 1 lh 1 Olh I Olh Ipp Powerdown 50mA Null Null Device Geometry Tuple Link Bus: 2bytes Erase Block: 64Kbvtes Read size: lbyte IWrite size: lbyte Partation: lblock Non-interleaved Manufacturer ID 13Ch 04h Tuple Link 13Eh 14Oh BOh Manufacturer Code OOh Manufacturer Info: 06h 2MB 07h 4MB 09h 8MB OAh 1OMB ODh 16MB OEh 20MB 33h Manufacturer Info: DVO 21h Function Identification 02h Tuple Link Olh IFunction: MEMORY OOh ISystem Init: None FFh End of CIS L 142h 3.3v 144h 146h 148h 14Ah 14Ch 14Eh Vpp Voltage 3.3V Ipp Static 15OmA Ipp Average 80mA Ipp Peak 80mA Ipp Powerdown 5OrnA Configuration Table Entry 4 IIndex Vcc & Vpp IParameter Selection Olh Olh 20h 138h 13Ah Vcc & Vpp Parameter Selection vcc 04h 02h 79h IOCh I OEh 1lOh 124h 126h 128h 12Ah 12Ch 12Eh 130h I I iO6h 108h IOAh 112h Il4h CAh I 06h IICCPeaklOOmA CCh CEh DOh D2h D4h D6h Address 1 Value 1 Description 104h 1Oh Tuple Link I I I I I. CPSOOOZ-002 0 May. 199 SHARP 8. Card 8. 1 12 ID242 SERIES PRODUCT OVERVIEW Control Reset The card is in initial state directly after power-up. But we recommend to do reset operation after power-up to make sure to initialize the card. During block erase, byte write, or lock-bit configuration modes, an active RESET will abort the operation. RDYI BSY# remains low until the reset operation completes. Memory contents being altered are no longer valid; the data may be partially erased or written. The host must wait after RESET goes to logic-Low write another command, as determined by (Vu) before it can tPHWL. It is important to assert RESET to the card during a system reset. If a CPU reset occurs without a card reset, the host will not be able to read from the card if that card is in a different mode when the system reset occurs. For example, if an end-user initiates a host reset when the card is in read status register mode, the host will attempt to read code from the card, but will actually read status register data. Sharp’s ID242 Series Flash Memory Card allows proper card reset following a system reset through the use of the RESET input. 8. 2 Status Register Each flash memory device in the card has status register. The status register may be read to determine when a write, block erase, or lock-bits configuration is complete, and whether that operation completed successfully (please refer to Table 10). It may be read at any time by writing the Read Status Register command (70h, 7070h) into the CUI. In word access mode, the status register data of even byte devices are output to D7-0,and the status register data of odd byte devices are output to D15-8. 8. 3 Write Protect Switch The ID242 Series Flash Memory Card has a write protect switch on the back of the card. When the switch is in the write protect position, the card blocks all writes to the common and attribute memory without Card Management Registers region (see Figure 5). 8. 4 Read identifier Codes / Lock bits Information Manufacture Code and Device Code are contained within each flash memory device in the memory card. The identifier code operation is initiated by writing the Read Identifier Codes command (90h, 9090h) into the CUI of each memory device. The specific address of each device is necessary to be selected to read these codes (Table 8). F1005-01 I m Writeble position I I I Write protZ&ition Note: The write protect switch is shown by the black square. Figure 4. Write Protect Switch [email protected] SHARP Table 7. ID242 SERIES PRODUCT 13 OVERVIEW Status Register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SR.7 SR.6 SR.5 SR.4 SR.3 SR.2 SR.l SR.0 WSMS ESS ECLBS BWSLBS VPPS BWSS DPS RFU SR.7 =WRITE STATE MACHINE I = Ready 0 = Busy STATUS Notes: Chech RDY/BSY# or SR.7 to determine block erase, word/byte write, or lock-bit configuration completion. SR.6-0 are invalid while SR.7=“0”. SR.6 =ERASE-SUSPEND STATUS I = Erase Suspended 0 = Erase in Progress/Completed SR.5 =ERASE AND CLEAR LOCK-BlTS STATUS 1 = Error ln Block Erasure or Clear Lock-Bits 0 = Successful Block Erase or Clear Lock-Bits SR.4 =BYTE WRITE AND SET LOCK-BIT 1 = Error in Byte Write or Set Block/Master Lock-Bit 0 = Successful Byte Write or Set Block/Master Lock-Bit STATUS SR.3 =VPP STATUS 1 = VPP Low Detect, Operation Abort 0 = VPP OK SR.2 =BYTE WRITE SUSPEND STATUS 1 = Byte Write Suspended 0 = Byte Write in Progress/Completed SR. 1 =DEVICE PROTECT STATUS 1 = Master Lock-bit,Block Lock-bit and/or RP# Lock Detected, Operation Abort 0 = Unlock SR.0 =Reserved for Future Enhancements Table 8. Identifier Block Lock Configuration If both SR.5 and SR.4 are ” 1 “s after a block erase or lockbit configuration attempt, an improper command sequence was entred. SR.3 does not provide a continuous indication of V,, level. The WSM interrogates and indicates the V,, level only after Block Erase, Word/Byte Write, Set Block/Master Lock-bit, or Clear Lock-bits command sequences. SR.3 is not guaranteed to reports accurate feedback only when V,,=V,,,,,,,,. SR. 1 does not provide a continuous indication of master and block lock-bit values. The WSM interrogates the master lock-bit, block lock-bit. and RP# only after Block Erase, Word/Byte Write, or Lock-bit configuration command sequences. If informs the system, depending on the attempted operation, if the block lock-bit is set, master lock-bit is set, and/or RP# is not 12V. Reading the block lock and master lock configuration codes after writing the Read Identifier Codes commnad indicates master and block lock-bit status. SR.0 is reserved for future use and should be masked out when polling the status register. Codes / Lock bits (X: Select Block) D7-D I: Reserved NOTE: A0 is ignored in word access mode. and D15-D8 outputs the Odd byte data. DPA: Address as select device pair BLKD: Block Lock Configuration Data MLKD: Master Lock Configuration Data T1052-01 CPSOOO2-0028 May. 1999 SHARI= ID242 SERIES PRODUCT 9. Component Component Management Management Registers Registers (CMR) OVERVIEW (CMR) are mapped at even byte locations beginning at address 4000h in attribute memory. 9. 1 Configuration Option Register (Address4000h) Address Bit.7 4000h SRESET SRESET: 9. 2 Bit.6 Bit.3 Bit.2 Bit. 1 Bit.0 Bit.2 Bit. 1 Bit.0 Reserved l=Reset State O=End Reset Cycle Card Configuration Register (Address:4002h) Address Bit.7 Bit.6 Bit.5 Bit.4 Bit.3 Reserved 4002h PWDN: 9. 3 Bit.4 Bit.5 Reserved PWDN l=Power-Down Device pairs that apointed by Sleep Control Register(4118h-411Ah) Down. O=Power-Up are in Power- Socket and Copy Register (Address:4006h) Address Bit.7 4006h Reserved Bit.6 Bit.5 Bit.4 Bit.3 Bit.2 Copy No. Bit.1 Bit.0 Soket No. Soket No.: Socket Number Copy No.: Copy Number The card may use to distinguish between similar cards installed in a system. TlO53.01 9. 4 Card Status Register (Address:41 OOh) Address Bit.7 Bit.6 Bit.5 Bit.4 Bit.3 Bit.2 Bit. 1 Bit.0 41OOh ADM ADS SRESET CMWP PWDN CISWP WP RDY/BSY ADM: ORed value of the Ready/Busy Mask Register. 1 = Any device is masked. 0 = All Devices are not Masked. ADS: ORed value of the Sleep Control Register. I = Any device-pair is Controled power-down by bit.2 of the Card Configuration Register. SRESET: Reflects the bit.7 of the Configuration Option Register. CMWP: Reflects the bit.1 of the Write Protection Register. PWDN: Reflects the bit.2 of the Card Configuration Register. CISWP: Reflects the bit.0 of the Write Protection Register. WP: Indicates the Write Protect Switch status. I = Write Protect Switch: ON I = Write Protect Switch: OFF RDY/BSY: Reflects the Ready/Busy Status Register. 1 = All devices are READY. 0 = Any device is BUSY. CPSOOO2.002 @ May. 1991 SHARI= 9. 5 ID242 SERIES PRODUCT 15 Write Protection Register (Address:41 04h) Address Bit.7 Bit.6 Bit.5 4104h CMWP: CISWP: NOTE: Bit.4 Bit.3 Reserved BLKBN: 9. 6 OVERVIEW Bit.2 Bit.1 Bit.0 BLKBN CMWP CISWP Block Locking Enable 1 = Enable Block Locking 0 = All Blocks Unlocked Common Memory Write Protect 1 = Common Memory without CIS region in Write Protect Status Common Memory CIS Write Protect I = Common Memory CIS in Write Protect Status ID242 series ignores BLKBN bit. Block Locking is always enable. Sleep Control Register (Address:41 18h-411 Ah) Address Bit.7 Bit.6 Bit.5 Bit.4 4llAh Bit.3 Bit.2 DEV6/7 DEV4/5 Bit. 1 Bit.0 DEV2/3 DEVO/l Reserved 4118h Reserved DEVlO/ll DEV8/9 1= Select sleep mode device-pair If set to “l”, the corresponding device-pairs are putted into deep power-down by PWDN bit of Configuration Status Register. mode Tl047.01 9. 7 Ready/Busy Mask Register (Address:41 20h-4122h) Address Bit.7 Bit.6 Bit.5 412231 4120h Bit.4 Reserved DEV7 DEV6 Bit.3 DEVll DEV5 DEV4 DEV3 Bit.2 Bit. 1 Bit.0 DEVlO DEV9 DEV8 DEV2 DEVl DEVO 1 =Mask the RdylBsy# The corresponding device’s Rdy/Bsy# signals to set bit are ignored for card’s RDY/BSY# output. T1040.01 9. 8 Ready/Busy Status Register (Address:41 30h-4132h) Address Bit.7 Bit.6 4132h 4130h Bit.5 Bit.4 Reserved DEV7 DEV6 Bit.3 DEVll DEV5 DEV4 1 =READY O=BUSY Each bit indicates the corresponding DEV3 Bit.2 Bit. 1 Bit.0 DEVlO DEV9 DEV8 DEV2 DEVl DEVO device’s Rdy/Bsy# signal. Tl041.01 9. 9 Ready/Busy Mode Register (Address:4140h) Address Bit.7 4140h Bit.6 Bit.5 Bit.4 Reserved RACK: MODE: Bit.3 Bit.2 Bit. 1 RACK Bit.0 MODE Ready Acknowledge Bit Must-clear this bit after receiving ready status to prepare for next device’s ready transition. RDY/BSY# Mode 1 = High-Performance Mode 0 = PCMCIA Mode T1055.01 [email protected] SHARP IO. ID242SERIESPRODUCTOVERVIEW Command Definitions Device operations are determined by writing specific commands to the Command User Interface. Table 9 defines the commands. Table 9. Command Definitions E Read Array / Reset Read Identifier Codes Read Status Register Zlear Status Register WordlByte Operation Data Address FFh (PFl+) 90h (9090h) 1 Second Bus Cycle ( 3peration Write DA 1 Write DA 2 Write DA 70h (707Oh) Write DA 50h (5050h) Write WA 40h (4040h) or 1Oh (1010h) Read 3 Write BA 20h (2020h) Write 3 Write -r First Bus Cycle gate Command Address 1 Data WA 1 WD Read Read I Block Erase Block Erase and Word/Byte Suspend Write 3 Write DA BOh (BOBOh) Block Erase and Word/Byte Resume Write 3 Write DA DOh (DODOh) Write BA 60h (6060h) Write Write DA 60h (6060h) Write Write DA 60h (6060h) Write Set Block Lock-Bit 4 Set Master Lock-Bit Clear Block Lock-Bit Data Address ID =Identifier Address WD =Write Data Address SRD =Data from Status Register IA =Identifier WA =Write BA =Block DA =Device code Address Codes Address Note: 1. Following the Read Identifier master lock codes. Codes command, read operations access manufacture, device, block lock, and 2. Status Register may be read to determine when a write, block erase, or lock bit configuration and whether that operation completed successfully. 3. If the block is locked, block erase or write operations 4. This command is complete, are desabled. is not available. CPSOOOZ-002@ May.1991 SHARP 11. ID242 SERIES PRODUCT OVERVIEW Electrical Specifications 11. 1 Absolute Maximum Ratings NOTES: 1. Operating temperature is for commercial product defined by this specification. 2. All specified voltages are with respect to GND. During transitions, this level may undershoot periods 4!0ns or overshoot to Vcc+2.Ov for periods <20ns. to -2.0~ for Il. 2 Recommended Operating Conditions 11.3 Capacitance Ta=25”C, f=lMHz PARAMETER SYMBOL MIN TYP MAX UNIT CONDITION Input Capacitance cm - 15 - PF v,,=o.ov Input/Output Capacitance C,” - 25 - PF vO,,=O.Ov 11. 4 AC Input/Output Test Conditions Vcc=3.3V-+Q.3V;oy)Lp$iq+~ Vcc=5Vk5% Or vcc=5vs-lo% 3s 1,5 T$q$=XT Figure 5. Transient F,008-0, Input/Output Reference Waveform Figure 8 showsInput/Output level and test level for AC test. Input riseand fall times(10% to 90%) < 10ns. ws""uz-owdMay.199< SHARP ID242 SERIES PRODUCT OVERVIEW 18 12. DC Characteristics (Ta = 0 to 60°C) PARAMETER iYM BOL NOTE -i- nput Low Voltage I nput High Voltage 2 3 nput Low Current nput High Current RI2 jutput Low Voltage TEST CONDITION JOLI 3 2 4,5 VTOHI 4 dOH2 5 jutput High Voltage ‘cc Stand-by Current \,‘cc CCS Deep Power-Down Chrrent I CCD \ ‘cc I CCR 68 I ccw 69 V cc Block Erase or C lear Lock-Bit Current 4 ‘CE 679 Lock Erase Suspend 4 TWS 4 ?xs 6 v ‘cc Read Current Word Write L .ock-Bit Current or Set \ ‘LKO :ontinue to next page 1 T1042-01 CPSOOOZ-0028 May. 199.9 SHARI= DC ID242SERIESPRODUCTOVERVIEW Characteristics T/+KAIVIC (Ta (Continued) ICK , BOL , TE , MIN ry MAX , I ;I;., v k;; 1 UNIT 1 TEST = 0 to 60°C: CONDITION I vrrs vcc or Read \ T,,Stmd-by C :urrent 6 4MB 1 8MB I 0.8 1.6 1OMB 2.0 16MB I 1.6 1.6 20MB 1 I 2.0 mA 2.0 1.6 I I VPF>VCC mA mA 2.0 UA UA ---I \ Ipp Deep C :urrent \ ’ Word L Zk-Bit Power-Down Write Current 6 or Set 6.9 \ I,,,, Block Erase or Cblear Lock-Bit Current 40 6.9 6 VrTLK I Vrr=l2.OVf 4MB 430 430 8MB 500 500 1OMB 530 530 1 I 530 I I 530 2MB I I 0.4 I I 0.4 4MB 1 8MB 1 I 0.8 I I 1.6 I 1.6 I 1 1.5 uA VW5 vcc I VPP>VCC 2.0 1.6 2.0 7,9 UA bA 4 UA 1 0.8 I 1.6 2.0 5% UA ---I UA 500 20MB 16MB Voltage mA 32 400 20MB V Ipp Lockout IVrr=5.0Vt 32 1OMB 10% mA 400 500 10% 40 2MB 16MB v I,+, Word Write or B lock Erase Suspend C ‘urren t vrr=5.0v* 2.0 1 1 1.5 1 v 1 71048-01 NOTE: 1. These parameters are applied to all 2. parameters are applied to An-AZ5 These input pins and and 3. These parameters are applied to CE,#.CEz#,WE#,OE#,REG# 4. These parameters are applied to RDY/BSY#. are applied to Do-D,, 5. These 6. All parameters 7. Block erase, word/byte the VPP Voltage is VPI’I, 8. Automatic operation. currents are Power in RMS unless otherwise write, and lock-bit VFPZ or VFI.I. Savings(APS) reduces in all Do-D,, i/put/output in input pins and output in input mode. mode. RESET. mode. notes. configurations typical are I CCK to 30mA inhibited at Vcc=SV when V,,, and 5 20mA VFPLK, and at Vcc=3.3V guaranteed in in static 9. Sampled. CPSOOO2.002@ May. 1998 ID242 SERIES PRODUCT OVERVIEW 20 13. AC Characteristics Testing Conditions : 1) Input Pulse Level 1.5 to 3.w (@vcc=5v~5%,vcc=5v+10%) 0 to 3.ov (@Vcc=3.3+0.3V) 2) Input Rise/Fall Time 3) Input/Output Timing Ions Reference Level 2.5V (@Vcc=5V~5%,Vcc=SV~lO%) 1.5v (@Vcc=3.3V+O.3V) 4) Output Load (including lTTL+lOOpF scope and jig capacitance) lTTL+SOpF (@VCC=~V+~%,VCC=~V+IO%) (@Vcc=3.3V+O.3V) 13. 1 Common Memory Read Operations (Ta = 0 tc 60°C) SYMBOL PARAMETER IEEE vcc=3.3vi JEIDA/ PCMCIA ON Vcc=SV~ vcc=w-t 5% MIN MAX MIN MAX MIN 250 - 150 - 160 10% ~ Unit MAX Read Cycle Time t AVAV tcR Address Access Time t AVQV t,(A) - 250 - 150 - 160 CE# Access Time tELQV t,(CE) - 250 - 150 - 160 OE# Access Time ... - 1t,(OE) 1 - 1 125 1 - 1 75 1 - 1 80 ItdidCE) 1 - 1 100 1 - 1 75 I - 1 80 Output Disable Time from CEl#,CE2# * kHQz Output Disable Time from OE# * tGHQZ QOE) - 100 - 75 - 80 Output Enable Time from CEI#,CE2# tELQNZ tc,,(CE) 5 - 5 - 5 - WV 0 - 0 - 0 - ns Output Enable Time from OE# Data Valid Time from Address Change +:Time until output become , floating. (The output voltage is not defined.) rio43ai [email protected] 9 SHARP ID242 SERIES PRODUCT OVERVIEW Address CEl#, CE2# OE# Dout Figure 6. AC Waveforms Note) 1. WE# = “HIGH”, 2. Either “HIGH” for Read Operations during a read cycle. or “LOW” in diagonal areas. 3. The output data becomes valid when last interval, ta (A), ta (CE) or ta (OE) have concluded. CPS0002-002QMay.199 SHARP ID242 SERIES PRODUCT OVERVIEW 22 13.2 Command Write Operations : Common Memory 13. 2. 1 WE# Controlled Write Operations (vcc=3.3Vi 0.3VTa=Oto 60°C) PARAMETER Write Cycle Time Address Setup Time Write Recovery Time Data Setup Time for WE# Data Hold Time OE# Hold Time from WE# CE# Setup Time for WE# Address WE# Setup Time for Write Pulse Width WE# High to RDY/BSY# going Low RESET Recovery Time VPP Setup Time VPP Hold Time Word/Byte Write Time Block Erase Time jet Lock-Bit Time Zlear Block Lock-Bits rime vw=3.3v k 0.3% Nor-d I byte Suspend Latency rime to Read Gase Suspend Latency Time o Read t\“HRHI t WHRHZ 10.0 PS 9.3 Ps vw= 12v -t 5% 10.4 PS vpp=3.3vi- 21.1 PS 10% 17.2 l-1 s 5% 17.2 vPP=w+ VPP=5Vt vrr=12v* 10% 0.3% I-is T1044.01 CPSOOOZ-0028 May. 199 SHARI= ID242 SERIES PRODUCT OVERVIEW (Vcc=5Vi 5%, Vcc=5Vi lOsTa = 0 I 60°C) PARAMETER Unit Write Cycle Time ns Address Setup Time ns Write Recovery Time ns Data Setup Time for WE# ns Data Hold Time ns OE# Hold Time from WE# ns CE# Setup Time for WE# ns Address Setup Time for ns WE# Write Pulse Width ns WE# High to RDY/BSY# going Low ns RESET Recovery Time VPP Setup Time PS ns VPP Hold Time ns Word/Byte Write Time PS PS S Block Erase Time S Set Lock-Bit PS Time Clear Block Lock-Bits Time Word I byte Suspend Time to Read Erase Suspend to Read Latency Latency Time r1049-oi CPSOOOZ-0026May.199 SHARP ID242 SERIES PRODUCT 1. 2. OVERVIEW 3. 4. 5. 6. VIH Address Vn. VIH CE#, CE2# VIL hH OE# VTL ‘VALID ~ sm DATA tPHWL hvmL , VOH RDYIB SY# I I VOL VIH RESET VIL IT tQVVL -- VPP I .ZJ VPP FL Figure 7. AC Waveforms for Write Operations (WE# Controlled) Note) While the data signal is in output mode, do not apply an opposite phase input signal. CPS0002.0020May.199 SHARP ID242SERIESPRODUCTOVERVIEW 13. 2. 2 CE# Controlled Write Operations (Vcc=3.3Vt- 0.3\(Ta = Oto 60°C) PARAMETER Write Cycle Time Address Setup Time Write Recovery Time Data Setup Time for CE# Data Hold Time OE# Hold Time from CE# WE# Setup Time for CE# Address CE# Setup Time for Write Pulse Width CE# High to RDY/BSY# going Low RESET Recovery Time VPP Setup Time VPP Hold Time Word/Byte Write Time Block Erase Time Set Lock-Bit Time Clear Block Lock-Bits Time Word I byte Suspend Latency Time to Read Erase Suspend Latency to Read Time tEHRHI tEHRH2 9.3 !JS 5% 10.4 PS 0.3v 21.1 I-1s VPP4V~ 10% vPP=lzv* vpp=3.3v-t Vpr=5VIk 10% 17.2 PS vPP=lzvk 5% 17.2 PS T1045-01 [email protected] J a SHARI= ID242 SERIES PRODUCT OVERVIEW 26 1 (Vcc=5V& 5%, Vcc=SV& IO%, Ta=O to 60°C PARAMETER Write Cycle Time Address Setup Time Write Recovery Time Data Setup Time for CE# Data Hold Time OE# Hold Time from CE# WE# Setup Time for CE# Address CE# Setup Time for Write Pulse Width CE# High to RDY/BSY# going Low RESET Recovery Time VPP Setup Time VPP Hold Time Word/Byte Write Time Block Erase Time Set Lock-Bit Time Clear Block Lock-Bits Time Word I Byte Suspend Time to Read Erase Suspend to Read Latency Latency Time T1046-01 SHARB= ID242 SERIES PRODUCT 1. 3. 2. 27 OVERVIEW 4. 5. Address tcw k,(A) 1 1 tsu(A-CEH) k&E)/ wE# OE# CE#, CE2# DATA tEHRHl.2 k’HEL tEHRL VOH RDYlBSY# I / VOL vm RESET 1 RL %%22 VPP FL 1. 2. 3. 4. 5. 6. v,, tAg~zIzGs9~~//Y V,, POWER-UP AND STANDBY /cl~~~~4tVM~~.17~~~~aj;/~~~~~~M~~.~~~F~P~~q WRITE DATA WRITE OR ERASE SETUP COMMAND 7j;‘Lx++J (,Y~P~~~)‘bfil;f;)‘~~il~~7~~~~~~~ WRITE VALID ADDRESS AND DATA OR ERASE COMFIRM $1/Yi-~~~~~filf$~)A~;C~aa~~ AUTOMATED DATA WRITE OR ERASE DELAY x~-~Jz.b-%7b~~~~~xL READ STATUS REGISTER DATA ~-F-~%~~z+‘~W~&A& WRITE READ ARRAY COMMAND Figure 8. AC Waveforms COMMAND for Write Operations (CE# Controlled) Note) While the data signal is in output mode, do not apply an opposite phase input signal. 6. SHARP ID242 SERIES PRODUCT OVERVIEW Attribute Memory Read Operation 13.3 (Ta=O-60°C) PARAMETER * : Time until becomes floating. (The output voltage Note) When the CIS constructed by EEPROM, T1056-01 is not defined) this card requires 5V voltage for Vcc. Address \ t,(A) e w h(A) 1 \ c / :El#, CE2# / \ ta(CE) OE# i/ ’ / ’ ’ ’ ’ ‘/ ’ / / / \\\\\\\\A L&E) Dout w I t&W t tdOE) ~ f-%%hms Data Output r q&Y-&T High-Inpedance e t&W A is valid F1009-0; I Figure 9. Attribute Memory Read Operation CPSOOOZ-00263May.1996 SHARP 13.4 ID242 SERIES PRODUCT OVERVIEW Attribute Memory Write Operation (Ta=O-60°C) I SYMBOL I vcc=3.3v* PARAMETER 0.3v 1 MAX PCMCIA vcc=.wi 10% MIN 1 Unit MAX I I I ns - I.. Write PulseWidth SetupTime for OE# 1Hold Time for OE# SetupTime for CE# Hold Time for CE# . ..l “.‘\- tWLWH - -- - ‘w(WE) tCHWI twIOE-WE) It 1 , 1.lllr.T “““~I. ,t,II.(OE-\iW tF1 u/H ILfCF.~ tCHEH t,, W _....- ll.... I I 300 150 ns 35 10 ns 35 10 ns 0 35 0 20 ns ns .-\-- .“’ \ - -/ I I T1057-01 Note) When the CIS constructedby EEPROM, this card requires5V voltage for Vcc. \ VIH AIN Address CEl#, CE;?# VIH OE# t,,(OE-WE) VIH WE# DATA F1057-01 Figure 10. Attribute Memory Write Operation SHARP 13.5 ID242 SERIES PRODUCT OVERVIEW Power-Up/Power Down SYMBOL PARAMETER PCMCIA CE# Signal Level (O.OV < Vcc < 2.OV) NOTES MIN 1 0 1 vcco. 1 VIH Vi (CE) CE# Signal Level (2.OV < Vcc < Vin) CE# Signal Level (Vtu < Vcc) CE# Setup Time I tsu WCC) - I I 20 UNITS MAX I I ViMAX V ViMAX V ViMAX V - ms tauWSET) CE# Recover Time treeWCC) - 1.0 - VCC Rising Time b 2 0.1 300 IJS ms VCC Falling Time 2 3.0 300 ms 1 RESET Width tPf tw (RESET) us -I RESET Width th (Hi-Z RESET) - 1 - RESET Width ts (Hi-Z RESET) - 0 - RESET Setup Time I - I 20 10 I - I - ms I ms ms NOTES: 1. ViMAx means Absolute Maximum Voltage for input in the period of O.OV < Vcc < 2.0 V, Vi (CE#) is only o.oov-ViMAX 2. The tpr and tpr are defined as “linear waveforms” in the period of 10% to 90%, or vice-versa. Even if the waveform is not a “liner waveform,” its rising and falling time must meet this specification. e -c- tPr tsu WCC) vcc -)- tsu (RESET) = th (Hi-Z RESET) -- Hi-Z tw (Hi-Z RESET) -3 :Et#, CEa# At- + RESET n ts (Hi-Z RESET) Hi-Z FlOlZ-01 Figure 11. Power- Up/Uown liming CPSOOO2.002 0 May. 1991 SHARI= 14. Specification ID242 SERIES PRODUCT OVERVIEW 31 Changes This datasheet is for ID242 series product overview, and final specifications will be submitted for qualification of the memory card. Please note that contents of this datasheet may be revised without announcement beforehand. Please do NOT finalize a system design with this information. 15. Other Precautions Permanent damage occurs if the memory card is stressed beyond Absolute Maximum Ratings. Operation beyond the Recommended Operating Conditions is not recommended and extended exposure beyond the Recommended Operating Conditions may affect device reliability. Writing to the memory card can be prevented by switching on the write protect switch on the end of the memory card. Avoid allowing the memory card connectors to come in contact with metals and avoid touching the connectors, as the internal circuits can be damaged by static electricity. Avoid storing in direct sunlight, high temperatures (do not place near heaters or radiators), high humidity and dusty areas. Avoid subjecting the memory card to strong physical abuse. Dropping, bending, smashing or throwing the card can result in loss of function. When the memory card is not being used, return it to its protective case. Do not allow the memory card to come in contact with fire. ID242SERIESPRODUCTOVERVIEW 16. External Diagrams 1 0A ENLARGEMEHT of THE WRITE-PROTECT SWITCH - - Protected Aped) (Substrdtc BACK FRONT A--P r- SCALE UNIT A,PPLICIILL mm l/l THICKNESS MATER1 AL CH- DATE FlNISk REVISE MEMORY CHARGl CARD NAt7E OATE Bltla* OLlY I ,997. 9. 8 TRIEFCI(ECR A,rn.l EXTERNAL DIAGRAM I wd matngaa \kU~UydtiA SHARP P~vI*rt PCMCIA Team Ic GROUP CORPORATION oe*v’rc Morn Ret. 2. 0 TYPE1 IMC026-A103 CPSOOO2-002 BY.199