INTEL IMC004FLSA

SERIES 2 FLASH MEMORY CARDS
iMC002FLSA, iMC004FLSA, iMC010FLSA, iMC020FLSA
Extended Temperature Specifications Included
Y
2, 4, 10 and 20 Megabyte Capacities
Y
PCMCIA 2.1/JEIDA 4.1 68-Pin Standard
Ð Hardwired Card Information
Structure
Ð Byte- or Word-Wide Selectable
Y
Y
Component Management Registers for
Card Status/Control and Flexible
System Interface
Automatic Erase/Write
Ð Monitored with Ready/Busy Output
Y
Card Power-Down Modes
Ð Deep-Sleep for Low Power
Applications
Y
Mechanical Write Protect Switch
Y
Solid-State Reliability
Y
Intel FlashFile TM Architecture
Y
High-Performance Read Access
Ð 150 ns Maximum
Y
High-Performance Random Writes
Ð 6 ms Typical Word Write
Y
Erase Suspend to Read Command
Ð Keeps Erase as Background Task
Y
Nonvolatility (Zero Retention Power)
Ð No Batteries Required for Back-up
Y
ETOX TM V 0.4m Flash Memory
Technology
Ð 5V Read, 12V Erase/Write
Ð High-Volume Manufacturing
Experience
Y
Extended Temperature Version
Ð b 40§ C to a 85§ C
Intel’s Series 2 Flash Memory Card facilitates high-performance disk emulation in mobile PCs and dedicated
equipment. Manufactured with Intel’s ETOX TM III 0.8m, FlashFile Memory devices, the Series 2 Card allows
code and data retention while erasing and/or writing other blocks. Additionally, the Series 2 Flash Memory
Card features low power modes, flexible system interfacing and a 150 ns read access time. When coupled with
Intel’s low-power microprocessors, these cards enable high-performance implementations of mobile computers and systems.
Series 2 Cards conform to the Personal Computer Memory Card International Association (PCMCIA 2.1)/Japanese Electronics Industry Development Association (JEIDA 4.1) 68-pin standard, providing electrical and
physical compatibility.
Data file management software, Flash Translation Layer (FTL), provides data file storage and memory management, much like a disk operating system. Intel’s Series 2 Flash Memory Cards, coupled with flash file
management software, effectively provide a removable, all-silicon mass storage solution with higher performance and reliability than disk-based memory architectures.
Designing with Intel’s FlashFile Architecture enables OEM system manufacturers to design and manufacture a
new generation of mobile PCs and dedicated equipment where high performance, ruggedness, long battery
life and lighter weight are a requirement. For large user groups in workstation environments, the Series 2
Cards provide a means to securely store user data and backup system configuration/status information.
December 1996
Order Number: 290434-006
SERIES 2 FLASH MEMORY CARDS
Table 1. Series 2 Flash Memory Card Pinout
Pin
Signal
I/O
Function
Active
Pin
Signal
I/O
Function
Active
1
GND
Ground
35
GND
2
DQ3
I/O
Data Bit 3
36
CD1Ý
O
3
DQ4
I/O
Data Bit 4
37
DQ11
I/O
Data Bit 11
4
DQ5
I/O
Data Bit 5
38
DQ12
I/O
Data Bit 12
5
DQ6
I/O
Data Bit 6
39
DQ13
I/O
Data Bit 13
6
DQ7
I/O
Data Bit 7
40
DQ14
I/O
Data Bit 14
7
CE1Ý
I
Card Enable 1
41
DQ15
I/O
Data Bit 15
8
A10
I
Address Bit 10
42
CE2Ý
I
Card Enable 2
9
OEÝ
I
Output Enable
43
VS1
O
Voltage Sense 1
10
A11
I
Address Bit 11
44
RFU
Reserved
11
A9
I
Address Bit 9
45
RFU
Reserved
12
A8
I
Address Bit 8
46
A17
I
Address Bit 17
13
A13
I
Address Bit 13
47
A18
I
Address Bit 18
14
A14
I
Address Bit 14
48
A19
I
Address Bit 19
15
WEÝ
I
Write Enable
LO
49
A20
I
Address Bit 20
16
RDY/BSYÝ
Ready-Busy
HI/LO
50
A21
I
Address Bit 21
17
VCC
Supply Voltage
51
VCC
18
VPP1
Supply Voltage
52
VPP2
19
A16
I
Address Bit 16
53
A22
I
Address Bit 22
20
A15
I
Address Bit 15
54
A23
I
Address Bit 23
21
A12
I
Address Bit 12
55
A24
I
Address Bit 24
22
A7
I
Address Bit 7
56
A25
23
A6
I
Address Bit 6
57
VS2
O
Voltage Sense 2
24
A5
I
Address Bit 5
58
RST
I
Reset
HI
25
A4
I
Address Bit 4
59
WAITÝ
O
Extend Bus Cycle
LO
26
A3
I
Address Bit 3
60
RFU
27
A2
I
Address Bit 2
61
REGÝ
I
Register Select
Address Bit 1
62
BVD2
O
Batt. Volt Det 2
LO
LO
Ground
Card Detect 1
No Connect
I
A0
I
Address Bit 0
63
BVD1
O
30
DQ0
I/O
Data Bit 0
64
DQ8
I/O
Data Bit 8
31
DQ1
I/O
Data Bit 1
65
DQ9
I/O
Data Bit 9
32
DQ2
I/O
Data Bit 2
66
DQ10
I/O
Data Bit 10
33
WP
O
67
CD2Ý
O
34
GND
68
GND
2
N.C.
Reserved
A1
Ground
N.C.
Supply Voltage
29
HI
LO
Supply Voltage
28
Write Protect
LO
LO
Batt. Volt Det 1
Card Detect 2
Ground
LO
SERIES 2 FLASH MEMORY CARDS
Table 2. Series 2 Flash Memory Card Pin Descriptions
Symbol
A0 –A25
DQ0 –DQ15
Type
Name and Function
I
ADDRESS INPUTS: A0 through A25 are address bus lines which enable direct
addressing of 64 megabytes of memory on a card. A0 is not used in word
access mode. A24 is the most significant address bit. Note: A25 is a no-connect
but should be provided on host side.
I/O
DATA INPUT/OUTPUT: DQ0 through DQ15 constitute the bidirectional data
bus. DQ15 is the most significant bit.
CE1Ý, CE2Ý
I
CARD ENABLE 1, 2: CE1Ý enables even bytes, CE2Ý enables odd bytes.
Multiplexing A0, CE1Ý and CE2Ý allows 8-bit hosts to access all data on DQ0
through DQ7. (See Table 3 for a more detailed description.)
OEÝ
I
OUTPUT ENABLE: Active low signal gating read data from the memory card.
WEÝ
I
WRITE ENABLE: Active low signal gating write data to the memory card.
RDY/BSYÝ
O
READY/BUSY OUTPUT: Indicates status of internally timed erase or write
activities. A high output indicates the memory card is ready to accept
accesses. A low output indicates that a device(s) in the memory card is(are)
busy with internally timed activities. See text for an alternate function (READYBUSY MODE REGISTER).
CD1Ý & CD2Ý
O
CARD DETECT 1, 2: These signals provide for correct card insertion detection.
They are positioned at opposite ends of the card to detect proper alignment.
The signals are connected to ground internally on the memory card and will be
forced low whenever a card is placed in the socket. The host socket interface
circuitry shall supply 10K or larger pull-up resistors on these signal pins.
WP
O
WRITE PROTECT: Write Protect reflects the status of the Write-Protect switch
on the memory card. WP set high e write protected, providing internal
hardware write lockout to the flash array.
VPP1, VPP2
WRITE/ERASE POWER SUPPLY: (12V nominal) for erasing memory array
blocks or writing data in the array. They must be 12V to perform an erase/write
operation.
VCC
CARD POWER SUPPLY (5V nominal) for all internal circuitry.
GND
I
GROUND for all internal circuitry.
REGÝ
I
REGISTER SELECT provides access to Series 2 Flash Memory Card registers
and Card Information Structure in the Attribute Memory Plane.
RST
I
RESET from system, active high. Places card in Power-On Default State.
RESET pulse width must be t 200 ns.
WAITÝ
O
WAIT (Extend Bus Cycle) is used by Intel’s I/O cards and is driven high.
BVD1, BVD2
O
BATTERY VOLTAGE DETECT: Upon completion of the power on reset cycle,
these signals are driven high to maintain SRAM-card compatibility.
RFU
RESERVED FOR FUTURE USE
NC
NO INTERNAL CONNECTION. Pin may be driven or left floating.
VS1, VS2
VOLTAGE SENSE: Notifies the host Socket of the card’s VCC requirements.
VS1 and VS2 are both open, indicating a 5V VCC card.
3
SERIES 2 FLASH MEMORY CARDS
290434 – 3
Figure 1. Detailed Block Diagram. The Card Control Logic Provides
Decoding Buffering and Control Signals.
4
SERIES 2 FLASH MEMORY CARDS
APPLICATIONS
Intel’s second generation Series 2 Flash Memory
Cards facilitate high performance disk emulation for
the storage of data files and application programs on
a purely solid-state removable medium. File management software, Flash Translation Layer (FTL), in
conjunction with the Series 2 Flash Memory Cards,
enable the design of high-performance light-weight
notebook, palmtop, and pen-based PCs that have
the processing power of today’s desktop computers.
Application software stored on the flash memory
card substantially reduces the slow disk-to-DRAM
download process. Replacing the mechanical disk
results in a dramatic enhancement of read performance and substantial reduction of power consumption, size and weightÐconsiderations particularly
important in portable PCs and equipment. The Series 2 Card’s high performance read access time allows the use of Series 2 Cards in an ‘‘execute-inplace’’ (XIP) architecture. XIP eliminates redundancy
associated with DRAM/Disk memory system architectures. Operating systems stored in Flash Memory
decreases system boot or program load times, enabling the design of PCs that boot, operate, store
data files and execute application programs from/to
nonvolatile memory without losing the ability to perform an update.
File management systems modify and store data
files by allocating flash memory space intelligently.
Wear leveling algorithms, employed to equally distribute the number of rewrite cycles, ensure that no
particular block is cycled excessively relative to other blocks. This provides hundreds of thousands of
hours of power on usage.
This file management software enables the user to
interact with the flash memory card in precisely the
same way as a magnetic disk.
Series 2 Flash Memory Cards provide durable nonvolatile memory storage for mobile PCs on the road,
facilitating simple transfer back into the desktop environment.
For systems currently using a static RAM/battery
configuration for data acquisition, the Series 2 Flash
Memory Card’s nonvolatility eliminates the need for
battery backup. The concern for battery failure no
longer exists, an important consideration for portable computers and medical instruments, both requiring continuous operation. Series 2 Cards consume
no power when the system is off, and only 60 mA in
Deep-Sleep mode (2 Megabyte card). Furthermore,
Flash Memory Cards offer a considerable cost and
density advantage over memory cards based on
static RAM with battery backup.
Besides disk emulation, the Series 2 Card’s electrical block-erasure, data writability, and inherent nonvolatility fit well with data accumulation and recording needs. Electrical block-erasure provides design
flexibility to selectively rewrite blocks of data, while
saving other blocks for infrequently updated parameters and lookup tables. For example, networks and
systems that utilize large banks of battery-backed
DRAM to store configuration and status benefit from
the Series 2 Flash Card’s nonvolatility and reliability.
SERIES 2 ARCHITECTURE
OVERVIEW
The Series 2 Flash Memory Card contains a 2 to 20
Megabyte Flash Memory array consisting of 2 to 20
28F008SA FlashFile Memory devices. Each
28F008SA contains sixteen individually-erasable, 64
Kbyte blocks; therefore, the Flash Memory Card
contains from 32 to 320 device blocks. It also contains two Card Control Logic devices that manage
the external interface, address decoding, and component management logic. (Refer to Figure 1 for a
block diagram.)
To support PCMCIA-compatible word-wide access,
devices are paired so that each accessible memory
block is 64 KWords (see Figure 2). Card logic allows
the system to write or read one word at a time, or
one byte at a time by referencing the high or low
byte. Erasure can be performed on the entire block
pair (high and low device blocks simultaneously), or
on the high or low byte portion separately.
Also in accordance with PCMCIA specifications this
product supports byte-wide operation, in which the
flash array is divided into 128K x 8 bit device blocks.
In this configuration, odd bytes are multiplexed onto
the low byte data bus.
5
SERIES 2 FLASH MEMORY CARDS
290434 – 1
Figure 2. Memory Architecture. Each Device Pair Consists of Sixteen 64 KWord Blocks.
Series 2 Flash Memory Cards offer additional features over the Bulk Erase Flash Card product family
(refer
to
iMC001FLKA,
iMC002FLKA
and
iMC004FLKA data sheets). Some of the more notable enhancements include: high density capability,
erase blocking, internal write/erase automation,
erase suspension to read, Component Management
Registers that provide software control of devicelevel functions and a deep-sleep mode.
Erase blocking facilitates solid-state storage applications by allowing selective memory reclamation. Multiple 64 Kbyte blocks may be simultaneously erased
within the memory card as long as not more than
one block per device is erasing. This shortens the
total time required for erasure, but requires additional supply current. A block typically requires 1.6 seconds to erase. Each memory block can be erased
and completely written 100,000 times.
Erase suspend allows the system to temporarily interrupt a block erase operation. This mode permits
reads from alternate device blocks while that same
device contains an erasing block. Upon completion
of the read operation, erasure of the suspended
block must be resumed.
6
Write/erase automation simplifies the system software interface to the card. A two-step command sequence initiates write or erase operations and provides additional data security. Internal device circuits
automatically execute the algorithms and timings
necessary for data-write or block-erase operations,
including verifications for long-term data integrity.
While performing either data-write or block-erase,
the memory card interface reflects this by bringing
its RDY/BSYÝ (Ready/Busy) pin low. This output
goes high when the operation completes. This feature reduces CPU overhead and allows software
polling or hardware interrupt mechanisms. Writing
memory data is achieved in single byte or word increments, typically in 6 ms.
Read access time is 150 ns or less over the entire
operating temperature range.
The Reset-PowerDown mode reduces power consumption to less than 60 mA to help extend battery
life of portable host systems. Activated through software control, this mode optionally affects the entire
flash array (Global Reset-PowerDown Register) or
specific device pairs (Sleep Control Register).
SERIES 2 FLASH MEMORY CARDS
PCMCIA/JEIDA INTERFACE
BATTERY VOLTAGE DETECT
The Series 2 Flash Memory Card interface supports
the PCMCIA 2.1 and JEIDA 4.1 68-pin card format
(see Tables 1 and 2). Detailed specifications are described in the PC Card Standard, Release 2.1, July,
1993, published by PCMCIA. The Series 2 Card conforms to the requirements of both Release 1 and
Release 2 of the PC Card Standard.
PCMCIA requires two signals, BVD1 and BVD2, be
supplied at the interface to reflect card battery condition. Flash Memory Cards do not require batteries.
When the power on reset cycle is complete, BVD1
and BVD2 are driven high to maintain compatibility.
CARD DETECT
Series 2 Card pin definitions are equivalent to the
Bulk-Erase Flash Card except that certain No Connects are now used. A22 through A24, RST (Reset),
and RDY/BSYÝ (Ready/Busy) have pin assignments as set by the PCMCIA standard.
Two signals, CD1Ý and CD2Ý, allow the host to determine proper socket seating. They reside at opposite ends of the connector and are tied to ground
within the memory card.
NOTE: The READY/BUSY signal is abbreviated as
RDY/BSY Ý by PCMCIA (card level) and as
RY/BY Ý by JEDEC (component level).
DESIGN CONSIDERATIONS
The outer shell of the Series 2 card meets all
PCMCIA/JEIDA Type 1 mechanical specifications.
See Figure 19 for mechanical dimensions.
WRITE PROTECT SWITCH
A mechanical write protect switch provides the
card’s memory array with internal write lockout. The
Write-Protect (WP) output pin reflects the status of
this mechanical switch. It outputs a high signal (VOH)
when writes are disabled. This switch does not lock
out writes to the Component Management Registers.
The Series 2 Card consists of two separate memory
planes: the Common Memory Plane (or Main Memory) and the Attribute Memory Plane. The Common
Memory Plane resides in the banks of device pairs
and represents the user-alterable memory space.
The Component Management Registers (CMR) and
the hardwired Card Information Structure (CIS) reside in the Attribute Memory Plane within the Card
Control Logic, as shown in Figure 3. The Card Control Logic interfaces the PCMCIA connector and the
internal flash memory array and performs address
decoding and data control.
Attribute Memory Plane
accessible with
REG (pin 61) e VIL
290434 – 2
INTEL
PCMCIA
e Performance Enhancement Register
e Defined in PCMCIA Release 2.0
Figure 3. Component Management Registers Allow S/W Control of Components within Card
7
SERIES 2 FLASH MEMORY CARDS
ADDRESS DECODE
Address decoding provides the decoding logic for
the 2 to 20 Device Chip Enables and the elements of
the Attribute Memory Plane. REGÝ selects between
the Common Memory Plane (REGÝ e VIH) and the
Attribute Memory Plane (REGÝ e VIL).
NOTE:
The Series 2 Card has active address inputs A0 to
A24 implying that reading and writing to addresses
beyond 32 Megabytes causes wraparound. Furthermore, reads to illegal addresses (for example, between 20 and 32 Meg on a 20 Megabyte card) returns Default data (00FFH or FFFFH).
The 28F008SA devices, storing data, applications or
firmware, form the Common Memory Plane accessed individually or as device pairs. Memory is linearly mapped in the Common Memory Plane. Three
memory access modes are available when accessing the Common Memory Plane: Byte-Wide, Word
Wide, and Odd-Byte modes.
Additional decoding selects the hardwired PCMCIA
CIS and Component Management Registers
mapped in the Attribute Memory Plane beginning at
address 000000H.
8
The 512 memory-mapped even-byte CMRs are linearly mapped beginning at address 4000H in the Attribute Memory Plane.
DATA CONTROL
Data Control Logic selects the path and direction for
accessing the Common or Attribute Memory Plane.
It controls any of the PCMCIA-defined Word-Wide,
Byte-Wide or Odd-Byte modes for either reads or
writes to these areas. As shown in Table 3, input
pins which determine these selections are REGÝ,
A0 through A24, WEÝ, OEÝ, CE1Ý, and CE2Ý.
PCMCIA specifications allow only even-byte access
to the Attribute Memory Plane.
In Byte-Wide mode, bytes contiguous in software actually alternate between two device blocks of a device pair. Therefore, erasure of one device block
erases every other contiguous byte. In accordance
with the PCMCIA standard for memory configuration,
the Series 2 Card does not support confining contiguous bytes within one flash device when in by-8
mode.
SERIES 2 FLASH MEMORY CARDS
Table 3. Data Access Mode Truth Table
Function Mode
REGÝ CEÝ2 CEÝ1 A0 OEÝ WEÝ
VPP2
VPP1
D15 –D8
D7 –D0
COMMON MEMORY PLANE
STANDBY(1)
BYTE READ
X
H
H
X
X
X
VPPL(2) VPPL(2)
HIGH-Z
HIGH-Z
H
H
L
L
L
H
VPPL(2) VPPL(2)
HIGH-Z
EVEN-BYTE
H
H
L
H
L
H
VPPL(2) VPPL(2)
HIGH-Z
ODD-BYTE
ODD-BYTE
EVEN-BYTE
ODD-BYTE
HIGH-Z
WORD READ
H
L
L
X
L
H
VPPL(2) VPPL(2)
ODD-BYTE READ
H
L
H
X
L
H
VPPL(2) VPPL(2)
BYTE WRITE
H
H
L
L
H
L
VPPH
VPPH
X
EVEN-BYTE
H
H
L
H
H
L
VPPH
VPPH
X
ODD-BYTE
WORD WRITE
H
L
L
X
H
L
VPPH
VPPH
ODD-BYTE
EVEN-BYTE
ODD-BYTE WRITE
H
L
H
X
H
L
VPPH VPPL(2)
ODD-BYTE
X
L
L
L
H
X(2)
X(2)
HIGH-Z
EVEN-BYTE
X(2)
ATTRIBUTE MEMORY PLANE
BYTE READ
L
H
L
H
L
H
L
H
X(2)
HIGH-Z
INVALID
WORD READ
L
L
L
X
L
H
X(2)
X(2)
INVALID
DATA(3)
EVEN-BYTE
ODD-BYTE READ
L
L
H
X
L
H
X(2)
X(2)
INVALID
DATA(3)
HIGH-Z
BYTE WRITE
L
H
L
L
H
L
X(2)
X(2)
X
EVEN-BYTE
X(2)
X
INVALID
OPERATION(3)
L
H
L
H
H
L
X(2)
WORD WRITE
L
L
L
X
H
L
X(2)
X(2)
INVALID
OPERATION(3)
EVEN-BYTE
ODD-BYTE WRITE
L
L
H
X
H
L
X(2)
X(2)
INVALID
OPERATION(3)
X
NOTES:
1. Standby mode is valid in Common Memory or Attribute Memory access.
2. To meet the low power specifications, VPP e VPPL; however VPPH presents no reliability problems.
3. Odd-Byte data are not valid during access to the Attribute Memory Plane.
4. H e VIH, L e VIL, X e Don’t Care.
9
SERIES 2 FLASH MEMORY CARDS
PRINCIPLES OF OPERATION
HARDWIRED CIS
Intel’s Series 2 Flash Memory Card provides electrically-alterable, non-volatile, random-access storage.
Individual 28F008SA devices utilize a Command
User Interface (CUI) and Write State Machine
(WSM) to simplify block-erasure and data write operations.
The card’s structure description resides in the evenbyte locations starting at 0000H and going to the
CIS ending tuple (FNULL) within the Attribute Memory Plane. Data included in the hardwired CIS consists of tuples. Tuples are a variable-length list of
data blocks describing details such as manufacturer’s name, the size of each memory device and the
number of flash devices within the card.
COMMON MEMORY ARRAY
Figure 4 shows the Common Memory Plane’s organization. The first block pair (64 KWords) of Common Memory, referred to as the Common Memory
Card Information Structure Block, optionally extends
the hardwired CIS in the Attribute Memory Plane for
additional card information. This may be written during initial card formatting for OEM customization.
Since this CIS Block is part of Common Memory, its
data can be altered. Write access to the Common
Memory CIS Block is controlled by the Write Protect
Control Register which may be activated by system
software after power-up. Additionally, the entire
Common Memory plane (minus the Common Memory CIS Block) may be software write protected. Note
that the Common Memory CIS Block is not part of
the Attribute Memory Plane. Do not assert REG Ý to
access the Common Memory CIS Block .
13FFFFFH
1200000H
COMPONENT MANAGEMENT
REGISTERS (CMRs)
The CMRs in the Attribute Memory Plane provide
special, software-controlled functionality. Card Control Logic includes circuitry to access the CMRs.
REG (PCMCIA, pin 61) selects the Attribute Memory
Plane (and therefore the CMRs) when equal to VIL.
CMRs are classified into two categories: those defined by PCMCIA R2.1 and those included by Intel
(referred to as Performance Enhancement Registers) to enhance the interface between the host system and the card’s flash memory array. CMRs (See
Figure 3) provide seven control functionsÐReadyBusy Interrupt Mode, Device Ready-Busy Status,
Device Ready-Busy Mask, Reset-PowerDown Control, Software-controlled Write Protection, Card
Status and Soft Reset.
Device Pair 9
1000000H
Device Pair 8
SOFT RESET REGISTER (PCMCIA)
0E00000H
Device Pair 7
(CONFIGURATION OPTION)
0C00000H
Device Pair 6
0A00000H
Device Pair 5
0800000H
Device Pair 4
The SOFT RESET REGISTER (Attribute Memory
Plane Address 4000H, Figure 5) is defined in the
PCMCIA Release 2.0 specification as the Configuration Option Register.
0600000H
Device Pair 3
0400000H
Device Pair 2
0200000H
Device Pair 1
0020000H
Device Pair 0
Optional CIS
0000000H
Figure 4. Common Memory Plane. Use
the Optional Common Memory Plane
CIS for Custom Card Format Information.
Bit 7 is the soft reset bit (SRESET). Writing a 1 to
this bit initiates card reset to the power-on default
state (see Side Bar page 11). This bit must be
cleared to use the CMRs or to access the devices.
SRESET implements in software what the reset pin
implements in hardware. On power-up, the card automatically assumes default conditions. Similar to
the reset pin (pin 58), this bit clears at the end of a
power-on reset cycle or a system reset cycle.
Bits 0 through 6 are not used by this memory card,
but power up as zeroes for PCMCIA compatibility.
10
SERIES 2 FLASH MEMORY CARDS
SOFT RESET REGISTER
(CONFIGURATION OPTION REGISTER)
(Read/Write Register)
ADDRESS
BIT 7
BIT 6
4000H
SRESET
BIT 5
BIT 4
BIT 4
BIT 2
BIT 1
BIT 0
PCMCIA CONFIGURATION INDEX
RESETS TO ZERO ON POWER UP
1 e RESET, CLEAR TO ACCESS CARD
Figure 5. SOFT RESET REGISTER (PCMCIA). Sets the Memory Card in the Power-On Default State.
Global PowerDown Register (PCMCIA)
(Configuration and Status)
POWER-ON DEFAULT CONDITIONS
#
#
#
#
#
The Global Reset-PowerDown Register (Attribute
Memory Plane Address 4002H, Figure 6) is referred
to as the Configuration and Status Register in the
PCMCIA Release 2.0 specification.
All Devices Powered Up In Standby Mode
Common Memory Available For Writes
All Device Ready/Busy Outputs Unmasked
PCMCIA Ready/Busy Mode Enabled
Ready/Busy Output Goes To Ready
Bit 2 (RP) controls global card power-down. Writing
a 1 to this bit places each device within the card into
‘‘Deep-Sleep’’ mode. Devices in Deep-Sleep are not
accessible. Recovery from power-down requires
500 ns for reads and 1 ms for writes.
The RP bit defaults to 0 on card power-up or reset.
Setting or clearing this bit has no affect on the bit
settings of the Sleep Control Register.
The remaining Global Reset-PwrDwn Register bits
are defined for Intel’s family of I/O cards and are
driven low for compatibility.
GLOBAL RESET-POWER-DOWN REGISTER
(CONFIGURATION AND STATUS REGISTER)
(Read/Write Register)
1 e POWER DOWN
ADDRESS
4002H
BIT 7
BIT 6
BIT 5
ZEROES
BIT 4
BIT 3
BIT 2
RP
BIT 1
BIT 0
ZEROES
Figure 6. GLOBAL RESET-PWRDWN REGISTER (PCMCIA). The RP
Bit Enables Reset PowerDown of All Flash Memory Devices.
11
SERIES 2 FLASH MEMORY CARDS
CARD STATUS REGISTER
(Read Only Register)
ADDRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
4100H
ADM
ADS
SRESET
CMWP
RP
CISWP
WP
RDY/BSYÝ
Figure 7. CARD STATUS REGISTER (Intel) Provides a Quick Review of the Card’s Status
CARD STATUS REGISTER (INTEL)
The Read-Only, CARD STATUS REGISTER (Attribute Memory Plane Address 4100H, Figure 7) returns generalized status of the Series 2 Card and its
CMRs.
Bit 0 (RDY/BSYÝ) reflects the card’s RDY/BSYÝ
(Ready-Busy) output. Software polling of this bit provides data-write or block-erase operation status. A
zero indicates a busy device(s) in the card.
Bit 1 (WP) reports the position of the card’s Write
Protection switch with 1 indicating write protected. It
reports the status of the WP pin.
Bit 2 (CISWP) reflects whether the Common Memory CIS is write protected using the WRITE PROTECT
REGISTER, with 1 indicating write protected.
Bit 3 (RP) reports whether the entire flash memory
array is in ‘‘Deep-Sleep’’ (Reset-PwrDwn) mode,
with 1 indicating ‘‘Deep-Sleep’’. This bit reflects the
RP bit of the GLOBAL RESET-POWERDOWN REGISTER. Powering down all device pairs individually
(using the Sleep Control Register), also sets this bit.
Bit 4 (CMWP) reports whether the Common Memory
Plane (minus Common Memory CIS) is write protected via the WRITE PROTECT REGISTER with 1 indicating write protected.
Bit 5 (SRESET) reflects the SRESET bit of the SOFT
RESET REGISTER. It reports that the card is in Soft
12
Reset with 1 indicating reset. When this bit is zero,
the flash memory array and CMRs may be accessed, otherwise clear it via the SRESET REGISTER.
Bit 6 (ADS, ANY DEVICE SLEEP) is the ‘‘ORed’’
value of the SLEEP CONTROL REGISTER. Powering down any device pair sets this bit.
Bit 7 (ADM, ANY DEVICE MASKED) is the ‘‘ORed’’
value of the READY/BUSY MASK REGISTER.
Masking any device sets this bit.
WRITE PROTECTION REGISTER
(INTEL)
The WRITE PROTECTION REGISTER (Attribute
Memory Plane Address 4104H, Figure 8) selects
whether the optional Common Memory CIS and the
remaining Common Memory blocks are write protected (see Figure 4).
Enable Common Memory CIS write protection by
writing a 1 to the CISWP Bit (bit 0).
Enable write protection of the remaining Common
Memory blocks by writing a 1 to the CMWP Bit (bit
1).
In the power-on default state, both bits are 0, and
therefore not write protected.
Reserved bits (2 – 7) have undefined values and
should be written as zeroes for future compatibility.
SERIES 2 FLASH MEMORY CARDS
WRITE PROTECTION REGISTER
(Read/Write Register)
ADDRESS
BIT 7
4104H
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
RESERVED FOR FUTURE USE
BIT 1
BIT 0
CMWP
CISWP
1 e WRITE PROTECT
Figure 8. WRITE PROTECTION REGISTER (Intel) Eliminates Accidental Data Corruption
Sleep Control Register will remain unchanged after
returning from a global reset and power down (writing a zero to the RP bit of the Global Reset-PowerDown Register).
SLEEP CONTROL REGISTER (INTEL)
Unlike the GLOBAL RESET-POWERDOWN REGISTER, which simultaneously resets and places all
flash memory devices into a Deep-Sleep mode, the
SLEEP CONTROL REGISTER (Attribute Memory
Plane Address 4118H–411AH, Figure 9) allows selective power-down control of individual device pairs.
READY-BUSY STATUS
REGISTER (INTEL)
The bits in the Read-only, READY-BUSY Status
Register (Attribute Memory Plane Address 4130H4134H, Figure 10) reflect the status (READY e 1,
BUSY e 0) of each device’s RY/BYÝ output. A busy
condition indicates that a device is currently processing a data-write or block-erase operation.
Writing a 1 to a specific bit of the SLEEP CONTROL
REGISTER places the corresponding device pair
into the ‘‘Deep-Sleep’’ mode. Devices in Deep-Sleep
are not accessible . On cards with fewer than
20 Megabytes (10 device pairs), writing a one to an
absent device pair has no affect and reads back as
zero.
These bits are logically ‘‘AND-ed’’ to form the
Ready/Busy output (RDY/BSYÝ, pin 16) of the
PCMCIA interface. On memory cards with fewer
than 20 devices, unused Device RY/BYÝ Status
Register bits appear as ready.
This register contains all zeroes (i.e., not in DeepSleep mode) when the card powers up or after a
hard or soft reset. Furthermore, the Global ResetPowerDown Register has no affect on the contents
of this register. Therefore, any bit settings of the
SLEEP CONTROL REGISTER
(Read/Write Register)
ADDRESS
BIT 7
BIT 6
411AH
4118H
BIT 5
BIT 4
BIT 3
BIT 2
RESERVED
DEVICES
14/15
DEVICES
12/13
DEVICES
10/11
DEVICES
8/9
DEVICES
6/7
DEVICES
4/5
BIT 1
BIT 0
DEVICES
18/19
DEVICES
16/17
DEVICES
2/3
DEVICES
0/1
1 e SELECTED DEVICE PAIR IN POWER-DOWN MODE AND RESET
Figure 9. SLEEP CONTROL REGISTER (Intel) Allows Specific
Devices to be Reset and Put into Power-Down Mode
13
SERIES 2 FLASH MEMORY CARDS
READY-BUSY STATUS REGISTER
(Read/Write Register)
ADDRESS
BIT 7
BIT 6
4134H
4132H
4130H
BIT 5
BIT 4
RESERVED
BIT 3
BIT 2
BIT 1
BIT 0
DEVICE
DEVICE
DEVICE
DEVICE
19
18
17
16
DEVICE
DEVICE
DEVICE
DEVICE
DEVICE
DEVICE
DEVICE
DEVICE
15
14
13
12
11
10
9
8
DEVICE
DEVICE
DEVICE
DEVICE
DEVICE
DEVICE
DEVICE
DEVICE
7
6
5
4
3
2
1
0
1 e DEVICE READY, 0 e DEVICE BUSY
Figure 10. READY-BUSY STATUS REGISTER (Intel) Provides
Operation Status of All Flash Memory Devices
In an unmasked condition (MASK REGISTER bits e
0), any device RY/BYÝ output going low pulls the
card’s RDY/BSYÝ output to VIL (BUSY). In this
case, all devices must be READY to allow the card’s
RDY/BSYÝ output to be ready (VIH). This is referred
to as the PCMCIA READY-BUSY MODE. An alternate type of READY-BUSY function is described in
the next section, READY-BUSY MODE REGISTER.
READY-BUSY MASK REGISTER
(INTEL)
The bits of the Read/Write READY-BUSY MASK
REGISTER (Attribute Memory Plane Address
4120H–4124H, Figure 11) mask out the corresponding ‘‘AND-ed’’ READY-BUSY STATUS REGISTER
bits from the PCMCIA data bus (RDY/BSYÝ, pin 16)
and the CARD STATUS REGISTER RDY/BSYÝ Bit
(bit 0).
READY-BUSY MASK
(Read/Write Register)
ADDRESS
BIT 7
BIT 6
4124H
4122H
4120H
BIT 5
BIT 4
RESERVED
BIT 3
BIT 2
BIT 1
BIT 0
DEVICE
DEVICE
DEVICE
DEVICE
19
18
17
16
DEVICE
DEVICE
DEVICE
DEVICE
DEVICE
DEVICE
DEVICE
DEVICE
15
14
13
12
11
10
9
8
DEVICE
DEVICE
DEVICE
DEVICE
DEVICE
DEVICE
DEVICE
DEVICE
7
6
5
4
3
2
1
0
1 e MASK ENABLED
Figure 11. READY-BUSY MASK REGISTER (Intel) Essential for Write Optimization
14
SERIES 2 FLASH MEMORY CARDS
If the READY-BUSY MASK REGISTER bits are set
to ones (masked condition), the RDY/BSYÝ output
and the CARD STATUS REGISTER RDY/BSYÝ bit
will reflect a READY condition regardless of the
state of the corresponding devices. The READYBUSY MASK REGISTER does not affect the
READY-BUSY STATUS REGISTER allowing software polling to determine operation status.
system with immediate notification that a specific
device’s operation has completed and that device may now be used. This is particularly useful
in a file management application where a block
pair, containing only deleted files, is being erased
to free up space so new file data may be written.
Enabling the HIGH-PERFORMANCE READY-BUSY
MODE requires a three step sequence:
1. Set all bits in the READY/BUSY MASK REGISTER. This prevents ready devices from triggering
an unwanted interrupt when step 3 is performed.
Unmasked is the default condition for the bits in this
register. On memory cards with fewer than 20 devices, unused device mask bits appear as masked.
2. Write 01H to the READY-BUSY MODE REGISTER. This sets the MODE bit.
READY-BUSY MODE REGISTER
(INTEL)
3. Write 01H to the READY-BUSY MODE REGISTER. This clears the RACK bit.
The READY-BUSY MODE REGISTER (Attribute
Memory Plane Address 4140H, Figure 12) provides
the selection of two types of system interfacing for
the busy-to-ready transition of the card’s
RDY/BSYÝ pin:
1. The standard PCMCIA READY-BUSY MODE, in
which the card’s RDY/BSYÝ signal generates a
low-to-high transition (from busy to ready) only
after all busy devices (not including masked
devices) have completed their data-write or blockerase operations. This may result in a long interrupt latency.
2. A High-Performance mode that generates a lowto-high (from busy-to-ready) transition after each
device becomes ready. This provides the host
The MODE and RACK bits must be written in the
prescribed sequence, not simultaneously. The
card’s circuitry is designed purposely in this manner
to prevent an initial, unwanted busy-to-ready transition. Note that in Step 2, writing to the RACK bit is
a Don’t Care.
When the High-Performance Mode is enabled, specific READY-BUSY MASK bits must be cleared after
an operation is initiated on the respective devices.
After each device becomes ready, the RDY/BSYÝ
pin makes a low-to-high transition. To catch the next
device’s completion of an operation, the RACK bit
must be cleared by writing ‘‘01H’’ to the Ready/Busy
Mode Register.
READY-BUSY MODE REGISTER
(Read/Write Register)
ADDRESS
4140H
BIT 7
BIT 6
BIT 5
BIT 4
RESERVED FOR FUTURE USE
BIT 3
BIT 2
BIT 1
BIT 0
RACK
MODE
MODE e READY-BUSY MODE
0 e PCMCIA MODE
1 e HIGH PERFORMANCE
RACK e READY ACKNOWLEDGE CLEAR TO
SET UP RDY/BSYÝ PIN, THEN CLEAR AFTER
EACH DEVICE BECOMES READY TO ACKNOWLEDGE TRANSITION.
Figure 12. High Performance Ready-Busy Mode REGISTER (Intel)
Used to Trigger a Ready Interrupt for Each Device
15
SERIES 2 FLASH MEMORY CARDS
PRINCIPLES OF DEVICE OPERATION
Individual 28F008SA devices include a Command
User Interface (CUI) and a Write State Machine
(WSM) to manage write and erase functions in each
device block.
The CUI serves as the device’s interface to the Card
Control Logic by directing commands to the appropriate device circuitry (Table 4). It allows for fixed
power supplies during block erasure and data writes.
The CUI handles the WEÝ interface into the device
data and address latches, as well as system software requests for status while the WSM is operating.
The CUI itself does not occupy an addressable
memory location. The CUI provides a latch used to
store the command and address and data information needed to execute the command. Erase Setup
and Erase Confirm commands require both appropriate command data and an address within the block
to be erased. The Data Write Setup command requires both appropriate command data and the address of the location to be written, while the Data
Write command consists of the data to be written
and the address of the location to be written.
The CUI initiates flash memory writing and erasing
operations only when VPP is at 12V. Depending on
the application, the system designer may choose to
make the VPP power supply switchable (available
when writes and erases are required) or hardwired to
VPPH. When VPP e VPPL, power savings are incurred and memory contents cannot be altered. The
CUI architecture provides protection from unwanted
write and erase operations even when high voltage
is applied to VPP. Additionally, all functions are disabled whenever VCC is below the write lockout voltage VLKO, or when the card’s Deep-Sleep modes
are enabled. The WSM automates the writing and
erasure of blocks within a device. This on-chip state
machine controls block erase and data-write, freeing
the host processor for other tasks. After receiving
the Erase Setup and Erase Confirm commands from
the CUI, the WSM controls block-erase. Progress is
monitored via the device’s status register, the card’s
control logic, and the RDY/BSYÝ pin of the
PCMCIA interface. Data-write is similarly controlled,
after destination address and expected data are
supplied.
Table 4. Device Command Set
28F008SA Command(1)
First Bus Ccyle
Second Bus Cycle
Bus
Cycles
Data
Data
(2)
Operation Addr(2)
Req’d Operation Addr
x8 Mode x16 Mode
x8 Mode x16 Mode
Read Array/Reset
1
Write
DA
FFH
FFFFH
Intelligent Identifer
3
Write
DA
90H
9090H
Read
IA
IID(3)
IID(3)
Read Device Status Register
2
Write
DA
70H
7070H
Read
DA
SRD(4)
SRD(4)
Clear Device Status Register
1
Write
DA
50H
5050H
Erase Setup/Erase Confirm
2
Write
BA
20H
2020H
Write
BA
D0H
D0D0H
Erase Suspend/
Erase Resume
2
Write
DA
B0H
B0B0H
Write
DA
D0H
D0D0H
Write Setup/Write
2
Write
WA
40H
4040H
Write
WA
WD(5)
WD(5)
Alternate Write Setup/Write(6)
2
Write
WA
10H
1010H
Write
WA
WD(5)
WD(5)
NOTES:
1. Commands other than those shown above are reserved by Intel for future device implementations and should not be
used.
2. DA e A device-level (or device pair) address within the card.
BA e Address within the block of a specific device (device pair) being erased.
WA e Address of memory location to be written.
IA e A device-level address; 00H for manufacturer code, 01 for device code.
3. Following the intelligent identifier command, two read operations access manufacturer (89H) and device codes (A2H).
4. SRD e Data read from Device Status Register.
5. WD e Data to be written at location WA. Data is latched on the rising edge of WEÝ.
6. Either 40H or 10H are recognized by the WSM as the Write Setup command.
16
SERIES 2 FLASH MEMORY CARDS
COMMAND DEFINITIONS
Read Array (FFH) Ð
Upon initial card power-up, after exit from the DeepSleep modes, and whenever illegal commands are
given, individual devices default to the Read Array
mode. This mode is also entered by writing FFH into
the CUI. In this mode, microprocessor read cycles
retrieve array data. Devices remain enabled for
reads until the CUI receives an alternate command.
Once the internal WSM has started a block-erase or
data-write operation within a device, that device will
not recognize the Read Array command until the
WSM has completed its operation (or the Erase Suspend command is issued during erase).
Intelligent Identifier (90H) Ð
After executing this command, the intelligent identifier values can be read. Only address A0 of each device is used in this mode, all other address inputs
are reserved and should be cleared to 0. [(Manufacturer code e 89H for A0 e 0), (Device code e A2H
for A0 e 1)] . The device will remain in this mode
until the CUI receives another command.
This information is useful by system software in determining what type of flash memory device is contained within the card and allows the correct matching of device to write and erase algorithms. System
software that fully utilizes the PCMCIA specification
will not use the intelligent identifier mode, as this
data is available within the Card Information Structure (refer to section on PCMCIA Card Information
Structure).
Read Status Register (70H)
After writing this command, a device read outputs
the contents of its Status Register, regardless of the
address presented to that device. The contents of
this register are latched on the falling edge of OEÝ,
CE1Ý (and/or CE2Ý), whichever occurs last in the
read cycle. This prevents possible bus errors which
might occur if the contents of the Status Register
changed while reading its contents. CE1Ý (and
CE2Ý for odd-byte or word access) or OEÝ must be
toggled with each subsequent status read, or the
completion of a write or erase operation will not be
evident. This command is executable while the
WSM is operating, however, during a block-erase or
data-write operation, reads from the device will auto-
matically return status register data. Upon completion of that operation, the device remains in the
Status Register read mode until the CUI receives
another command.
The read Status Register command functions when
VPP e VPPL or VPPH.
Clear Status Register (50H)
The Erase Status and Write Status bits may be set
to ‘‘1’’s by the WSM and can only be reset by the
Clear Status Register Command. These bits indicate
various failure conditions. By allowing system software to control the resetting of these bits, several
operations may be performed (such as cumulatively
writing several bytes or erasing multiple blocks in
sequence). The device’s Status Register may then
be polled to determine if an error occurred during
that sequence. This adds flexibility to the way the
device may be used.
Additionally, the VPP Status bit (SR.3) MUST be reset by system software (Clear Status Register command) before further block-erases are attempted
(after an error).
The Clear Status Register command functions when
VPP e VPPL or VPPH. This command puts the device
in the Read Array mode.
Write Setup/Write
A two-command sequence executes a data-write
operation. After the system switches VPP to VPPH,
the write setup command (40H) is written to the CUI
of the appropriate device, followed by a second
write specifying the address and write data (latched
on the rising edge of WEÝ). The device’s WSM controls the data-write and write verify algorithms internally. After receiving the two-command write sequence, the device automatically outputs Status
Register data when read (see Figure 13). The CPU
detects the completion of the write operation by analyzing card-level or device-level indicators. Cardlevel indicators include the RDY/BSYÝ pin and the
READY-BUSY STATUS REGISTER; while devicelevel indicators include the specific device’s Status
Register. Only the Read Status Register command
is valid while the write operation is active. Upon
completion of the data-write sequence (see section
on Status Register) the device’s Status Register reflects the result of the write operation. The device
remains in the Read Status Register mode until the
CUI receives an alternate command.
17
SERIES 2 FLASH MEMORY CARDS
Erase Setup/Erase Confirm
Commands (20H)
Erase Suspend (B0H)/Erase Resume
(D0H)
Within a device, a two-command sequence initiates
an erase operation on one device block at a time.
After the system switches VPP to VPPH, an Erase
Setup command (20H) prepares the CUI for the
Erase Confirm command (D0H). The device’s WSM
controls the erase algorithms internally. After receiving the two-command erase sequence, the device
automatically outputs Status Register data when
read (see Figure 14). If the command after erase
setup is not an Erase Confirm command, the CR
sets the Write Failure and Erase Failure bits of the
Status Register, places the device into the Read
Status Register mode, and waits for another command. The Erase Confirm command enables the
WSM for erase (simultaneously closing the address
latches for that device’s block (A16 –A19). The CPU
detects the completion of the erase operation by analyzing card-level or device-level indicators. Cardlevel indicators include the RDY/BSY pin and the
READY-BUSY STATUS REGISTER; while devicelevel indicators include the specific device’s Status
Register. Only the Read Status Register and Erase
Suspend command is valid during an active erase
operation. Upon completion of the erase sequence
(see section on Status Register) the device’s Status
Register reflects the result of the erase operation.
The device remains in the Read Status Register
mode until the CUI receives an alternate command.
Erase Suspend allows block erase interruption to
read data from another block of the device or to
temporarily conserve power for another system operation. Once the erase process starts, writing the
Erase Suspend command to the CUI (see Figure 15)
requests the WSM to suspend the erase sequence
at a predetermined point in the erase algorithm. In
the erase suspend state, the device continues to
output Status Register data when read.
The two-step block-erase sequence ensures that
memory contents are not accidentally erased. Erase
attempts while VPPL k VPP k VPPH produce spurious results and are not recommended. Reliable
block erasure only occurs when VPP e VPPH. In the
absence of this voltage, memory contents are protected against erasure. If block erase is attempted
while VPP e VPPL, the VPP Status bit will be set to
‘‘1’’.
When erase completes, the Erase Status bit should
be checked. If an erase error is detected, the device’s Status Register should be cleared. The CUI
remains in Read Status Register mode until receiving an alternate command.
18
Polling the device’s RY/BYÝ and Erase Suspend
Status bits (Status Register) will determine when the
erase suspend mode is valid. It is important to note
that the card’s RDY/BSYÝ pin will also transition to
VOH and will generate an interrupt if this pin is connected to a system-level interrupt. At this point, a
Read Array command can be written to the device’s
CUI to read data from blocks other than those
which are suspended. The only other valid commands at this time are Read Status Register (70H)
and Erase Resume (D0H). If VPP goes low during
Erase Suspend, the VPP Status bit is set in the
Status Register and the erase operation is aborted.
The Erase Resume command clears the Erase Suspend state and allows the WSM to continue with the
erase operation. The device’s RY/BYÝ Status and
Erase Suspend Status bits and the card’s READYBUSY Status Register are automatically updated to
reflect the erase resume condition. The card’s RDY/
BSYÝ pin also returns to VOL.
Invalid/Reserved
These are unassigned commands having the same
effect as the Read Array command. Do not issue
any command other than the valid commands specified above. Intel reserves the right to redefine these
codes for future functions.
SERIES 2 FLASH MEMORY CARDS
DEVICE STATUS REGISTER
Bit 5ÐErase Status
Each 28F008SA device in the Series 2 Card contains a Status Register which displays the condition
of its Write State Machine. The Status Register is
read at any time by writing the Read Status command to the CUI. After writing this command, all subsequent Read operations output data from the
Status Register, until another command is written to
the CUI.
This bit will be cleared to 0 to indicate a successful
block-erasure. When set to a ‘‘1’’, the WSM has
been unsuccessful at performing an erase verification. The device’s CUI only resets this bit to a ‘‘0’’ in
response to a Clear Status Register command.
Bit 7ÐWSM Status
This bit reflects the Ready/Busy condition of the
WSM. A ‘‘1’’ indicates that read, block-erase or
data- write operations are available. A ‘‘0’’ indicates
that write or erase operations are in progress.
Bit 4ÐWrite Status
This bit will be cleared to a 0 to indicate a successful
data-write operation. When the WSM fails to write
data after receiving a write command, the bit is set
to a ‘‘1’’ and can only be reset by the CUI in response to a Clear Status Register command.
Bit 3ÐVPP Status
Bit 6ÐErase Suspend Status
If an Erase Suspend command is issued during the
erase operation, the WSM halts execution and sets
the WSM Status bit and the Erase Suspend Status
bit to a ‘‘1’’. This bit remains set until the device
receives an Erase Resume command, at which point
the CUI resets the WSM Status bit and the Erase
Suspend Status bit.
During block-erase and data-write operations, the
WSM monitors the output of the device’s internal
VPP detector. In the event of low VPP, the WSM sets
(‘‘1’’) the VPP Status bit, the status bit for the operation in progress (either write or erase). The CUI resets these bits in response to a Clear Status Register command. Also, the WSM RY/BYÝ bit will be set
to indicate a device ready condition. This bit MUST
be reset by system software (Clear Status Register
command) before further data writes or block erases
are attempted.
Device Status Register (Read Only Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
WSM
Status
Erase
Suspend
Status
Erase
Status
Write
Status
VPP
Status
Bit 2
Bit 1
Bit 0
Reserved
19
SERIES 2 FLASH MEMORY CARDS
Bus
Operation
Command
x8 Mode
x16 Mode
Write
Write Setup
Write
Data Write
Data e 40H
Address e Byte
Within Card to be
Written
Data to be Written
Address e Byte
Within Card to be
Written
Data e 4040H
Address e Word
Within Card to be
Written
Data to be Written
Address e Word
Within Card to be
Written
Read
Defaults to
Status Register
Status Register
Device Sta- Data. Toggle OEÝ, Data. Toggle OEÝ or
(CE1Ý and CE2Ý)
tus Register CE1Ý or CE2Ý to
Read Mode
update Status
to update Status
Register
Registers
Standby
Check SR Bit 7
1 e Ready,
0 e Busy
Check SR Bits
7 and 15
1 e Ready,
0 e Busy
x8 Mode
x16 Mode
Standby
Check SR Bit 3
1 e VPP Detected
Low
Check SR Bits
3 and 11
1 e VPP Detected
Low
Standby
Check SR Bit 4
1 e Data Write Error
Check SR Bits
4 and 12
1 e Data Write Error
290434 – 17
FULL STATUS CHECK
PROCEDURE
Bus
Command
Operation
290434 – 18
Figure 13. Device-Level Automated Write Algorithm
NOTES:
1. Repeat for subsequent data writes.
2. In addition, the card’s READY-BUSY STATUS REGISTER or the RDY/BSYÝ pin may be used.
3. Full device-level status check can be done after each data write or after a sequence of data writes.
4. Write FFH (or FFFFH) after the last data write operation to reset the device(s) to Read Array Mode.
5. If a data write operation fails due to a low VPP (setting SR Bit 3), the Clear Status Register command MUST be issued
before further attempts are allowed by the Write State Machine.
6. If a data write operation fails during a multiple write sequence, SR Bit 4 (Write Status) will not be cleared until the
Command User Interface receives the Clear Status Register command.
20
SERIES 2 FLASH MEMORY CARDS
Bus
Command
Operation
x8 Mode
x16 Mode
Write
Erase
Setup
Data e 20H
Address e Block
Within Card to be
Erased
Data e 2020H
Address e Block Pair
Within Card to be
Erased
Write
Erase
Data e D0H
Address e Block
Within Card to be
Erased
Data e D0D0H
Address e Block
Pair Within Card to
be Erased
Read
Defaults to
Status Register
Device Sta- Data. Toggle OEÝ,
tus Register CE1Ý or CE2Ý to
Read Mode
update Status
Register
Standby
Check SR Bit 7
1 e Ready,
0 e Busy
Status Register
Data. Toggle OEÝ or
(CE1Ý and CE2Ý)
to update Status
Register
Check SR Bits 7 and 15
1 e Ready,
0 e Busy
290434 – 19
FULL STATUS CHECK PROCEDURE
Bus
Command
Operation
Standby
Standby
Standby
x8 Mode
x16 Mode
Check SR Bit 3
1 e VPP Detected
Low
Check SR Bits
3 and 11
Either Bit 1 e VPP
Detected Low
Check SR Bits 4 and 5 Check SR Bits 4, 5,
12, 13
Both 1 e Command
Sequence Error
All 1 e Command
Sequence Error
Check SR Bit 5
1 e Block Erase
Error
Check SR Bits
5 and 13
Both 1 e Block
Erase Failure
290434 – 20
Figure 14. Device-Level Automated Erase Algorithm
NOTES:
1. Repeat for subsequent data writes.
2. In addition, the card’s READY-BUSY STATUS REGISTER or the RDY/BSYÝ pin may be used.
3. Full device-level status check can be done after each block erase or after a sequence of block erases.
4. Write FFH (or FFFFH) after the last block erase operation to reset the device(s) to Ready Array Mode.
5. If a block erase operation fails due to a low VPP (setting SR Bit 3), the Clear Status Register command MUST be issued
before further attempts are allowed by the Write State Machine.
6. If a block erase operation fails during a multiple block erase sequence, SR Bit 4 (Write Status) will not be cleared until the
Command User Interface receives the Clear Status Register command.
21
SERIES 2 FLASH MEMORY CARDS
Bus
Operation
Command
x8 Mode
x16 Mode
Suspend
Erase
Data e B0H,
Address e Desired
Block to Erase
Suspend
Data e B0B0H,
Address e Desired
Block Pair to Erase
Suspend
Read
Status Register
Data. Toggle OEÝ,
CE1Ý or CE2Ý to
update Status
Register
Status Register
Data. Toggle OEÝ or
(CE1Ý and CE2Ý)
to update Status
Register
Standby
Check SR Bit 7
1 e Ready,
0 e Busy
Check SR Bit 7 and 15
1 e Ready,
0 e Busy
Standby
Check SR Bit 6
1 e Suspended,
0 e In Progress
Check SR Bit 6 and 14
1 e Suspended,
0 e In Progress
Data e FFH
Data e FFFFH
Read Data
until finished
Read Data
until finished
Data e D0H,
Address e Valid
Block Address.
Data e D0D0H,
Address e Valid
Block Pair Address.
Write
Write
Rd Array
Cmd
Read
Write
Erase
Resume
290434 – 27
Figure 15. Erase Suspend/Resume Algorithm. Allows Reads to Interrupt Erases.
POWER CONSUMPTION
STANDBY MODE
In most applications, software will only be accessing
one device pair at a time. The Series 2 Card is defined to be in the standby mode when one device
pair is in the Read Array Mode while the remaining
devices are in the Deep-Sleep Mode. The Series 2
Card’s CE1Ý and CE2Ý input signals must also be
at VIH. In standby mode, much of the card’s circuitry
is shut off, substantially reducing power consumption. Typical power consumption for a 20 Megabyte
Series 2 card in standby mode is 65 mA.
22
SLEEP MODE
Writing a ‘‘1’’ to the PWRDWN bit of the GLOBAL
POWERDOWN REGISTER places all FlashFile
Memory devices into a Deep-Sleep mode. This disables most of the 28F008SA’s circuitry and reduces
current consumption to 0.2 mA per device. Additionally, when the host system pulls ASIC control logic
high and latches all address and data lines (i.e., not
toggling), the card’s total current draw is reduced to
approximately 5 mA (CMOS input levels) for a 20
Megabyte card. On writing a ‘‘0’’ to the PWRDWN bit
(Global PowerDown Register) or any individual device pair (Sleep Control Register), a Deep-Sleep
mode recovery period must be allowed for
28F008SA device circuitry to power back on.
SERIES 2 FLASH MEMORY CARDS
SYSTEM DESIGN CONSIDERATIONS
POWER SUPPLY DECOUPLING
Flash memory power-switching characteristics require careful device decoupling. System designers
are interested in three supply current issuesÐstandby, active and transient current peaks, produced by
rising and falling edges of CE1Ý and CE2Ý. The
capacitive and inductive loads on the card and internal flash memory device pairs determine the magnitudes of these peaks.
The Flash Memory Card features on-card ceramic
decoupling capacitors connected between VCC and
GND, and between VPP1/VPP2 and GND to help
transient voltage peaks.
On the host side, the card connector should also
have a 4.7 mF electrolytic capacitor between VCC
and GND, as well as between VPP1/VPP2 and GND.
The bulk capacitors will overcome voltage slumps
caused by printed-circuit-board trace inductance,
and will supply charge to the smaller capacitors as
needed.
POWER UP/DOWN PROTECTION
Each device in the Flash Memory Card is designed
to offer protection against accidental erasure or writing, caused by spurious system-level signals that
may exist during power transitions. The card will
power-up into the Read Array Mode.
A system designer must guard against active writes
for VCC voltages above VLKO when VPP is active.
Since both WEÝ and CE1Ý (and/or CE2Ý) must be
low for a command write, driving either to VIH will
inhibit writes. With its Command User Interface, alteration of device contents only occurs after successful completion of the two-step command sequences.
While these precautions are sufficient for most applications, an alternative approach would allow VCC to
reach its steady state value before raising VPP1/
VPP2 above VCC a 2.0V. In addition, upon powering-down, VPP1/VPP2 should be below VCC a 2.0V,
before lowering VCC.
HOT INSERTION/REMOVAL
The capability to remove or insert PC cards while the
system is powered on (i.e., hot insertion/removal)
requires careful design approaches on the system
and card levels. To design for this capability consider card overvoltage stress, system power droop and
control line stability.
A PCMCIA/JEIDA specified socket properly sequences the power supplies to the flash memory
card via shorter and longer pins. This assures that
hot insertion and removal will not result in card damage or data loss.
PCMCIA CARD INFORMATION
STRUCTURE
The Card Information Structure (CIS) starts at address zero of the card’s Attribute Memory Plane. It
contains a variable-length chain of data blocks (tuples) that conform to a basic format as shown in
Table 5. This section describes each tuple contained
within the Series 2 Flash Memory Card.
The Device Information Tuple
This tuple (CISTPLÐDEV e 01H) contains information pertaining to the card’s speed and size. The Series 2 Card is offered with a 150 nanosecond access
time. Card sizes range between 2 and 20 Megabytes.
Table 5. Tuple Format
Bytes
Data
0
Tuple Code: CISTPLÐxxx. The tuple code 0FFH indicates no more tuples in the list.
1
Tuple Link: TPLÐLlNK. Link to the next tuple in the list. This can be viewed as the number of
additional bytes in tuple, excluding this byte. If the link field is zero, the tuple body is empty. If the
link field contains 0FFH, this tuple is the last tuple in the list.
2bn
Bytes specific to this tuple.
23
SERIES 2 FLASH MEMORY CARDS
The Device Geometry Tuple
This tuple (CISTPLÐDEVlCEGEO e 1EH) is conceptually similar to a DOS disk geometry tuple
(CISTPLÐGEOMETRY), except it is not a formatdependent property; this deals with the fixed architecture of the memory device(s).
Level 1 Version/Product
Information Tuple
This tuple (CISTPLÐVERI e 15H) contains Level-1version compliance and card-manufacturer information. Fields are described as follows:
TPLLV1 MAJORÐMajor version number e 04H.
Fields are defined as follows:
DGTPL BUSÐValue e n, where system bus width
e 2(nb1) bytes. N e 2 for standard PCMClA Release 1.0/2.0 cards.
DGTPL EBSÐValue e n, where the memory array’s
physical memory segments have a minimum erase
block size of 2(nb1) address increments of
DGTPLÐBUS-wide accesses.
DGTPL RBSÐValue e n, where the memory array’s physical memory segments have a minimum
read block size of 2(nb1) address increments of
DGTPLÐBUS-wide accesses.
DGTPL WBSÐValue e n, where the memory array’s physical memory segments have a minimum
write block size of 2(nb1) address increments of
DGTPLÐBUS-wide accesses.
DGTPL PARTÐValue e n, where the memory array’s physical memory segments can have partitions
subdividing the arrays in minimum granularity of
2(nb1) number of erase blocks.
FL DEVICE INTERLEAVEÐValue e n, where card
architectures employ a multiple of 2(nb1) times interleaving of the entire memory arrays with the above
characteristics. Non-interleaved cards have values
n e 1.
Jedec Programming
Information Tuple
This tuple (CISTPLÐJEDEC e 18H) contains the
Intel manufacturing identifier (89H) and the
28F008SA device ID (A2H).
24
TPLLV1 MINORÐMinor version number e 01H for
release 2.0.
TPLLV1 INFOÐ
Name of manufacturer
Name of product
Card type
Speed
Register Base
Test Codes
Legalities
e
e
e
e
e
e
e
intel;
SERIES2-‘‘Card size’’;
2;
150 ns or 200 ns
REGBASE 4000H
DBBDRELP
COPYRIGHT intel
Corporation 1991
The Configurable Card Tuple
This tuple (ClSTPLÐCONF e 1AH) describes the
interface supported by the card and the locations of
the Card Configuration Registers and the Card Configuration Table.
Fields are described as follows:
TPCC SZÐSize of fields byte e 01H.
TPCC LASTÐIndex number of the last entry in the
Card Configuration Table e 00H.
TPCC RADRÐConfiguration Registers Base Address in Reg Space e 4000H.
TPCC RMSKÐConfiguration
Mask e 03H.
Registers
Present
The End-Of-List Tuple
The end-of-list tuple (CISTPLÐEND e FFH) marks
the end of a tuple chain. Upon encountering this tuple, continue tuple processing as if a long-link to address 0 of common memory space were encountered.
SERIES 2 FLASH MEMORY CARDS
Tuple
Address
Value
Description
00H
01H
02H
03H
04H
53H
52H
06H
08H
0AH
06H
0EH
26H
4EH
FFH
Tuple
Address
Value
Description
CISTPLÐDEV
TPLÐLINK
32H
6CH
l
34H
00H
END TEXT
DEVICEÐINFO e
FLASH 150 ns
DEVICEÐINFO e
FLASH 200 ns
36H
53H
S
38H
45H
E
3AH
52H
R
CARD SIZE
2M
4M
10M
20M
3CH
49H
I
3EH
45H
E
40H
53H
S
42H
32H
2
END OF
DEVICE
44H
2DH
Ð
46H
30H
30H
31H
32H
2M e 0
4M e 0
10M e 1
20M e 2
48H
32H
34H
30H
30H
2M e 2
4M e 4
10M e 0
20M e 0
4AH
20H
SPACE
1EH
CISTPLÐ
DEVICEGEO
0CH
06H
0EH
02H
10H
11H
TPLÐLINK
DGTPLÐBUS
DGTPLÐEBS
12H
01H
DGTPLÐRBS
14H
01H
16H
03H
DGPLÐWBS
DGTPLÐPART
18H
01H
1AH
18H
1CH
02H
FLÐDEVICE
INTERLEAVE
CISTPLÐJEDEC
TPLÐLINK
1EH
89H
INTEL J-ID
20H
A2H
28F008 J-ID
22H
15H
24H
50H
CISTPLÐVER1
TPLÐLINK
26H
04H
TPLLV1
MAJOR
28H
01H
TPLLV1
MINOR
2AH
69H
TPLLV1 INFO
i
2CH
6EH
n
2EH
74H
t
30H
65H
e
4CH
00H
END TEXT
4EH
32H
CARD TYPE 2
50H
41H
42H
45H
5AH
48H
49H
4CH
4FH
A e 2M, 150 ns
B e 4M, 150 ns
E e 10M, 150 ns
Z e 20M, 150 ns
H e 2M, 200 ns
I e 4M, 200 ns
L e 10M, 200 ns
O e 20M, 200 ns
25
SERIES 2 FLASH MEMORY CARDS
26
Tuple
Address
Value
Description
Tuple
Address
Value
Description
52H
20H
SPACE
96H
69H
i
54H
52H
REGBASE-R
98H
6EH
n
56H
45H
E
9AH
74H
t
58H
47H
G
9CH
65H
e
5AH
42H
B
9EH
6CH
l
5CH
41H
A
A 0H
20H
SPACE
5EH
53H
S
60H
45H
E
A2H
43H
CORPORATION
C
A4H
4FH
O
A6H
52H
R
A8H
50H
P
62H
20H
SPACE
64H
34H
4000h
4
66H
30H
0
AAH
4FH
O
68H
30H
0
ACH
52H
R
6AH
30H
0
AEH
41H
A
6CH
68H
h
B0H
54H
T
6EH
20H
SPACE
B2H
49H
I
70H
44H
D
B4H
4FH
O
72H
42H
B
B6H
4EH
N
74H
42H
B
B8H
20H
SPACE
76H
44H
D
BAH
31H
1
78H
52H
R
BCH
39H
9
7AH
45H
E
BEH
39H
9
7CH
4CH
L
C0H
31H
1
7EH
50H
P
C2H
00H
END TEXT
80H
00H
END TEXT
C4H
FFH
END OF LIST
1AH
CISTPLÐCONF
43H
COPYRIGHT
C
C6H
82H
C8H
06H
TPLÐLINK
84H
4FH
O
86H
50H
P
88H
59H
Y
TPCCÐSZ
TPCCÐLAST
TPCCÐRADR
8AH
52H
R
8CH
49H
I
8EH
47H
G
90H
48H
H
92H
54H
T
94H
20H
SPACE
CAH
01H
CCH
00H
CEH
00H
D0H
40H
D2H
03H
D4H
FFH
D6H
FFH
D8H
00H
TPCCÐRADR
TPCCÐRMSK
END OF LIST
CISTPLÐEND
INVALID ECIS
ADDRESS
SERIES 2 FLASH MEMORY CARDS
OPERATING SPECIFICATlONS
NOTICE: This data sheet contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with
your local Intel Sales office that you have the latest
data sheet before finalizing a design.
ABSOLUTE MAXIMUM RATINGS*
Storage TemperatureÀÀÀÀÀÀÀÀÀÀÀÀ b 40§ C to a 85§ C
Voltage on Any Pin with
Respect to Ground ÀÀÀÀÀ b 2.0V to VCC a 2.0V(1)
*WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
VPP1/VPP2 Supply Voltage with
Respect to Ground ÀÀÀÀÀÀÀ b 2.0V to a 14.0V(1, 2)
VCC Supply Voltage with
Respect to Ground ÀÀÀÀÀÀÀÀÀÀÀÀ b 0.5V to a 7.0V
NOTES:
1. Minimum DC input voltage is b0.5V. During transitions, inputs may undershoot to b2.0V tor periods of less than 20 ns.
Maximum DC voltage on output pins is VCC a 0.5V. The voltage may overshoot to VCC a 2.0V for periods of less than 20
ns.
2. Maximum DC input voltage on VPP1/VPP2 may overshoot to a 14.0V for periods of less than 20 ns.
COMMERCIAL TEMPERATURE OPERATING CONDITIONS
These operating conditions apply to commercial temperature devices.
Symbol
Parameter
TA
Operating Temperature
VCC
VCC Supply Voltage (5%)
Min
Max
Unit
0
70
§C
4.75
5.25
V
EXTENDED TEMPERATURE OPERATING CONDITIONS
These operating conditions apply to extended temperature devices.
Min
Max
Unit
TA
Symbol
Operating Temperature
Parameter
b 40
85
§C
VCC
VCC Supply Voltage (5%)
4.75
5.25
V
CHARACTERISTICS
All AC and DC characteristics apply to both commercial and extended temperature devices.
COMMON DC CHARACTERISTICS, CMOS and TTL
Symbol
Parameter
Typ
Max
Unit
Test Condition
1, 3
g1
g 20
mA
VCC e VCC Max
VIN e VCC or GND
Output Leakage Current
1
g1
g 20
mA
VCC e VCC Max
VOUT e VCC or GND
VIL
Input Low Voltage
1
Input High Voltage (TTL)
2.4
0.8
VCC a 0.3
V
VIH
0.7 VCC
VCC a 0.3
ILI
Input Leakage Current
ILO
Notes
1
Input High Voltage (CMOS)
Min
b 0.5
V
VOL
Output Low Voltage
1
VSS
0.4
V
VCC e VCC Min
IOL e 3.2 mA
VOH
Output High Voltage
1
4.0
VCC
V
VCC e VCC Min
IOH e b 2.0 mA
VPPL
VPP during Read Only Operations
1, 2
0.0
6.5
V
VPPH
VPP during Read/Write Operations
1
11.4
12.6
V
VLKO
VCC Erase/Write Lock Voltage
1
2.0
V
NOTES:
1. Values are the same for byte and word wide modes and for all card densities.
2. Block Erases/Data Writes are inhibited when VPP e VPPL and not guaranteed in the range between VPPH and VPPL.
3. Exceptions: With VIN e GND, the leakage on CE1Ý, CE2Ý, REGÝ, OEÝ, WEÝ, will be s 500 mA due to internal pullup
resistors and, with VIN e VCC, RST leakage will be s 500 mA due to internal pulldown resistor.
27
SERIES 2 FLASH MEMORY CARDS
DC CHARACTERISTICS, CMOS
Symbol
Parameter
Notes
Byte Wide Mode
Min
Typ
Max
Word Wide Mode
Min
Typ
Max
Unit
Test Condition
ICCR
VCC Read Current
1, 3
45
85
65
120
mA
VCC e VCC Max,
Control Signals
e GND
tCYCLE e 200 ns,
IOUT e 0 mA
ICCW
VCC Write Current
1, 3
35
80
45
110
mA
Data Write
in Progress
ICCE
VCC Erase Current
1, 2, 3
35
80
45
110
mA
Block (Pair) Erase
in Progress
ICCS
VCC Standby Current
110
420
110
420
2 Meg
4 Meg
ICCSL
VCC Sleep Current
160
620
160
620
10 Meg
310
1220
310
1220
20 Meg
560
2200
560
2200
1, 4, 6
2 Meg
4 Meg
1, 4, 5
10 Meg
20 Meg
60
60
100
100
260
260
mA
VCC e VCC Max,
Control Signals
e VIH
mA
460
460
IPPW
VPP Write
Current (VPP e VPPH)
1, 3
15
30
mA
Data Write
in Progress
IPPE
VPP Erase
Current (VPP e VPPH)
1, 3
15
30
mA
Block (Pair) Erase
in Progress
IPPSL
VPP Sleep Current
2 Meg
0.2
10
0.2
10
0.4
20
0.4
20
1
50
1
50
20 Meg
2
100
2
100
2 Meg
2.0
20
2.0
20
4 Meg
1, 5
10 Meg
IPPS1
IPPS2
VPP Standby or
Read Current
(VPP s VCC)
VPP Standby or
Read Current
(VPP l VCC)
2.2
30
2.2
30
10 Meg
4 Meg
2.8
60
2.8
60
20 Meg
3.8
110
3.8
110
2 Meg
20
400
20
400
4 Meg
1, 6
40
800
40
800
10 Meg
100
2000
100
2000
20 Meg
200
4000
200
4000
1, 6
mA
mA
mA
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC e 5.0V, VPP e 12.0V, T e 25§ C.
2. The Data Sheet specification for the 28F008SA in Erase Suspend (ICCES) is 5 mA typical and 10 mA max with the device
deselected. If the device(s) are read while in Erase Suspend Mode, current draw is the sum of ICCES and ICCR.
3. Standby or Sleep currents are not included for non-accessed devices.
4. Address and data inputs to card static. Control line voltages equal to VIH or VIL.
5. All 28F008SA devices in Deep-Sleep (Reset-PowerDown) mode.
6. In Byte and Word Mode, all but two devices in Deep-Sleep.
28
SERIES 2 FLASH MEMORY CARDS
DC CHARACTERISTICS, TTL
Symbol
Parameter
Notes
Byte Wide Mode
Min
Typ
Max
Word Wide Mode
Min
Typ
Max
Unit
Test Condition
ICCR
VCC Read Current
1, 3
70
135
90
170
mA VCC e VCC Max,
Control Signals e GND
tCYCLE e 200 ns,
IOUT e 0 mA
ICCW
VCC Write Current
1, 3
60
130
70
160
mA Data Write
in Progress
ICCE
VCC Erase Current
1, 2, 3
60
130
70
160
mA Block (Pair) Erase
in Progress
ICCS
VCC Standby Current
2 Meg
4 Meg
1, 4, 6
20
100
20
100
VCC e VCC Max,
Control Signals
mA e VIH
1, 4, 5
20
100
20
100
mA
10 Meg
20 Meg
ICCSL
VCC Sleep Current
2 Meg
4 Meg
10 Meg
20 Meg
IPPW
VPP Write
Current (VPP e VPPH)
1, 3
10
30
20
60
mA Data Write
in Progress
IPPE
VPP Erase
Current (VPP e VPPH)
1, 3
10
30
20
60
mA Block (Pair) Erase
in Progress
IPPSL
VPP Sleep Current
IPPS1
IPPS2
VPP Standby or
Read Current
(VPP s VCC)
VPP Standby or
Read Current
(VPP l VCC)
2 Meg
0.2
10
0.2
10
4 Meg
0.4
20
0.4
20
10 Meg
1.0
50
1.0
50
20 Meg
2.0
100
2.0
100
2 Meg
2.0
20
2.0
20
4 Meg
2.2
30
2.2
30
10 Meg
2.8
60
2.8
60
20 Meg
3.8
110
3.8
110
2 Meg
20
400
20
400
4 Meg
40
800
40
800
10 Meg
100
2000
100
2000
20 Meg
200
4000
200
4000
1, 5
1, 6
1, 6
mA
mA
mA
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC e 5.0V, VPP e 12.0V, T e 25§ C.
2. The Data Sheet specification for the 28F008SA in Erase Suspend (ICCES) is 5 mA typical and 10 mA max with the device
deselected. If the device(s) are read while in Erase Suspend Mode, current draw is the sum of ICCES and ICCR.
3. Standby or Sleep currents are not included for non-accessed devices.
4. Address and data inputs to card static. Control line voltages equal to VIH or VIL.
5. All 28F008SA devices in Deep-Sleep (Reset-PowerDown) mode.
6. In Byte and Word Mode, all but two devices in Deep-Sleep.
7. The current consumption from the 28F008SA is insignificant in relation to the ASIC’s.
29
SERIES 2 FLASH MEMORY CARDS
AC CHARACTERISTICS
AC Timing Diagrams and characteristics are guaranteed to meet or exceed PCMCIA Release 2.0 specifications. PCMCIA allows a 300 ns access time for
Attribute Memory. Note that read and write access
timings to the Series 2 Flash Memory Card’s Common and Attribute Memory Planes are identical at
150 ns. Furthermore, there is no delay in switching
between the Common and Attribute Memory Planes.
COMMON AND ATTRIBUTE MEMORY, AC CHARACTERISTICS: Read-Only Operations
Symbol
Parameter
Max
Unit
Address Access Time
150
ns
ta (CE)
Card Enable Access Time
150
ns
ta (OE)
Output Enable Access Time
75
ns
tEHQX
tdis (CE)
Output Disable Time from CEÝ
75
ns
tGHQZ
tdis (CE)
Output Disable Time from OEÝ
75
ns
tGLQX
ten (CE)
Output Enable Time from CEÝ
5
ns
tELQX
ten (OE)
Output Enable Time from OEÝ
5
ns
tAXQX
tv (A)
Data Valid from Add Change
JEDEC
PCMCIA
tAVAV
tRC
Read Cycle Time
tAVQV
ta (A)
tELQV
tGLQV
tRHQV
Reset-PwrDwn Recovery to Output Delay
tsu (VCC)
CE Setup Time on Power-Up
First Access after Reset
Notes
Min
150
ns
0
ns
500
ns
1
ms
500
ns
290434 – 28
Transient Input/Output Reference Waveform (VCC e 5.0V) for Standard Test Configuration
290434 – 29
Transient Input/Output Reference Waveform (VCC e 3.3V) for Standard Test Configuration
30
NOTE:
1. The hatched area may be either high or low.
290434– 21
SERIES 2 FLASH MEMORY CARDS
Figure 16. AC Waveform for Read Operations
31
SERIES 2 FLASH MEMORY CARDS
COMMON AND ATTRIBUTE MEMORY, AC CHARACTERISTICS: Write Operations(1)
Symbol
JEDEC
Parameter
PCMCIA
Notes
Min
Max
Unit
tAVAV
tWC
Write Cycle Time
150
ns
tWLWH
tw (WE)
Write Pulse Width
80
ns
tAVWL
tsu (A)
Address Setup Time
20
ns
tAVWH
tsu (A-WEH)
Address Setup Time for WEÝ
100
ns
tVPWH
tvps
VPP Setup to WEÝ Going High
100
ns
tELWH
tsu (CE-WEH)
Card Enable Setup Time for WEÝ
100
ns
tDVWH
tsu (D-WEH)
Data Setup Time for WEÝ
50
ns
tWHDX
th (D)
Data Hold Time
20
ns
tWHAX
trec (WE)
Write Recover Time
20
ns
tWHRL
WEÝ High to RDY/BSYÝ
tWHQV1
Duration of Data Write Operation
tWHQV2
Duration of Block Erase Operation
tQVVL
tWHGL
120
VPP Hold from Operation Complete
th (OE-WE)
tRHWL
2
ns
6
ms
0.3
sec
0
ns
Write Recovery before Read
10
ns
Reset-PwrDwn Recovery to WEÝ Going Low
1
ms
NOTES:
1. Read timing characteristics during erase and data write operations are the same as during read-only operations. Refer to
AC Characteristics for Read-Only operations.
2. Refer to text on Data-Write and Block-Erase Operations.
BLOCK ERASE AND DATA WRITE PERFORMANCE
Parameter
Notes
Block Pair Erase Time(1)
2, 4
Block Pair Write Time
2, 4
Byte/Word Write Time
4
Min
Typ(3) Max Unit
1.1
4.8 ms
10
sec
0.5
2.1
sec
6 ms
3 ms
NOTES:
1. Individual blocks can be erased 100,000 times.
2. Excludes System-Level Overhead.
3. 25§ C, 12.0 VPP.
4. Monitor Ready/Busy Registers for the completion of a write/erase command.
32
NOTE:
By writing the appropriate register, or on power-up, the card control ASIC generates the RPÝ signal to the card’s devices.
290434– 22
SERIES 2 FLASH MEMORY CARDS
Figure 17. AC Waveform for Write Operations
33
SERIES 2 FLASH MEMORY CARDS
COMMON AND ATTRIBUTE MEMORY, AC CHARACTERISTICS: CEÝ-Controlled Write Operations(1)
Symbol
JEDEC
Parameter
PCMCIA
Min
1
150
Max
Unit
tAVAV
tWC
tELEH
tw (WE)
Chip Enable Pulse Width
1
80
ns
tAVEL
tsu (A)
Address Setup Time
1
20
ns
tAVEH
tsu (A-WEH)
Address Setup Time for CEÝ
1
100
ns
tVPEH
tvps
VPP Setup to CEÝ Going High
1
100
ns
tWLEH
tsu (CE-WEH)
Write Enable Setup Time for CEÝ
1
100
ns
tDVEH
tsu (D-WEH)
Data Setup Time for CEÝ
1
50
ns
tEHDX
th (D)
Data Hold Time
1
20
ns
tEHAX
trec (WE)
Write Recover Time
1
20
CEÝ High to RDY/BSYÝ
1
tEHRL
Write Cycle Time
Notes
ns
ns
120
ns
tEHQV1
Duration of
Data Write
Duration of Data Write Operation
1
6
ms
tEHQV2
Duration of
Erase
Duration of Block Erase Operation
1
0.3
sec
VPP Hold from Operation Complete
1, 2
0
ns
th (OE-WE)
Write Recovery before Read
1
10
ns
1
ms
tQVVL
tEHGL
tRHEL
Reset-PwrDwn Recovery to CEÝ Going Low
NOTES:
1. Read timing characteristics during erase and data write operations are the same as during read-only operations. Refer to
AC Characteristics for Read-Only operations.
2. Refer to text on Data-Write and Block-Erase Operations.
34
NOTE:
By writing the appropriate register, or on power-up, the card control ASIC generates the RPÝ signal to the card’s devices.
290434– 23
SERIES 2 FLASH MEMORY CARDS
Figure 18. Alternate AC Waveform for Write Operations
35
SERIES 2 FLASH MEMORY CARDS
290434 – 24
Figure 19. Series 2 Flash Memory Card Package Dimensions
36
SERIES 2 FLASH MEMORY CARDS
290434 – 25
Figure 20. Card Connector Socket
290434 – 26
L1 MAX
0.020
(0.5)
L2
L3 REF
Pin TypeÐSee Table 1
Detect
0.059 (1.5) g 0.039
General 0.084 (2.1) g 0.064
Power
0.098 (2.5) g 0.078
0.024
(0.6)
Figure 21. Pin/Socket Contact Length with Wipe
37
SERIES 2 FLASH MEMORY CARDS
Label Dimensions
290434 – 30
NOTES:
Total label dimensions are g 0.003×
Total label thickness with adhesive is 0.002×
Card Dimensions with Label
290434 – 31
Figure 22. Label Information
38
SERIES 2 FLASH MEMORY CARDS
Table 5. Capacitance TA e 25§ C, f e 1.0 MHz
Symbol
Commercial
Characteristics
Min
CIN
COUT
Unit
Max
Address/Control Capacitance (A0 –A8, CE1Ý, CE2Ý)
30
pF
Address/Control Capacitance (A9 –A24, all others)
20
pF
VCC, VPP
2
mF
Output Capacitance
20
pF
NOTE:
Sampled, not 100% tested.
ORDERING INFORMATION
iMC020FLSA-15
M9508014,SBXXXX
WHERE:
i
MC
020
e INTEL
e MEMORY CARD
e DENSITY IN MEGABYTES
FL
S
A
-ET
15
e
e
e
e
e
(002,004,010,020 AVAILABLE)
FLASH TECHNOLOGY
BLOCKED ARCHITECTURE
SERIES 2
EXTENDED TEMPERATURE
150 ns
M
95
08
014
SBXXXX
e
e
e
e
e
MANILA
1995
WEEK 08
LOT Ý
CUSTOMER IDENTIFIER
ADDITIONAL INFORMATION
28F008SA FlashFile TM Memory Data Sheet
AP-361 ‘‘Implementing the Integrated Registers of the Series 2 Flash Memory Card’’
AP-364 ‘‘28F008SA Automation and Algorithms’’
AP-359 ‘‘28F008SA Hardware Interfacing’’
AP-360 ‘‘28F008SA Software Drivers’’
AP-606 ‘‘Interchangeability of Series 1/2/2 a Flash Memory Cards’’
ORDER NUMBER
290429
292096
292099
292094
292095
REVISION HISTORY
Number
Description
02
Added 150 ns TUPLE, Deleted 250 ns TUPLE
Corrected Global Power Register Address to 4002H
Corrected Write Protection Register Address to 4104H
Corrected Ready-Busy Mode Register Address to 4140H
ICC Standby Byte Wide Mode MAX/TYP Increased
Added Power-On Timing Spec
Added First Access after Reset Spec
Changed Advanced Information to Preliminary
03
Added 2 MByte card support
Changed write timing waveforms to match PCMCIA
Changed PowerDown (PWD) to Reset-PowerDown (RP)
04
Extended Operating Temperature Range
Added Maximum Byte Write Time
05
Added 150 ns Timings
Change Cover Drawing to Accommodate Label
06
Modified DC characteristics to reflect a conversion to new memory componentsÐthe 0.4m
version of the 28F008SA. The new devices also have improved program and erase
performance.
39