LINER LTC1605-2C

LTC1605-1/LTC1605-2
Single Supply 16-Bit, 100ksps,
Sampling ADCs
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FEATURES
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DESCRIPTIO
The LTC ®1605-1/LTC1605-2 are 100ksps, sampling
16-bit A/D converters that draw only 55mW (typical) from
a single 5V supply. These easy-to-use devices include a
sample-and-hold, precision reference, switched capacitor
successive approximation A/D and trimmed internal clock.
Sample Rate: 100ksps
Complete 16-Bit Solution on a Single 5V Supply
Unipolar Input Range: 0V to 4V (LTC1605-1)
Bipolar Input Range: ±4V (LTC1605-2)
Power Dissipation: 55mW Typ
Signal-to-Noise Ratio: 86dB Typ
Operates with Internal or External Reference
Internal Synchronized Clock
28-Pin 0.3" PDIP and SSOP Packages
The LTC1605-1’s input range is 0V to 4V while the
LTC1605-2’s input range is ±4V. An external reference
can be used if greater accuracy over temperature is
needed.
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APPLICATIO S
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The ADC has a microprocessor compatible, 16-bit or two
byte parallel output port. A convert start input and a data
ready signal (BUSY) ease connections to FIFOs, DSPs and
microprocessors.
Industrial Process Control
Multiplexed Data Acquisition Systems
High Speed Data Acquisition for PCs
Digital Signal Processing
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATIO
LTC1605-1 Low Power, 100kHz, 16-Bit Sampling ADC on 5V Supply
5V
10µF
28
0.1µF
Typical INL Curve
27
2.0
VDIG VANA
1 VIN
6 TO 13
15 TO 22
4k
16-BIT
SAMPLING ADC
33.2k
2.5V
20k
D15 TO D0
16-BIT
OR 2 BYTE
PARALLEL
BUS
10k
4 CAP
BUSY 26
2.2µF
BUFFER
2.5V
3 REF
CONTROL
LOGIC AND
TIMING
2.5V
REFERENCE
4k
CS 25
R/C 24
BYTE 23
2.2µF
DIGITAL
CONTROL
SIGNALS
1.5
1.0
INL (LSBs)
0V TO 4V 200Ω
INPUT
0.5
0
–0.5
–1.0
–1.5
–2.0
0
AGND1
2
AGND2
5
DGND
14
16384
32768
49152
65535
CODE
1605-1/2 TA01
1605-1/2 TA02/G04
1
LTC1605-1/LTC1605-2
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ABSOLUTE
AXI U RATI GS
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PACKAGE/ORDER I FOR ATIO
(Notes 1, 2)
VANA .......................................................................... 7V
VDIG to VANA ........................................................... 0.3V
VDIG ........................................................................... 7V
Ground Voltage Difference
DGND, AGND1 and AGND2 .............................. ±0.3V
Analog Inputs (Note 3)
VIN ..................................................................... ±25V
CAP ............................ VANA + 0.3V to AGND2 – 0.3V
REF .................................... Indefinite Short to AGND2
Momentary Short to VANA
Digital Input Voltage (Note 4) ........ VDGND – 0.3V to 10V
Digital Output Voltage ........ VDGND – 0.3V to VDIG + 0.3V
Power Dissipation .............................................. 500mW
Operating Ambient Temperature Range
LTC1605-1C/LTC1605-2C ....................... 0°C to 70°C
LTC1605-1I/LTC1605-2I .................... – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
TOP VIEW
ORDER PART
NUMBER
VIN 1
28 VDIG
AGND1 2
27 VANA
REF 3
26 BUSY
CAP 4
25 CS
AGND2 5
LTC1605-1CG
LTC1605-1IG
LTC1605-2CG
LTC1605-2IG
LTC1605-1CN
LTC1605-1IN
LTC1605-2CN
LTC1605-2IN
24 R/C
D15 (MSB) 6
23 BYTE
D14 7
22 D0
D13 8
21 D1
D12 9
20 D2
D11 10
19 D3
D10 11
18 D4
D9 12
17 D5
D8 13
16 D6
DGND 14
15 D7
G PACKAGE
28-LEAD PLASTIC SSOP
N PACKAGE
28-LEAD PDIP
TJMAX = 125°C, θJA = 95°C/W (G)
TJMAX = 125°C, θJA = 130°C/W (N)
Consult factory for Military grade parts.
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CO VERTER CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. With external reference (Notes 5, 6).
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
●
16
Bits
No Missing Codes
●
15
Bits
Transition Noise
1
LSBRMS
Integral Linearity Error
(Note 7)
●
±3
LSB
Zero Error
Ext. Reference = 2.5V (Note 8)
●
±10
mV
±2
Zero Error Drift
±7
Full-Scale Error Drift
Full-Scale Error
Ext. Reference = 2.5V (Notes 12, 13)
Full-Scale Error Drift
Ext. Reference = 2.5V
Power Supply Sensitivity
VANA = VDIG = VDD
VDD = 5V ±5% (Note 9)
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ppm/°C
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ppm/°C
±0.50
●
±2
%
ppm/°C
±8
LSB
A ALOG I PUT
The ● denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
VIN
Analog Input Range (Note 9)
4.75V ≤ VANA ≤ 5.25V, 4.75V ≤ VDIG ≤ 5.25V
LTC1605-1
LTC1605-2
MIN
●
●
TYP
0 to 4
±4
MAX
UNITS
V
V
CIN
Analog Input Capacitance
10
pF
RIN
Analog Input Impedance
10
kΩ
2
LTC1605-1/LTC1605-2
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DY A IC ACCURACY
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Notes 5, 14)
SYMBOL
PARAMETER
CONDITIONS
MIN
S/(N + D)
Signal-to-(Noise + Distortion) Ratio
1kHz Input Signal (Note 14)
10kHz Input Signal
20kHz, – 60dB Input Signal
THD
Total Harmonic Distortion
TYP
MAX
UNITS
87
85
30
dB
dB
dB
1kHz Input Signal, First 5 Harmonics
10kHz Input Signal, First 5 Harmonics
– 101
– 92
dB
dB
Peak Harmonic or Spurious Noise
1kHz Input Signal
10kHz Input Signal
– 101
– 92
dB
dB
Full-Power Bandwidth
(Note 15)
275
kHz
40
ns
Aperture Delay
Aperture Jitter
Sufficient to Meet AC Specs
Transient Response
Full-Scale Step (Note 9)
Overvoltage Recovery
(Note 16)
µs
2
150
ns
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I TER AL REFERE CE CHARACTERISTICS
The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
VREF Output Voltage
IOUT = 0
VREF Output Tempco
IOUT = 0
●
MIN
TYP
MAX
UNITS
2.470
2.500
2.520
V
±5
Internal Reference Source Current
ppm/°C
µA
1
External Reference Voltage for Specified Linearity
(Notes 9, 10)
External Reference Current Drain
Ext. Reference = 2.5V (Note 9)
CAP Output Voltage
IOUT = 0
2.30
2.50
●
2.70
V
100
µA
2.50
V
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DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
VIH
High Level Input Voltage
VDD = 5.25V
●
VIL
Low Level Input Voltage
VDD = 4.75V
●
IIN
Digital Input Current
VIN = 0V to VDD
●
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
VDD = 4.75V
IO = –10µA
VOL
Low Level Output Voltage
VDD = 4.75V
IO = 160µA
IO = – 200µA
IO = 1.6mA
●
TYP
MAX
UNITS
0.8
V
±10
µA
2.4
V
5
pF
4.5
V
4.0
V
0.05
●
0.10
V
0.4
V
IOZ
Hi-Z Output Leakage D15 to D0
VOUT = 0V to VDD, CS High
●
±10
µA
COZ
Hi-Z Output Capacitance D15 to D0
CS High (Note 9)
●
15
pF
ISOURCE
Output Source Current
VOUT = 0V
–10
mA
ISINK
Output Sink Current
VOUT = VDD
10
mA
3
LTC1605-1/LTC1605-2
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TI I G CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fSAMPLE(MAX)
Maximum Sampling Frequency
●
tCONV
Conversion Time
●
8
µs
tACQ
Acquisition Time
●
2
µs
t1
Convert Pulse Width
(Note 11)
●
t2
Data Valid Delay After R/C↓
(Note 9)
●
8
µs
t3
BUSY Delay from R/C↓
CL = 50pF
●
65
ns
t4
BUSY Low
t5
BUSY Delay After End of Conversion
220
ns
t6
Aperture Delay
40
ns
t7
Bus Relinquish Time
●
10
35
t8
BUSY Delay After Data Valid
●
50
200
ns
t9
Previous Data Valid After R/C↓
7.4
µs
t10
R/C to CS Setup Time
t11
Time Between Conversions
t12
Bus Access and Byte Delay
100
kHz
40
ns
µs
8
(Notes 9, 10)
(Notes 9, 10)
83
ns
10
ns
10
µs
10
83
ns
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POWER REQUIRE E TS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
VDD
Positive Supply Voltage
(Notes 9, 10)
4.75
IDD
Positive Supply Current
PDIS
Power Dissipation
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND, AGND1
and AGND2 wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below ground or above VANA =
VDIG = VDD, they will be clamped by internal diodes. This product can
handle input currents of greater than 100mA below ground or above VDD
without latch-up.
Note 4: When these pin voltages are taken below ground, they will be
clamped by internal diodes. This product can handle input currents of
90mA below ground without latchup. These pins are not clamped to VDD.
Note 5: VDD = 5V, fSAMPLE = 100kHz, tr = tf = 5ns unless otherwise
specified.
Note 6: Linearity, offset and full-scale specifications apply for a VIN input
with respect to ground.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual end points of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Zero error for the LTC1605-1 is the voltage measured from
0.5LSB when the output code flickers between 0000 0000 0000 0000
and 0000 0000 0000 0001. Zero error for the LTC1605-2 is the voltage
measured from – 0.5LSB when the output code flickers between 0000
0000 0000 0000 and 1111 1111 1111 1111.
4
●
TYP
MAX
UNITS
5.25
V
11
16
mA
55
80
mW
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: With CS low the falling R/C edge starts a conversion. If R/C
returns high at a critical point during the conversion it can create small
errors. For best results ensure that R/C returns high within 3µs after the
start of the conversion.
Note 12: As measured with fixed resistors shown in Figure 4. Adjustable to
zero with external potentiometer.
Note 13: Full-scale error is the untrimmed deviation from ideal last code
transition, divided by the full-scale range and includes the effect of offset
error.
Note 14: All specifications in dB are referred to a full-scale 4V input for the
LTC1605-1 and to ±4V input for the LTC1605-2.
Note 15: Full-power bandwidth is defined as full-scale input frequency at
which a signal-to-(noise + distortion) degrades to 60dB or 10 bits of
accuracy.
Note 16: Recovers to specified performance after (±20V) input
overvoltage for the LTC1605-1 and ±15V for the LTC1605-2.
LTC1605-1/LTC1605-2
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TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Supply Voltage
12.5
12.0
fSAMPLE = 100kHz
11.0
10.5
10.0
4.75
5.00
5.25
CHANGE IN CAP VOLTAGE (V)
POWER SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
11.5
9.5
4.50
0.04
fSAMPLE = 100kHz
12.0
11.5
11.0
10.5
10.0
–50
5.50
–25
0
25
50
TEMPERATURE (°C)
75
1605-1/2 G01
–0.02
–0.04
LTC1605-2
–0.06
100
2.0
1.5
1.5
1.0
1.0
0.5
0.5
–0.5
–1.0
–20
0
–0.5
–1.5
–2.0
–2.0
0
16384
32768
49152
65535
0
CODE
16384
32768
49152
–50
–60
LTC1605-1
–70
–80
100
65535
TOTAL HARMONIC DISTORTION (dB)
–70
SINAD (dB)
88
86
84
82
80
1605-1/2 G07/F11
1M
Total Harmonic Distortion vs
Input Frequency (LTC1605-2)
90
10 15 20 25 30 35 40 45 50
FREQUENCY (kHz)
10k
100k
1k
RIPPLE FREQUENCY (Hz)
LTXXXX GXX
SINAD vs Input Frequency
(LTC1605-2)
fSAMPLE = 100kHz
fIN = 1kHz
SINAD = 87dB
THD = 101.1dB
SNR = 87.2dB
5
LTC1605-2
–40
1605-1/2 G05
1605-1/2 TA02/G04
0
–30
CODE
LTC1605-2 Nonaveraged
4096-Point FFT Plot
10
Power Supply Feedthrough
vs Ripple Frequency
–1.0
–1.5
0
1605-1/2 G03
POWER SUPPLY FEEDTHROUGH (dB)
2.0
0
LTC1605-1
–0.10
–80 –70 –60 –50 –40 –30 –20 –10
LOAD CURRENT (mA)
Typical DNL Curve
DNL (LSB)
INL (LSBs)
0
1605-1/2 G02
Typical INL Curve
MAGNITUDE (dB)
0.02
–0.08
SUPPLY VOLTAGE (V)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
Change in CAP Voltage vs
Load Current
Supply Current vs Temperature
–80
–90
–100
–110
1
10
INPUT FREQUENCY (kHz)
100
1605-1/2 G08
1
10
INPUT FREQUENCY (kHz)
100
1605-1/2 G09
5
LTC1605-1/LTC1605-2
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PIN FUNCTIONS
VIN (Pin 1): Analog Input. Connect through a 200Ω
resistor to the analog input. Full-scale input range is 0V
to 4V for the LTC1605-1 and ±4V for the LTC1605-2.
being the LSB. With BYTE high the upper eight bits and
the lower eight bits will be switched. The MSB is output
on Pin 15 and bit 8 is output on Pin 22. Bit 7 is output on
Pin 6 and the LSB is output on Pin 13.
AGND1 (Pin 2): Analog Ground. Tie to analog ground
plane.
R/C (Pin 24): Read/Convert Input. With CS low, a falling
edge on R/C puts the internal sample-and-hold into the
hold state and starts a conversion. With CS low, a rising
edge on R/C enables the output data bits.
REF (Pin 3): 2.5V Reference Output. Bypass with 2.2µF
tantalum capacitor. Can be driven with an external reference.
CS (Pin 25): Chip Select. Internally OR’d with R/C. With
R/C low, a falling edge on CS will initiate a conversion.
With R/C high, a falling edge on CS will enable the output
data.
CAP (Pin 4): Reference Buffer Output. Bypass with 2.2µF
tantalum capacitor.
AGND2 (Pin 5): Analog Ground. Tie to analog ground
plane.
BUSY (Pin 26): Output Shows Converter Status. It is low
when a conversion is in progress. Data valid on the rising
edge of BUSY. CS or R/C must be high when BUSY rises
or another conversion will start without time for signal
acquisition.
D15 to D8 (Pins 6 to 13): Three-State Data Outputs.
Hi-Z state when CS is high or when R/C is low.
DGND (Pin 14): Digital Ground.
D7 to D0 (Pins 15 to 22): Three-State Data Outputs.
Hi-Z state when CS is high or when R/C is low.
VANA (Pin 27): 5V Analog Supply. Bypass to ground with
a 0.1µF ceramic and a 10µF tantalum capacitor.
BYTE (Pin 23): Byte Select. With BYTE low, data will be
output with Pin 6 (D15) being the MSB and Pin 22 (D0)
VDIG (Pin 28): 5V Digital Supply. Connect directly to
Pin␣ 27.
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FU CTIO AL BLOCK DIAGRA
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4k
6K*
CSAMPLE
VIN
10k
OPEN*
20k
3.75k*
VANA
CSAMPLE
REF
VDIG
ZEROING SWITCHES
4k
2.5V REF
+
REF BUF
COMP
16-BIT CAPACITIVE DAC
–
CAP
(2.5V)
16
SUCCESSIVE APPROXIMATION
REGISTER
AGND1
•
•
•
OUTPUT LATCHES
AGND2
DGND
INTERNAL
CLOCK
*RESISTOR VALUES FOR THE LTC1605-2
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CONTROL LOGIC
1605-1/2 BD
CS
R/C
BYTE
BUSY
D15
D0
LTC1605-1/LTC1605-2
TEST CIRCUITS
Load Circuit for Output Float Delay
Load Circuit for Access Timing
5V
5V
1k
DBN
1k
DBN
1k
DBN
DBN
CL
CL
1k
50pF
1605-1/2 TC02
1605-1/2 TC01
B. HI-Z TO VOL AND VOH TO VOL
A. VOH TO HI-Z
B. VOL TO HI-Z
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A. HI-Z TO VOH AND VOL TO VOH
50pF
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APPLICATIONS INFORMATION
Conversion Details
The LTC1605-1/LTC1605-2 use a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 16-bit or two byte
parallel output. The ADC is complete with a precision
reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs. (Please
refer to the Digital Interface section for the data format.)
Conversion start is controlled by the CS and R/C inputs.
At the start of conversion, the successive approximation
register (SAR) is reset. Once a conversion cycle has
begun, it cannot be restarted.
During the conversion, the internal 16-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, VIN is connected through the resistor divider
and S1 to the sample-and-hold capacitor during the
acquire phase and the comparator offset is nulled by the
SAMPLE
RIN1
S1
SAMPLE
S3
CSAMPLE
–
VIN
RIN2
HOLD
S2
+
CDAC
COMPARATOR
DAC
VDAC
S
A
R
16-BIT
LATCH
1605-1/2 F01
Figure 1. LTC1605-1/LTC1605-2 Simplified Equivalent Circuit
autozero switch, S3. In this acquire phase, a minimum
delay of 2µs will provide enough time for the sample-andhold capacitor to acquire the analog signal. During the
convert phase, S3 opens, putting the comparator into the
compare mode. The input switch S2 switches CSAMPLE to
ground, injecting the analog input charge onto the summing junction. This input charge is successively compared with the binary-weighted charges supplied by the
capacitive DAC. Bit decisions are made by the high speed
comparator. At the end of a conversion, the DAC output
balances the VIN input charge. The SAR contents (a 16bit data word) that represents the VIN are loaded into the
16-bit output latches.
Driving the Analog Inputs
The nominal input range for the LTC1605-1 is 0V to 4V or
(1.6VREF) and for the LTC1605-2 the input range is ±4V
or (±1.6VREF). The inputs are overvoltage protected to
±25V. The input impedance is typically 10kΩ; therefore,
it should be driven by a low impedance source. Wideband
noise coupling into the input can be minimized by placing
a 1000pF capacitor at the input as shown in Figure 2. An
NPO-type capacitor gives the lowest distortion. Place the
capacitor as close to the device input pin as possible. If
an amplifier is to be used to drive the input, care should
be taken to select an amplifier with adequate accuracy,
linearity and noise for the application. The following list
is a summary of the op amps that are suitable for driving
the LTC1605-1/LTC1605-2. More detailed information is
available in the Linear Technology data books and
LinearViewTM CD-ROM.
LinearView is a trademark of Linear Technology Corporation
7
LTC1605-1/LTC1605-2
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APPLICATIONS INFORMATION
LT®1007 - Low noise precision amplifier. 2.7mA supply
current ±5V to ±15V supplies. Gain bandwidth product
8MHz. DC applications.
LT1097 - Low cost, low power precision amplifier. 300µA
supply current. ±5V to ±15V supplies. Gain bandwidth
product 0.7MHz. DC applications.
LT1227 - 140MHz video current feedback amplifier.
10mA supply current. ±5V to ±15V supplies. Low noise
and low distortion.
LT1360 - 37MHz voltage feedback amplifier. 3.8mA
supply current. ±5V to ±15V supplies. Good AC/DC
specs.
LT1363 - 50MHz voltage feedback amplifier. 6.3mA
supply current. Good AC/DC specs.
LT1364/LT1365 - Dual and quad 50MHz voltage feedback amplifiers. 6.3mA supply current per amplifier.
Good AC/DC specs.
LT1468 - 90MHz, 22V/µs 16-Bit Accurate Amplifier
AIN
200Ω
VIN
1000pF
33.2k
CAP
1605-1/2 F02
Figure 2. Analog Input Filtering
Internal Voltage Reference
The LTC1605-1/LTC1605-2 has an on-chip, temperature
compensated, curvature corrected, bandgap reference,
which is factory trimmed to 2.50V. The full-scale range of
the ADC is equal to (1.6VREF) or nominally 0V to 4V for the
LTC1605-1 and (±1.6VREF) or nominally ±4V for the
LTC1605-2. The output of the reference is connected to
the input of a unity-gain buffer through a 4k resistor (see
Figure 3). The input to the buffer or the output of the
reference is available at REF (Pin 3). The internal reference can be overdriven with an external reference if more
accuracy is needed. The buffer output drives the internal
DAC and is available at CAP (Pin 4). The CAP pin can be
used to drive a steady DC load of less than 2mA. Driving
an AC load is not recommended because it can cause the
performance of the converter to degrade.
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For minimum code transition noise the REF pin and the
CAP pin should each be decoupled with a capacitor to
filter wideband noise from the reference and the buffer
(2.2µF tantalum).
Offset and Gain Adjustments
The LTC1605-1/LTC1605-2 offset and full-scale errors
have been trimmed at the factory with the external
resistors shown in Figure 4. This allows for external
adjustment of offset and full scale in applications where
absolute accuracy is important. See Figure 5 for the offset
and gain trim circuit for the LTC1605-1/LTC1605-2.
First adjust the offset to zero by adjusting resistor R3.
Apply an input voltage of 30.5µV (0.5LSB) and adjust R3
so the code is changing between 0000 0000 0000 0001
and 0000 0000 0000 0000. The gain error is trimmed by
adjusting resistor R4. An input voltage of 3.999908V (FS
– 1.5LSB) is applied to VIN and R4 is adjusted until the
output code is changing between 1111 1111 1111 1110
and 1111 1111 1111 1111. Figure 6a shows the unipolar
transfer characteristic of the LTC1605-1.
For the LTC1605-2, first adjust the offset to zero by
adjusting resistor R3. Apply an input voltage of – 61µV
(– 0.5LSB) and adjust R3 so the code is changing between 1111 1111 1111 1111 and 0000 0000 0000 0000.
The gain error is trimmed by adjusting resistor R4. An
input voltage of 3.999817V (+ FS – 1.5LSB) is applied to
VIN and R4 is adjusted until the outut code is changing
between 0111 1111 1111 1110 and 0111 1111 1111
1111. Figure 6b shows the bipolar transfer characteristics of the LTC1605-2.
DC Performance
One way of measuring the transition noise associated
with a high resolution ADC is to use a technique where a
DC signal is applied to the input of the ADC and the
resulting output codes are collected over a large number
of conversions. For example, in Figure 7 the distribution
of output code is shown for a DC input that has been
digitized 10000 times. The distribution is Gaussian and
the RMS code transition is about 1LSB.
LTC1605-1/LTC1605-2
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APPLICATIONS INFORMATION
4k
3
REF
(2.5V)
2.2µF
111...110
VANA
OUTPUT CODE
+
–
4
CAP
(2.5V)
111...111
BANDGAP
REFERENCE
S
S
INTERNAL
CAPACITOR
DAC
2.2µF
UNIPOLAR
ZERO
000...001
FS = 4V
1LSB = FS/65536
000...000
1605-1/2 F03
0V 1
LSB
FS – 1LSB
INPUT VOLTAGE (V)
Figure 3. Internal or External Reference Source
1605-1/2 F06a
Figure 6a. LTC1605-1 Unipolar Transfer Characteristics
011...111
2
200Ω
1%
33.2k
1%
2.2µF
3
4
+
2.2µF
5
BIPOLAR
ZERO
011...110
VIN
AGND1
LTC1605-1
LTC1605-2
REF
OUTPUT CODE
1
+
0V TO 4V
OR ± 4V
INPUT
CAP
000...001
000...000
111...111
111...110
AGND2
100...001
FS = 8V
1LSB = FS/65536
1605-1/2 F04
100...000
Figure 4. 0V to 4V Input for the LTC1605-1
and ±4V for the LTC1605-2 Without Trim
– FS/2
–1 0V 1
LSB
LSB
INPUT VOLTAGE (V)
FS/2 – 1LSB
1605-1/2 F06b
Figure 6B. LTC1605-2 Bipolar Transfer Characteristics
0V TO 4V
OR ± 4V
INPUT 200Ω
1%
1
2
33.2k
1%
GAIN
TRIM
5V
R4
50k
OFFSET
TRIM
R3
50k
3000
REF
576k
4
+
3500
LTC1605-1
LTC1605-2
2.2µF
3
4000
AGND1
COUNT
+
4500
VIN
CAP
2000
1500
2.2µF
5
2500
1000
AGND2
500
1605-1/2 F05
Figure 5. 0V to 4V Input for the LTC1605-1 and
±4V for the LTC1605-2 with Offset and Gain Trim
0
–5 –4 –3 –2 –1 0 1
CODE
2
3
4
5
1605-1/2 F07
Figure 7. Histogram for 10000 Conversions
9
LTC1605-1/LTC1605-2
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DIGITAL INTERFACE
Internal Clock
The ADC has an internal clock that is trimmed to achieve
a typical conversion time of 7µs. No external adjustments
are required and, with the typical acquisition time of 1µs,
throughput performance of 100ksps is assured.
Timing and Control
Conversion start and data read are controlled by two
digital inputs: CS and R/C. To start a conversion and put
the sample-and-hold into the hold mode, bring CS and
R/C low for no less than 40ns. Once initiated, it cannot be
restarted until the conversion is complete. Converter
status is indicated by the BUSY output and this is low
while the conversion is in progress.
There are two modes of operation. The first mode is
shown in Figure 8. The digital input R/C is used to control
the start of conversion. CS is tied low. When R/C goes
low, the sample-and-hold goes into the hold mode and a
conversion is started. BUSY goes low and stays low
during the conversion and will go back high after the
conversion has been completed and the internal output
shift registers have been updated. R/C should remain low
for no less than 40ns. During the time R/C is low, the
digital outputs are in a Hi-Z state. R/C should be brought
back high within 3µs after the start of the conversion to
ensure that no errors occur in the digitized result. The
second mode, shown in Figure 9, uses the CS signal to
control the start of a conversion and the reading of the
digital output. In this mode, the R/C input signal should
be brought low no less than 10ns before the falling edge
of CS. The minimum pulse width for CS is 40ns. When CS
falls, BUSY goes low and will stay low until the end of the
conversion. BUSY will go high after the conversion has
been completed. The new data is valid when CS is
brought back low again to initiate a read. Again, it is
recommended that both R/C and CS return high within
3µs after the start of the conversion.
Output Data
The output data can be read as a 16-bit word or it can be
read as two 8-bit bytes. The format of the output data is
straight binary for the LTC1605-1 and two’s complement
for the LTC1605-2. The digital input pin BYTE is used to
control the two byte read. With the BYTE pin low, the first
eight MSBs are output on the D15 to D8 pins and the eight
LSBs are output on the D7 to D0 pins. When the BYTE pin
is taken high, the eight LSBs replace the eight MSBs
(Figure 10).
t1
R/C
t 11
t2
t4
t3
BUSY
t6
MODE
t5
ACQUIRE
CONVERT
ACQUIRE
t CONV
t ACQ
CONVERT
t9
DATA MODE
PREVIOUS
DATA VALID
HI-Z
t7
PREVIOUS
DATA VALID
DATA
VALID
NOT VALID
t8
Figure 8. Conversion Timing with Outputs Enabled After Conversion (CS Tied Low)
10
HI-Z
DATA
VALID
1605-1/2 F08
LTC1605-1/LTC1605-2
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t 10
t 10
t 10
t 10
R/C
t1
t1
CS
t3
t4
BUSY
t6
MODE
ACQUIRE
CONVERT
ACQUIRE
t CONV
HI-Z
DATA BUS
DATA
VALID
t 12
t7
HI-Z
1605-1/2 F09
Figure 9. Using CS to Control Conversion and Read Timing
t 10
t 10
R/C
CS
BYTE
PINS 6 TO 13
HI-Z
HIGH BYTE
t 12
PINS 15 TO 22
HI-Z
t 12
LOW BYTE
HI-Z
LOW BYTE
t7
HIGH BYTE
HI-Z
1605-1/2 F10
Figure 10. Using CS and BYTE to Control Data Bus Read Timing
11
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Dynamic Performance
FFT (Fast Fourier Transform) test techniques are used to
test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT
algorithm, the ADC’s spectral content can be examined
for frequencies outside the fundamental. Figure 11 shows
a typical LTC1605-2 FFT plot which yields a SINAD of
87dB and THD of –101.1dB.
Signal-to-Noise Ratio
MAGNITUDE (dB)
The Signal-to-Noise and Distortion Ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental
input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band
limited to frequencies from above DC and below half the
sampling frequency. Figure 11 shows a typical SINAD of
87dB with a 100kHz sampling rate and a 1kHz input.
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
fSAMPLE = 100kHz
fIN = 1kHz
SINAD = 87dB
THD = 101.1dB
SNR = 87.2dB
0
5
10 15 20 25 30 35 40 45 50
FREQUENCY (kHz)
1605-1/2 G07/F11
Figure 11. LTC1605-2 Nonaveraged 4096-Point FFT Plot
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as:
THD = 20log
12
√V22 + V32 + V42 ... + VN2
V1
where V1 is the RMS amplitude of the fundamental
frequency and V2 through VN are the amplitudes of the
second through Nth harmonics.
Board Layout, Power Supplies and Decoupling
Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best
performance from the LTC1605-1/LTC1605-2, a printed
circuit board is required. Layout for the printed circuit
board should ensure the digital and analog signal lines
are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC. The analog
input should be screened by AGND.
Figures 12 through 15 show a layout for a suggested
evaluation circuit which will help obtain the best performance from the 16-bit ADC. Additional information regarding the evaluation circuit and Gerber files for the PC
board layout are available from Linear Technology or
your local sales office. Pay particular attention to the
design of the analog and digital ground planes. The
DGND pin of the LTC1605-1/LTC1605-2 can be tied to the
analog ground plane. Placing the bypass capacitor as
close as possible to the power supply, the reference and
reference buffer output is very important. Low impedance common returns for these bypass capacitors are
essential to low noise operation of the ADC, and the PC
track width for these lines should be as wide as possible.
Also, since any potential difference in grounds between
the signal source and ADC appears as an error voltage in
series with the input signal, attention should be paid to
reducing the ground circuit impedance as much as
possible. The digital output latches and the onboard
sampling clock have been placed on the digital ground
plane. The two ground planes are tied together at the
power supply ground connection.
LTC1605-1/LTC1605-2
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Figure 12. Component Side Silkscreen for the Suggested LTC1605-1/LTC1605-2 Evaluation Circuit
ANALOG
GROUND PLANE
DIGITAL
GROUND PLANE
Figure 13. Bottom Side Showing Analog Ground Plane
ANALOG
GROUND PLANE
Figure 14. Component Side Showing Separate Analog
and Digital Ground Plane
13
2
1
2
1
2
R17
51
GND
NA
OUT
U8
1MHz, OSC
EXT_CLK
1
J1
J2
AIN
GND
E2
3
3
4
3
2
1
2
3
4
5
6
7
10
9
1
8
CLK
LOAD
ENP
ENT
A
B
C
OUT
TRIM
QA
QB
QC
QD
RCO
15
14
13
12
11
5
6
7
8
JP1
R18
200Ω
1%
VCC
R21, 2k
3
15
2
1
JP4
2
CLK
13
CS
VCC 3
VCC
Q
Q
JP5
2
C3
0.1µF
C4
2.2µF
C16
1000pF
C9
0.1µF
C8
0.1µF
C7
10µF
VKK
C5
0.1µF
R19
33.2k
1%
C10
0.1µF
DIGITAL I.C. BYPASSING
28
27
26
25
24
23
14
5
4
3
2
1
VDIG
VANA
BUSY
CS
R/C
BYTE
DGND
AGND2
CAP
REF
AGND1
VIN
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
U1
LTC1605-1
LTC1605-2
C11
0.1µF
VCC
D12
D13
D14
D15
U4B
74HC04
3
4
22 D0
21 D1
20 D2
19 D3
18 D4
17 D5
16 D6
15 D7
13 D8
12 D9
11 D10
10 D11
9
8
7
6
C12
0.1µF
R20
1K
C13
0.1µF
1
C1
15PF
11
9
8
D6
D7
7
D5
6
5
D3
D4
4
3
2
11
1
9
8
7
6
5
4
3
2
D2
D1
D0
D8
D9
D10
D11
D12
D13
D14
D15
C14
0.1µF
Figure 15. LTC1605-1 Suggested Evaluation Circuit Schematic
GND 1
RCEXT
CEXT
B
A
4
C2
2.2µF
U6A
74HC221
NORNAL 1
BYTE
REVERSE 3
C17
10µF
EXT VREF INT
VCC VDD
JP3
2
C6
22µF
10V
R16
20
INT 1 VCC
CLK
EXT 3
U4E
74HC04
11
10
U9
LT1019-2.5
GND
TEMP
CLR
D
NC2
+
INPUT HEATER
NC1
D16
MBR0520
U7
74HC160
U4D
74HC04
VCC
9
VKK
VIN
U5
LT1121
GND
2
VIN
7V TO 15V
1
E1
VIN
VKK
Q0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
U4C
74HC04
5
6
CLK
OC
D7
D6
D5
D4
D3
D2
D1
D0
U3
74HC574
CLK
OC
D7
D6
D5
D4
D3
D2
D1
D0
U2
74HC574
C15
10µF
19
12
13
14
15
16
17
18
19
1
U4A
74HC04
12
13
14
15
16
17
18
2
R0, 1.2k
R1, 1.2k
R2, 1.2k
R3, 1.2k
R4, 1.2k
R5, 1.2k
R6, 1.2k
R7, 1.2k
R8, 1.2k
R9, 1.2k
R10, 1.2k
R11, 1.2k
R12, 1.2k
R13, 1.2k
R14, 1.2k
20
19
18
17
16
15
14
D7
D0
D1
D2
D3
D4
D5
D6
GND
GND
CLK
D15
D0
D1
D2
D3
D4
12
13
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
11
10
9
8
7
6
5
4
3
2
1
D8
D9
D10
D11
D12
D13
D14
1605-1/2 F15
JP2
LED
ENABLE
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APPLICATIONS INFORMATION
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LTC1605-1/LTC1605-2
LTC1605-1/LTC1605-2
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TYPICAL APPLICATIO S
The circuit in Figure 16 is an example showing the LTC1605
16-bit A/D converter and LTC1391 8-channel MUX connected to a 68HC11 controller. The LTC1605’s 16-bit data
output is read in two 8-bit bytes using Pins 6 (MSB, Bit7)
through 13 (Bit8, Bit0), connected to the HC11’s PORTC.
The MUX’s 4-bit serial address data is sent using the
controller’s SPI.
The process to convert a channel’s input signal is shown
in sample listing A. It begins with shifting in the MUX’s
channel data while the SS signal is a logic high. The MUX
channel address is latched on the falling edge of SS and the
chosen channel’s input is applied at the LTC1605’s input,
Pin 1. Through the processor’s PORTA, a low-going pulse
is applied to the LTC1605’s R/C pin, initiating a conversion. The processor then monitors the BUSY output.
When this signal becomes a logic high, signaling the end
of conversion, the processor reads the high byte of the
conversion through PORTC. The low byte is read through
PORTC when the processor changes the BYTE signal to a
logic high. The timing relationship of the control signals
and data are shown in Figure 17.
Sample Listing A
*************************************************************************
*
*
* This example program selects the an LTC1391 MUX channel, initiates a *
* conversion, and retrieves conversion data. It stores the 16-bit data *
* in two consecutive memory locations. The program is designed for use *
* with the LTC1605’s /CS tied to ground (see timing diagram in
*
* Figure 17).
*
*
*
*************************************************************************
*
*****************************************
* 68HC11 register definitions
*
*****************************************
*
PORTA EQU
$1000 Parallel port A
*
Use Bit0 as an input for the LTC1605’s /BUSY signal
*
Use Bit3 as an output driving the LTC1605’s BYTE
*
input
PIOC
EQU
$1002 Parallel I/O control register
*
“STAF,STAI,CWOM,HNDS, OIN, PLS, EGA,INVB”
PORTC EQU
$1003 Port C data register
*
“Bit7,Bit6,Bit5,Bit4,Bit3,Bit2,Bit1,Bit0”
DDRC
EQU
$1007 Port D data direction register
*
“Bit7,Bit6,Bit5,Bit4,Bit3,Bit2,Bit1,Bit0”
*
1 = output, 0 = input
PORTD EQU
$1008 Port D data register
*
“ - , - , SS* ,CSK ;MOSI,MISO,TxD ,RxD “
DDRD
EQU
$1009 Port D data direction register
SPCR
EQU
$1028 SPI control register
*
“SPIE,SPE ,DWOM,MSTR;SPOL,CPHA,SPR1,SPR0”
SPSR
EQU
$1029 SPI status register
*
“SPIF,WCOL, - ,MODF; - , - , - , - “
SPDR
EQU
$102A SPI data register; Read-Buffer; Write-Shifter
*
* RAM variables to hold the LTC1605’s 14 conversion result
*
DIN1
EQU
$00
This memory location holds the LTC1605’s bits 15 - 08
DIN2
EQU
$01
This memory location holds the LTC1605’s bits 07 - 00
MUX
EQU
$02
This memory location holds the MUX address data
*
15
LTC1605-1/LTC1605-2
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TYPICAL APPLICATIO S
*****************************************
* Start GETDATA Routine
*
*****************************************
*
ORG
$C000 Program start location
INIT1 LDAA
#$03
0,0,0,0,0,0,1,1
*
“STAF=0,STAI=0,CWOM=0,HNDS=0, OIN=0, PLS=0, EGA=1,INVB=1”
STAA
PIOC
Ensures that the PIOC register’s status is the same
*
as after a reset, necessary of simple Port D manipulation
LDAA
#$00
0,0,0,0,0,0,0,0
*
“Bits 7 - 0 are used as inputs for the LTC1605’s data
STAA
DDRC
Direction of PortD’s bit are now set as inputs
LDAA
#$2F
-,-,1,0;1,1,1,1
*
-, -, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X
STAA
PORTD Keeps SS* a logic high when DDRD, Bit5 is set
LDAA
#$38
-,-,1,1;1,0,0,0
STAA
DDRD
SS* , SCK, MOSI are configured as Outputs
*
MISO, TxD, RxD are configured as Inputs
* DDRD’s Bit5 is a 1 so that port D’s SS* pin is a general output
LDAA
#$50
STAA
SPCR
The SPI is configured as Master, CPHA = 0, CPOL = 0
*
and the clock rate is E/2
*
(This assumes an E-Clock frequency of 4MHz. For higher
*
E-Clock frequencies, change the above value of $50 to a
*
value that ensures the SCK frequency is 2MHz or less.)
GETDATAPSHX
PSHY
PSHA
*
*****************************************
* Setup indecies
*
*****************************************
*
LDX
#$0
The X register is used as a pointer to the memory
*
locations that hold the conversion data
LDY
#$1000
*
*****************************************
* Ensure that a logic high is applied
*
* to the LTC1391’s /CS and the
*
* LTC1605’s R/C pins
*
*****************************************
*
BSET
PORTD,Y %00100000
This sets the SS* output bit to a logic
*
high, ensuring that the LTC1391’s CS*
*
input is a logic high while clocking
*
MUX address data into the LTC1391
BSET
PORTA,Y %00010000
This sets the R/C* output bit to a logic
*
high, ensuring that the LTC1605’s R/C*
*
input is a logic high before initiating
*
a conversion
*****************************************
16
LTC1605-1/LTC1605-2
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TYPICAL APPLICATIO S
* Retrieve the MUX address from memory
*
* and send it to the LTC1391
*
*****************************************
*
LDAA
MUX
Retrieve the MUX address from memory
ORAA
#$08
Enable the selected MUX address
STAA
SPDR
Select the MUX channel
WAIT1 LDAA
SPSR
This loop waits for the SPI to complete a serial
*
transfer/exchange by reading the SPI Status Register
BPL
WAIT1 The SPIF (SPI transfer complete flag) bit is the SPSR’s
*
MSB and is set to one at the end of an SPI transfer. The
*
branch will occur while SPIF is a zero.
BCLR
PORTD,Y %00100000
This forces a logic low on PORTD’s SS*,
*
latching the MUXes data
*
*****************************************
* Initiate a LTC1605 conversion
*
*****************************************
*
BCLR
BSET
PORTA,Y %00010000
PORTA,Y %00010000
Initiate a conversion
This sets the LTC1605’s R/C* to a logic
high
*
*
*****************************************
* Set the LTC1605’s BYTE input low to
*
* ensure that the high byte is present
*
* during the first read
*
*****************************************
*
LDAA
PORTA
Get the contents of Port A
ANDA
#%11110111
Set Bit3 low
STAA
PORTA
Set the LTC1605’s BYTE input low
*
*****************************************
* The next short loop ensures that the *
* LTC1605’s conversion is finished *
* before starting the data transfer*
*****************************************
*
CONVENDLDAA
PORTA
Retrieve the contents of port A
ANDA
#%00000001
Look at Bit0
*
Bit0 = Lo; the LTC1605’s conversion is not
*
complete
*
Bit0 = Hi; the LTC1605’s conversion is complete
BEQ
CONVEND
Branch to the loop’s beginning while Bit7
*
remains low
*
17
LTC1605-1/LTC1605-2
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TYPICAL APPLICATIO S
*************************************************************************
* This routine retrieves the LTC1605’s 16-bit data using two 8-bit
*
* reads. The BYTE input is manipulated through Port A’s Bit3. During *
* the first read when BYTE is low, the upper byte is read and stored in
* DIN1.During the second read when BYTE is high, the lower byte is
*
* read and stored in DIN2.
*
*************************************************************************
*
LDAA
PORTC Retrieve the LTC1605’s high byte
STAA
DIN1
Store the high byte
LDAA
PORTA Get the contents of Port A
ORAA
#%00001000
Set Bit3 high
STAA
PORTA Set the LTC1605’s BYTE input high
LDAA
PORTC Retrieve the LTC1605’s low byte
STAA
DIN2
Store the high byte
PULA
Restore the A register
PULY
Restore the Y register
PULX
Restore the X register
RTS
*
5V
2
3
4
5
6
7
V+
S1
D
3
15
14
V–
S3
DOUT
S4
DIN
S5
CS
S6
DLK
S7
DGND
13
8
1/2 LT1630
5V
2
0.1µF
+
–
4
12
1
LTC1605-1
LTC1605-2
200Ω
1%
1
22
21
17
20
16
+
2.2µF
USE FOR LTC1605-2
9
M0S1
SS
CLK
–5V SUPPLY FOR
LTC1605-2
VIN
33.2k
1%
5
CAP
AGND2
2.2µF
3
2
SPI
19
14
REF
AGND1
DGND
10µF
1µF
28
VDIG
27
VANA
6
D7/D15
7
D6/D14
8
D5/D13
9
D4/D12
10
D3/D11
11
D2/D10
12
D1/D9
13
D0/D8
18
4
11
10
5V
0.1µF
16
+
8
S0
S2
5V
0.1µF
LTC1391
1
BUSY
15
26
25
24
R/C
23
BYTE
PORTC, BIT7
PORTC, BIT6
PORTC, BIT5
PORTC, BIT4
PORTC, BIT3
PORTC, BIT2
PORTC, BIT1
PORTC, BIT0
PORTA, BIT0
CS
1605-1/2 F16
Figure 16. 8-Channel, 16-Bit Data Acquisition System with Interface to the 68HC11
18
PORTA, BIT4
PORTA, BIT3
LTC1605-1/LTC1605-2
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
G Package
28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
10.07 – 10.33*
(0.397 – 0.407)
28 27 26 25 24 23 22 21 20 19 18 17 16 15
7.65 – 7.90
(0.301 – 0.311)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
5.20 – 5.38**
(0.205 – 0.212)
1.73 – 1.99
(0.068 – 0.078)
0° – 8°
0.65
(0.0256)
BSC
0.55 – 0.95
(0.022 – 0.037)
0.13 – 0.22
(0.005 – 0.009)
NOTE: DIMENSIONS ARE IN MILLIMETERS
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.152mm (0.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE
0.05 – 0.21
(0.002 – 0.008)
0.25 – 0.38
(0.010 – 0.015)
G28 SSOP 1098
N Package
28-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
1.370*
(34.789)
MAX
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0.255 ± 0.015*
(6.477 ± 0.381)
0.300 – 0.325
(7.620 – 8.255)
0.130 ± 0.005
(3.302 ± 0.127)
0.045 – 0.065
(1.143 – 1.651)
0.020
(0.508)
MIN
0.009 – 0.015
(0.229 – 0.381)
(
+0.035
0.325 –0.015
8.255
+0.889
–0.381
)
0.125
(3.175)
MIN
0.065
(1.651)
TYP
0.005
(0.127)
MIN
0.100
(2.54)
BSC
0.018 ± 0.003
(0.457 ± 0.076)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
N28 1098
19
LTC1605-1/LTC1605-2
U
TYPICAL APPLICATIO
MUX
CS
MUX
DATA
CH0
CH1
CH2
R/C
BUSY
BYTE
ADC
DATA
HI BYTE
LO BYTE
DATA 0
HI BYTE
LO BYTE
HI BYTE
LO BYTE
DATA 1
1605-1/2 F17
Figure 17. This Is the Timing Relationship Between the Selected MUX Channel, Its Conversion Data
and the ADC and MUX Control Signals When Using the Sample Program In Listing 1. The Conversion
Process Is Latency Free: the Data Is Always Generated Based On the Currently Selected MUX Input
RELATED PARTS
PART NUMBER
LT ® 1019-2.5
LTC1274/LTC1277
LTC1415
LTC1419
LT1460-2.5
LTC1594/LTC1598
LTC1604
LTC1605
20
DESCRIPTION
Precision Bandgap Reference
Low Power 12-Bit, 100ksps ADCs
Single 5V, 12-Bit, 1.25Msps ADC
Low Power 14-Bit, 800ksps ADC
Micropower Precision Series Reference
Micropower 4-/8-Channel 12-Bit ADCs
16-Bit, 333ksps Sampling ADC
Low Power 100ksps 16-Bit ADC
Linear Technology Corporation
COMMENTS
0.05% Max, 5ppm/°C Max
10mW Power Dissipation, Parallel/Byte Interface
55mW Power Dissipation, 72dB SINAD
True 14-Bit Linearity, 81.5dB SINAD, 150mW Dissipation
0.075% Max, 10ppm/°C Max, Only 130µA Supply Current
Serial I/O, 3V and 5V Versions
±2.5V Input, 90dB SINAD, 100dB THD
Single 5V, ±10V Inputs
160512f LT/TP 0999 4K • PRINTED IN THE USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
 LINEAR TECHNOLOGY CORPORATION 1999