MOSEL VITELIC V436616R24V 128 MB 168-PIN UNBUFFERED DIMM 3.3 VOLT 16M x 64 PRELIMINARY Features Description ■ 168 Pin Unbuffered 16, 777, 216 x 64 bit Oganization SDRAM DIMM ■ Utilizes High Performance 256 Mbit, 16M x 16 SDRAM in TSOPII-54 Packages ■ Fully PC Board Layout Compatible to INTEL’S Rev 1.0 Module Specification ■ Single +3.3V (± 0.3V) Power Supply ■ Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) ■ Auto Refresh (CBR) and Self Refresh ■ All Inputs, Outputs are LVTTL Compatible ■ 8192 Refresh Cycles every 64 ms ■ Serial Present Detect (SPD) ■ SDRAM Performance The V436616R24V memory module is organized 16, 777, 216 x 64 bits in a 168 pin dual in line memory module (DIMM). The 16M x 64 memory module uses 4 Mosel-Vitelic 16M x 16 SDRAM. The x64 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. Component Used tCK tAC -7 Units CL=3 143 MHz CL=2 133 MHz Clock Access Time CAS CL=3 Latency CL=2 5.4 ns 5.4 ns Clock Frequency (max.) ■ Supported Latencies at 133 MHz Operation for Module CL tRCD tRP tRC 2 2 2 8 V436616R24V Rev. 1.1 January 2002 CLK 1 MOSEL VITELIC V436616R24V Pin Configurations (Front Side/Back Side) Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VSS I/O1 I/O2 I/O3 I/O4 VCC I/O5 I/O6 I/O7 I/O8 I/O9 VSS I/O10 I/O11 I/O12 I/O13 I/O14 VCC I/O15 I/O16 CBO* CB1* VSS NC NC VCC WE DQM0 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 DQM1 CS0 DU VSS A0 A2 A4 A6 A8 A10(AP) BA1 VCC VCC CLK0 VSS DU CS2 DQM2 DQM3 DU VCC NC NC CB2* CB3* VSS I/O17 I/O18 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 I/O19 I/O20 VCC I/O21 NC DU CKE1 VSS I/O22 I/O23 I/O24 VSS I/O25 I/O26 I/O27 I/O28 VCC I/O29 I/O30 I/O31 I/O32 VSS CLK2 NC WP SDA SCL VCC 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 VSS I/O33 I/O34 I/O35 I/O36 VCC I/O37 I/O38 I/O39 I/O40 I/O41 VSS I/O42 I/O43 I/O44 I/O45 I/O46 VCC I/O47 I/O48 CB4* CB5* VSS NC NC VCC CAS DQM4 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 DQM5 CS1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VCC CLK1 A12 VSS CKE0 CS3 DQM6 DQM7 DU VCC NC NC CB6* CB7* VSS I/O49 I/O50 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 I/O51 I/O52 VCC I/O53 NC DU NC VSS I/O54 I/O55 I/O56 VSS I/O57 I/O58 I/O59 I/O60 VCC I/O61 I/O62 I/O63 I/O64 VSS CLK3 NC SA0 SA1 SA2 VCC Notes: * These pins are not used in this module. Pin Names SA0–A2 Serial Data IN for Presence Detect A0–A12 Address Inputs I/O1–I/O64 Data Inputs/Outputs CB0–CB7 Check Bits (x72 Organization) RAS Row Address Strobe NC No Connection CAS Column Address Strobe DU Don’t Use WE Read/Write Input BA0, BA1 Bank Selects CKE0, CKE1 Clock Enable CS0–CS3 Chip Select CLK0–CLK3 Clock Input DQM0–DQM7 Data Mask VCC Power (+3.3 Volts) VSS Ground SCL Clock for Presence Detect SDA Serial Data OUT for Presence Detect V436616R24V Rev. 1.1 January 2002 2 MOSEL VITELIC V436616R24V Part Number Information V 4 3 66 16 R 2 4 V X T G - XX SPEED 75PC = PC133 CL3,2 75 = PC133 CL3 10PC = PC133 CL3,2 LEAD FINISH G = GOLD MOSEL VITELIC MANUFACTURED SDRAM 3.3V COMPONENT PACKAGE, T = TSOP WIDTH DEPTH COMPONENT A=0.17u B=0.14u REV LEVEL 168 PIN Unbuffered DIMM X16 COMPONENT LVTTL REFRESH RATE 8K 4 BANKS Functional Block Diagram 10 CLK1/3 3.3pF WE CS0 CS WE LDQM I/O1–I/O8 DQM0 I/O1–I/O8 10 CS 10 UDQM I/O9–I/O16 DQM1 I/O9–I/O16 WE LDQM I/O1–I/O8 DQM4 I/O33–I/O40 D0 10 UDQM I/O9–I/O16 DQM5 I/O41–I/O48 10 D2 CS2 CS WE LDQM I/O1–I/O8 DQM2 I/O17–I/O24 10 D1 10 E2PROM SPD (256 WORD X 8 BITS) SCL0 SA2 SA1 SA0 SDA WP 47K UDQM I/O9–I/O16 DQM7 I/O57–I/O64 10 CKE: SDRAM D0–D3 RAS RAS: SDRAM D0–D3 CAS CAS: SDRAM D0–D3 WE WE: SDRAM D0–D3 A(12:0) A(12:0): SDRAM D0–D3 BA0, BA1: SDRAM D0–D3 D0–D3 VCC D0/D2 CLK0/2 3.3pF V436616R24V Rev.1.1 January 2002 D3 CKE0 BA0, BA1 10 CS 10 UDQM I/O9–I/O16 DQM3 I/O25–I/O32 WE LDQM I/O1–I/O8 DQM6 I/O49–I/O56 C0–C7 D0–D3 VSS Two 0.1µF capacitors per each SDRAM D1/D3 3 MOSEL VITELIC V436616R24V Serial Presence Detect Information written into the E2PROM device during module production using a serial presence detect protocol (I 2C synchronous 2-wire bus) A serial presence detect storage device - is assembled onto the module. Information about the module configuration, speed, etc. is E2PROM SPD-Table: Hex Value Byte Number Function Described SPD Entry Value 16Mx64 0 Number of SPD bytes 128 80 1 Total bytes in Serial PD 256 08 2 Memory Type SDRAM 04 3 Number of Row Addresses (without BS bits) 13 0D 4 Number of Column Addresses (for x16 SDRAM) 9 09 5 Number of DIMM Banks 1 01 6 Module Data Width 64 40 7 Module Data Width (continued) 0 00 8 Module Interface Levels LVTTL 01 9 SDRAM Cycle Time at CL=3 7.5 ns 75 10 SDRAM Access Time from Clock at CL=3 5.4 ns 54 11 Dimm Config (Error Det/Corr.) none 00 12 Refresh Rate/Type Self-Refresh, 7.8µs 82 13 SDRAM width, Primary x16 10 14 Error Checking SDRAM Data Width n/a / x16 00 15 Minimum Clock Delay from Back to Back Random Column Address tccd = 1 CLK 01 16 Burst Length Supported 1, 2, 4, 8 0F 17 Number of SDRAM Banks 4 04 18 Supported CAS Latencies CL =2, 3 06 19 CS Latencies CS Latency = 0 01 20 WE Latencies WL = 0 01 21 SDRAM DIMM Module Attributes Non Buffered/Non Reg. 00 22 SDRAM Device Attributes: General Vcc tol ± 10% 0E 23 Minimum Clock Cycle Time at CAS Latency = 2 7.5 ns 75 24 Maximum Data Access Time from Clock for CL = 2 5.4 ns 54 25 Minimum Clock Cycle Time at CL = 1 Not Supported 00 26 Maximum Data Access Time from Clock at CL = 1 Not Supported 00 27 Minimum Row Precharge Time 15 ns 0F 28 Minimum Row Active to Row Active Delay tRRD 14ns 0E 29 Minimum RAS to CAS Delay tRCD 15 ns 0F 30 Minimum RAS Pulse Width tRAS 42 ns 2A V436616R24V Rev. 1.1 January 2002 4 MOSEL VITELIC V436616R24V SPD-Table: (Continued) Hex Value Byte Number Function Described SPD Entry Value 16Mx64 128 MByte 20 31 Module Bank Density (Per Bank) 32 SDRAM Input Setup Time 1.5 ns 15 33 SDRAM Input Hold Time 0.8 ns 08 34 SDRAM Data Input Setup Time 1.5 ns 15 35 SDRAM Data Input Hold Time 0.8 ns 08 36-61 Superset Information (May be used in Future) 62 SPD Revision 63 Checksum for Bytes 0 - 62 64 Manufacturer’s JEDEC ID Code 65-71 72 00 Revision 2.0 02 E4 Mosel Vitelic 40 Manufacturer’s JEDEC ID Code (cont.) 00 Manufacturing Location 73-90 Module Part Number (ASCII) 91-92 PCB Identification Code 93 Assembly Manufacturing Date (Year) 94 Assembly Manufacturing Date (Week) V436616R24V 95-98 Assembly Serial Number 99-125 Reserved 00 126 Intel Specification for Frequency 64 127 Supported Features 8F 128+ Unused Storage Location 00 DC Characteristics TA = 0°C to 70°C; VSS = 0 V; VDD, VDDQ = 3.3V ± 0.3V Limit Values Symbol Parameter Min. Max. Unit VIH Input High Voltage 2.0 VCC +0.3 V V IL Input Low Voltage –0.5 0.8 V V OH Output High Voltage (IOUT = –2.0 mA) 2.4 — V V OL Output Low Voltage (IOUT = 2.0 mA) — 0.4 V II(L) Input Leakage Current, any input (0 V < VIN < 3.6 V, all other inputs = 0V) –40 40 µA IO(L) Output leakage current (DQ is disabled, 0V < VOUT < V CC) –40 40 µA V436616R24V Rev.1.1 January 2002 5 MOSEL VITELIC V436616R24V Capacitance TA = 0°C to 70°C; VDD = 3.3V ± 0.3V, f = 1 MHz Limit Values Symbol Parameter Max. 16M x 64 Unit CI1 Input Capacitance (A0 to A11, RAS, CAS, WE) 60 pF CI2 Input Capacitance (CS0-CS3) 30 pF CICL Input Capacitance (CLK0-CLK3) 22 pF CI3 Input Capacitance (CKE0, CKE1) 50 pF CI4 Input Capacitance (DQM0-DQM7) 15 pF CIO Input/Output Capacitance (I/O1-I/064) 15 pF CSC Input Capacitance (SCL, SA0-2) 8 pF CSD Input/Output Capacitance (SA0-SA2) 10 pF Absolute Maximum Ratings Parameter Max. Units Voltage on VDD Supply Relative to V SS -1 to 4.6 V Voltage on Input Relative to VSS -1 to 4.6 V Operating Temperature 0 to +70 °C -55 to 125 °C 3.2 W Storage Temperature Power Dissipation Operating Currents TA = 0°C to 70°C, VCC = 3.3V ± 0.3V (Recommended operating conditions otherwise noted) Symbol Parameter & Test Condition ICC1 Operating Current tRC = tRCMIN., tCK= tCKMIN. Active-precharge command cycling, without Burst Operation 1 bank operation Precharge Standby Current in Power Down Mode CS =VIH , CKE≤ VIL(max) ICC2P ICC2PS ICC2N ICC2NS ICC3 ICC3P ICC4 Precharge Standby Current in Non-Power Down Mode CS =VIH , CKE≥ VIL(max) Unit Note 920 mA 7 tCK = min. 12 mA 7 tCK = Infinity 8 mA 7 160 mA 20 mA 200 mA 40 mA 600 mA tCK = min. tCK = Infinity CKE > VIH(MIN.) No Operating Current tCK = min, CS = VIH(min) bank ; active state ( 4 banks) CKE < VIL(MAX.) (Power down mode) Burst Operating Current tCK = min Read/Write command cycling V436616R24V Rev. 1.1 January 2002 Max. 6 7,8 MOSEL VITELIC V436616R24V Operating Currents TA = 0°C to 70°C, VCC = 3.3V ± 0.3V (Recommended operating conditions otherwise noted) (Continued) Symbol Parameter & Test Condition Max. Unit Note 7 ICC5 Auto Refresh Current tCK = min Auto Refresh command cycling 960 mA ICC6 Self Refresh Current Self Refresh Mode, CKE<0.2V 12 mA 6.8 mA L-version Notes: 1. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and tRC. Input signals are changed one time during tCK. 2. These parameter depend on output loading. Specified values are obtained with output open. AC Characteristics TA = 0° to 70°C; VSS = 0V; VCC = 3.3V ± 0.3V, tT = 1 ns Limit Values # Symbol Parameter Min. Max. Unit Clock Cycle Time CAS Latency = 3 CAS Latency = 2 7.5 7.5 – – s ns ns Clock Frequency CAS Latency = 3 CAS Latency = 2 – – 133 133 MHz MHz Access Time from Clock CAS Latency = 3 CAS Latency = 2 – _ 5.4 6.0 ns ns Note Clock and Clock Enable 1 2 3 tCK tCK tAC 2, 4 4 tCH Clock High Pulse Width 2.5 – ns 5 tCL Clock Low Pulse Width 2.5 – ns 6 tT Transition Tim 0.3 1.2 ns Setup and Hold Times 7 tIS Input Setup Time 1.5 – ns 5 8 tIH Input Hold Time 0.8 – ns 5 9 tCKS Input Setup Time 1.5 – ns 5 10 tCKH CKE Hold Time 0.8 – ns 5 11 tRSC Mode Register Set-up Time 14 – ns 12 tSB 0 7.5 ns Power Down Mode Entry Time V436616R24V Rev.1.1 January 2002 7 MOSEL VITELIC V436616R24V AC Characteristics TA = 0° to 70°C; VSS = 0V; VCC = 3.3V ± 0.3V, tT = 1 ns (Continued) Limit Values # Symbol Parameter Min. Max. Unit Note Row to Column Delay Time 15 – ns 6 Common Parameters 13 tRCD 14 tRP Row Precharge Time 15 – ns 6 15 tRAS Row Active Time 42 100K ns 6 16 tRC Row Cycle Time 60 – ns 6 17 tRRD Activate(a) to Activate(b) Command Period 15 – ns 6 18 tCCD CAS(a) to CAS(b) Command Period 1 – CLK Refresh Period (8192 cycles) — 64 ms Self Refresh Exit Time 1 Refresh Cycle 19 tREF 20 tSREX CLK Read Cycle 21 tOH Data Out Hold Time 3 – ns 22 tLZ Data Out to Low Impedance Time 1 – ns 23 tHZ Data Out to High Impedance Time 3 7.5 ns 24 tDQZ DQM Data Out Disable Latency – 2 CLK 25 tWR Write Recovery Time 2 – CLK 26 tDQW DQM Write Mask Latency 0 – CLK Write Cycle V436616R24V Rev. 1.1 January 2002 8 2 7 MOSEL VITELIC V436616R24V Notes: 1. The specified values are valid when addresses are changed no more than once during t CK(min.) and when No Operation commands are registered on every rising clock edge during t RC(min). Values are shown per module bank. 2. The specified values are valid when data inputs (DQ’s) are stable during t RC(min.). 3. All AC characteristics are shown for device level. An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 4. AC timing tests have VIL = 0.4V and V IH = 2.4V with the timing referenced to the 1.4V crossover point. The transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0V. + 1.4 V tCH 2.4V CLOCK 50 Ohm 0.4V tCL tSETUP Z=50 Ohm tT I/O tHOLD 50 pF 1.4V INPUT tAC tAC tLZ I/O tOH 50 pF 1.4V OUTPUT Measurement conditions for tac and toh tHZ 5. If clock rising time is longer than 1 ns, a time (tT/2 -0.5) ns has to be added to this parameter. 6. Rated at 1.5V 7. If tT is longer than 1 ns, a time (tT -1) ns has to be added to this parameter. 8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-up” the device. 9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 10. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. 11. tDAL is equivalent to tDPL + tRP. V436616R24V Rev.1.1 January 2002 9 MOSEL VITELIC V436616R24V Package Diagram SDRAM DIMM Module Package 5.250 (133.350) R 0.079 (R 2.000) 0.157 ± 0.004 (4.000 ± 0.100) 0.350 (8.890) B A .118DIA ± 0.004 (3.000DIA ± 0.100) 0.250 (6.350) .450 (11.430) 0.100 Min (2.540 Min) 0.700 (17.780) 0.118 (3.000) 1.000 (25.40) 0.089 (2.26) 5.014 (127.350) 0.118 (3.000) C 0.250 (6.350) 1.450 (36.830) 2.150 (54.61) 4.550 (115.57) 0.200 Min (5.08 Min) 0.100 Max (2.54 Max) 0.100 Min 0.250 (6.350) 0.250 (6.350) 0.123 ± .005 (3.125 ± .125) 0.079 ± 0.004 (2.000 ± 0.100) Detail A 0.039 ± 0.002 (1.000 ± 0.050) 0.123 ± 0.005 (3.125 ± 0.125) 0.079 ± 0.004 (2.000 ± 0.100) Detail B Tolerances : ± 0.005(.13) unless otherwise specified V436616R24V Rev. 1.1 January 2002 (2.540 Min) 0.050 ± 0.0039 (1.270 ± 0.10) 10 0.008 ± 0.006 (0.200 ± 0.150) 0.050 (1.270) Detail C MOSEL VITELIC V436616R24V Label Information Module Density MOSEL VITELIC Part Number Criteria of PC100 or PC133 (refer to MVI datasheet) DIMM manufacture date code V436616R24VXXX-XX 128MB CLX PC133U-XXX-542-A XXXX-XXXXXXX Assembly in Taiwan PC133 U -XXX UNBUFFERED DIMM A Gerber file Intel PC100 x16 Based CL= 3 or 2 (CLK) tRCD= 3 or 2 (CLK) tRP= 3 or 2 (CLK) V436616R24V Rev.1.1 January 2002 54 2 CAS Latency 2=CL2 3=CL3 JEDEC SPD Revision 2 tAC = 5.4 ns 11 MOSEL VITELIC V436616R24V WORLDWIDE OFFICES U.S.A. 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MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC. V436616R24V Rev. 1.1 January 2002 12