MOSEL VITELIC V43658R04V 3.3 VOLT 8M x 64 UNBUFFERED SDRAM MODULE PRELIMINARY Features Description ■ 168 Pin Unbuffered 8,388,608 x 64 bit Oganization SDRAM DIMM ■ Utilizes High Performance 128 Mbit, 8M x 16 SDRAM in TSOPII-54 Packages ■ Fully PC Board Layout Compatible to INTEL’S Rev 1.0 Module Specification ■ Single +3.3V (± 0.3V) Power Supply ■ Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) ■ Auto Refresh (CBR) and Self Refresh ■ All Inputs, Outputs are LVTTL Compatible ■ 4096 Refresh Cycles every 64 ms ■ Serial Present Detect (SPD) ■ SDRAM Performance The V43658R04V memory module is organized 8,388,608 x 64 bits in a 168 pin dual in line memory module (DIMM). The 8M x 64 memory module uses 4 Mosel-Vitelic 8M x 16 SDRAM. The x64 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. V43658R04V Rev. 1.0 March 2002 Part Number 1 Speed Grade Configuration V43658R04VXTG-75 -75, CL=3 (133 MHz) 8M x 64 V43658R04VXTG-75PC -75PC, CL=2,3 (133 MHz) 8M x 64 V43658R04VXTG-10PC -10PC, CL=2,3 (100 MHz) 8M x 64 V43658R04V MOSEL VITELIC Pin Configurations (Front Side/Back Side) Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VSS I/O1 I/O2 I/O3 I/O4 VCC I/O5 I/O6 I/O7 I/O8 I/O9 VSS I/O10 I/O11 I/O12 I/O13 I/O14 VCC I/O15 I/O16 CBO* CB1* VSS NC NC VCC WE DQM0 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 DQM1 CS0 DU VSS A0 A2 A4 A6 A8 A10(AP) BA1 VCC VCC CLK0 VSS DU CS2 DQM2 DQM3 DU VCC NC NC CB2* CB3* VSS I/O17 I/O18 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 I/O19 I/O20 VCC I/O21 NC DU CKE1 VSS I/O22 I/O23 I/O24 VSS I/O25 I/O26 I/O27 I/O28 VCC I/O29 I/O30 I/O31 I/O32 VSS CLK2 NC WP SDA SCL VCC 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 VSS I/O33 I/O34 I/O35 I/O36 VCC I/O37 I/O38 I/O39 I/O40 I/O41 VSS I/O42 I/O43 I/O44 I/O45 I/O46 VCC I/O47 I/O48 CB4* CB5* VSS NC NC VCC CAS DQM4 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 DQM5 CS1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VCC CLK1 NC VSS CKE0 CS3 DQM6 DQM7 DU VCC NC NC CB6* CB7* VSS I/O49 I/O50 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 I/O51 I/O52 VCC I/O53 NC DU NC VSS I/O54 I/O55 I/O56 VSS I/O57 I/O58 I/O59 I/O60 VCC I/O61 I/O62 I/O63 I/O64 VSS CLK3 NC SA0 SA1 SA2 VCC Notes: * These pins are not used in this module. Pin Names A0–A11 Address Inputs I/O1–I/O64 Data Inputs/Outputs RAS Row Address Strobe CAS Column Address Strobe WE Read/Write Input BA0, BA1 Bank Selects CKE0, CKE1 Clock Enable CS0–CS3 Chip Select CLK0–CLK3 Clock Input DQM0–DQM7 Data Mask VCC Power (+3.3 Volts) VSS Ground SCL Clock for Presence Detect V43658R04V Rev. 1.0 March 2002 2 SDA Serial Data OUT for Presence Detect SA0–A2 Serial Data IN for Presence Detect CB0–CB7 Check Bits (x72 Organization) NC No Connection DU Don’t Use V43658R04V MOSEL VITELIC Part Number Information V 4 3 65 8 R 0 4 V X T G - XX MOSEL VITELIC MANUFACTURED SDRAM SPEED 75PC = PC133 CL2,3 75 = PC133 CL3 10PC = PC100 CL2 LEAD FINISH G = GOLD 3.3V COMPONENT PACKAGE, T=TSOP WIDTH DEPTH COMPONENT REV LEVEL 168-pins unbuffered DIMM X16 COMPONENT LVTTL REFRESH RATE 4K 4 BANKS Block Diagram 10 CLK1/3 10pF WE CS0 CS WE LDQM I/O1–I/O8 DQM0 I/O1–I/O8 10 CS 10 UDQM I/O9–I/O16 DQM1 I/O9–I/O16 WE LDQM I/O1–I/O8 DQM4 I/O33–I/O40 D0 10 UDQM I/O9–I/O16 DQM5 I/O41–I/O48 10 D2 CS2 CS WE LDQM I/O1–I/O8 DQM2 I/O17–I/O24 10 D1 10 E2PROM SPD (256 WORD X 8 BITS) SCL0 SA2 SA1 SA0 SDA WP 47K UDQM I/O9–I/O16 DQM7 I/O57–I/O64 10 CKE: SDRAM D0–D3 RAS RAS: SDRAM D0–D3 CAS CAS: SDRAM D0–D3 WE WE: SDRAM D0–D3 A(11:0) A(11:0): SDRAM D0–D3 BA0, BA1: SDRAM D0–D3 D0–D3 VCC D0/D2 CLK0/2 15pF V43658R04V Rev.1.0 March 2002 D3 CKE0 BA0, BA1 10 CS 10 UDQM I/O9–I/O16 DQM3 I/O25–I/O32 WE LDQM I/O1–I/O8 DQM6 I/O49–I/O56 C0–C7 D0–D3 VSS Two 0.1µF capacitors per each SDRAM D1/D3 3 V43658R04V MOSEL VITELIC Serial Presence Detect Information written into the E2PROM device during module production using a serial presence detect protocol (I2C synchronous 2-wire bus) A serial presence detect storage device - is assembled onto the module. Information about the module configuration, speed, etc. is E2PROM SPD Table Byte Number Hex Value Function Described SPD Entry Value -75PC -75 -10PC 0 Number of SPD bytes 128 80 80 80 1 Total bytes in Serial PD 256 08 08 08 2 Memory Type SDRAM 04 04 04 3 Number of Row Addresses (without BS bits) 12 0C 0C 0C 4 Number of Column Addresses (for x16 SDRAM) 9 09 09 09 5 Number of DIMM Banks 1 01 01 01 6 Module Data Width 64 40 40 40 7 Module Data Width (continued) 0 00 00 00 8 Module Interface Levels LVTTL 01 01 01 9 SDRAM Cycle Time at CL=3 7.5 ns/10.0 ns 75 75 A0 10 SDRAM Access Time from Clock at CL=3 5.4 ns/6.0 ns 54 54 60 11 Dimm Config (Error Det/Corr.) none 00 00 00 12 Refresh Rate/Type Self-Refresh, 15.6µs 80 80 80 13 SDRAM width, Primary x16 10 10 10 14 Error Checking SDRAM Data Width n/a / x8 00 00 00 15 Minimum Clock Delay from Back to Back Random Column Address tccd = 1 CLK 01 01 01 16 Burst Length Supported 1, 2, 4, 8 0F 0F 0F 17 Number of SDRAM Banks 4 04 04 04 18 Supported CAS Latencies CL = 3, 2 06 06 06 19 CS Latencies CS Latency = 0 01 01 01 20 WE Latencies WL = 0 01 01 01 21 SDRAM DIMM Module Attributes Non Buffered/Non Reg. 00 00 00 22 SDRAM Device Attributes: General Vcc tol ± 10% 0E 0E 0E 23 Minimum Clock Cycle Time at CAS Latency = 2 7.5 ns/10.0 ns 75 A0 A0 24 Maximum Data Access Time from Clock for CL = 2 5.4 ns/6.0 ns 54 60 60 25 Minimum Clock Cycle Time at CL = 1 Not Supported 00 00 00 26 Maximum Data Access Time from Clock at CL =1 Not Supported 00 00 00 27 Minimum Row Precharge Time 15 ns/20 ns 0F 14 14 V43658R04V Rev. 1.0 March 2002 4 V43658R04V MOSEL VITELIC SPD (Continued)Table Byte Number Hex Value Function Described SPD Entry Value -75PC -75 -10PC 14 ns/15 ns/16 ns 0E 0F 10 28 Minimum Row Active to Row Active Delay tRRD 29 Minimum RAS to CAS Delay tRCD 15 ns/20 ns 0F 14 14 30 Minimum RAS Pulse Width tRAS 42 ns/45 ns 2A 2D 2D 31 Module Bank Density (Per Bank) 64 MByte 10 10 10 32 SDRAM Input Setup Time 1.5 ns/2.0 ns 15 15 20 33 SDRAM Input Hold Time 0.8 ns/1.0 ns 08 08 10 34 SDRAM Data Input Setup Time 1.5 ns/2.0 ns 15 15 20 35 SDRAM Data Input Hold Time 0.8 ns/1.0 ns 08 08 10 00 00 00 02 02 12 D1 16 84 40 40 40 00 00 00 Reserved 00 00 00 126 Intel Specification for Frequency 64 64 64 127 Supported frequency 128+ Unused Storage Location 00 00 00 62-61 Superset Information (May be used in Future) 62 SPD Revision 63 Checksum for Bytes 0 - 62 64 Manufacturer’s JEDEC ID Code 65-71 72 Manufacturing Location Module Part Number (ASCII) 91-92 PCB Identification Code 93 Assembly Manufacturing Date (Year) 94 Assembly Manufacturing Date (Week) 99-125 Mosel Vitelic Manufacturer’s JEDEC ID Code (cont.) 73-90 95-98 Revision 2/1.2 V43658R04V Assembly Serial Number DC Characteristics TA = 0°C to 70°C; VSS = 0 V; VDD, VDDQ = 3.3V ± 0.3V Limit Values Symbol Parameter Min. Max. Unit VIH Input High Voltage 2.0 VCC +0.3 V VIL Input Low Voltage –0.5 0.8 V V OH Output High Voltage (IOUT = –2.0 mA) 2.4 — V VOL Output Low Voltage (IOUT = 2.0 mA) — 0.4 V V43658R04V Rev.1.0 March 2002 5 V43658R04V MOSEL VITELIC Limit Values Symbol Parameter Min. Max. Unit II(L) Input Leakage Current, any input (0 V < VIN < 3.6 V, all other inputs = 0V) –40 40 µA IO(L) Output leakage current (DQ is disabled, 0V < VOUT < VCC) –40 40 µA Capacitance TA = 0°C to 70°C; VDD = 3.3V ± 0.3V, f = 1 MHz Limit Values Symbol Parameter Max. 8M x 64 Unit CI1 Input Capacitance (A0 to A11, RAS, CAS, WE) 60 pF CI2 Input Capacitance (CS0-CS3) 30 pF CICL Input Capacitance (CLK0-CLK3) 22 pF CI3 Input Capacitance (CKE0, CKE1) 50 pF CI4 Input Capacitance (DQM0-DQM7) 15 pF CIO Input/Output Capacitance (I/O1-I/064) 15 pF CSC Input Capacitance (SCL, SA0-2) 8 pF CSD Input/Output Capacitance (SA0-SA2) 10 pF Absolute Maximum Ratings Parameter Max. Units Voltage on VDD Supply Relative to V SS -1 to 4.6 V Voltage on Input Relative to VSS -1 to 4.6 V Operating Temperature 0 to +70 °C -55 to 125 °C 4 W Storage Temperature Power Dissipation V43658R04V Rev. 1.0 March 2002 6 V43658R04V MOSEL VITELIC Operating Currents TA = 0°C to 70°C, VCC = 3.3V ± 0.3V (Recommended operating conditions otherwise noted) Max. Symbol ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3N ICC3P Parameter & Test Condition -75PC /-75 -10PC Unit Note 680 600 mA 7 Operating Current tRC = tRCMIN., tCK= tCKMIN. Active-precharge command cycling, without Burst Operation 1 bank operation Precharge Standby Current in Power Down Mode CS =VIH , CKE≤ VIL(max) tCK = min. 6 6 mA 7 tCK = Infinity 4 4 mA 7 Precharge Standby Current in Non-Power Down Mode CS =VIH , CKE≥ VIL(max) tCK = min. 180 140 mA tCK = Infinity 20 20 mA No Operating Current tCK = min, CS = VIH(min) bank ; active state ( 4 banks) CKE>= VIH(MIN.) 220 180 mA CKE <= VIL(MAX.) (Power down mode) 40 40 mA 440 360 mA 7,8 7 ICC4 Burst Operating Current tCK = min Read/Write command cycling ICC5 Auto Refresh Current tCK = min Auto Refresh command cycling 1000 840 mA ICC6 Self Refresh Current Self Refresh Mode, CKE=<0.2V 6 6 mA 3.2 3.2 mA L-version Notes: 1. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and tRC . Input signals are changed one time during tCK. 2. These parameter depend on output loading. Specified values are obtained with output open. V43658R04V Rev.1.0 March 2002 7 V43658R04V MOSEL VITELIC AC Characteristics 3,4 TA = 0° to 70°C; VSS = 0V; VCC = 3.3V ± 0.3V, tT = 1 ns Limit Values -75PC # Symbol Parameter Min. -75 Max. Min. -10PC Max. Min. Max. Unit Note Clock and Clock Enable 1 2 3 tCK fCK tAC Clock Cycle Time CAS Latency = 3 CAS Latency = 2 7.5 7.5 System frequency CAS Latency = 3 CAS Latency = 2 – – 133 133 – – 133 100 – – 100 100 MHz MHz Clock Access Time CAS Latency = 3 CAS Latency = 2 – – 5.4 6 – – 5.4 6 – – 6 6 ns ns 7.5 10 10 10 ns ns 4,5 4 tCH Clock High Pulse Width 2.5 – 2.5 – 3 – ns 6 5 tCL Clock Low Pulse Width 2.5 – 2.5 – 3 – ns 6 6 tCS Input Setup time 1.5 – 1.5 – 2 – ns 7 7 tCH Input Hold Time 0.8 – 0.8 – 1 – ns 7 8 tCKSP CKE Setup Time (Power down mode) 2 – 2 – 2 – ns 8 9 tCKSR CKE Setup Time (Self Refresh Exit) 8 – 8 – 8 – ns 9 10 tT Transition time (rise and fall) 1 – 1 – 1 – ns RAS to CAS delay 15 – 20 – 20 – ns Common Parameters 11 tRCD 12 tRC Cycle Time 70 120k 70 120k 70 120k ns 13 tRAS Active Command Period 42 – 45 – 45 – ns 14 tRP Precharge Time 15 – 20 – 20 – ns 15 tRRD Bank to Bank Delay Time 14 – 15 – 20 – ns 16 tCCD CAS to CAS delay time (same bank) 1 – 1 – 1 – CLK Refresh Cycle 17 tSREX Self Refresh Exit Time 10 – 10 – 10 – ns 9 18 tREF Refresh Period (4096 cycles) 64 – 64 – 64 – ms 8 4 Read Cycle 19 tOH Data Out Hold Time 3 – 3 – 3 – ns 20 tLZ Data Out to Low Impedance Time 0 – 0 – 0 – ns 21 tHZ Data Out to High Impedance Time 3 7.5 3 7.5 3 8 ns 22 tDQZ DQM Data Out Disable Latency 2 – 2 – 2 – CLK 10 Write Cycle 23 tDPL Data input to Precharge (write recovery) 1 – 1 – 1 – CLK 24 tDAL Data In to Active/refresh 5 – 5 – 5 – CLK 25 tDQW DQM Write Mask Latency 0 – 0 – 0 – CLK V43658R04V Rev. 1.0 March 2002 8 11 V43658R04V MOSEL VITELIC Notes: 1. The specified values are valid when addresses are changed no more than once during tCK(min.) and when No Operation commands are registered on every rising clock edge during tRC(min). Values are shown per module bank. 2. The specified values are valid when data inputs (DQ’s) are stable during tRC(min.). 3. All AC characteristics are shown for device level. An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 4. AC timing tests have VIL = 0.4V and V IH = 2.4V with the timing referenced to the 1.4V crossover point. The transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0V. + 1.4 V tCH 2.4V CLOCK 50 Ohm 0.4V tCL tSETUP Z=50 Ohm tT I/O tHOLD 50 pF 1.4V INPUT tAC tAC tLZ I/O tOH 50 pF 1.4V OUTPUT Measurement conditions for tac and toh tHZ 5. If clock rising time is longer than 1 ns, a time (tT/2 -0.5) ns has to be added to this parameter. 6. Rated at 1.5V 7. If tT is longer than 1 ns, a time (tT -1) ns has to be added to this parameter. 8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-up” the device. 9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 10. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. 11. tDAL is equivalent to tDPL + tRP. V43658R04V Rev.1.0 March 2002 9 V43658R04V MOSEL VITELIC Package Diagram SDRAM DIMM Module Package All measurements in mm 133.35 (2.54 max) 10 11 40 41 84 3.0 1 17.78 35.00 127.35 42.18 1.27 ± 0.10 66.68 A 85 B 94 95 124 C 125 168 6.35 3.125 3.125 6.35 2.0 4.45 8.25 2.26 RADIUS 1.27 + 0.10 Tolerances: ± (0.13) unless otherwise specified. V43658R04V Rev. 1.0 March 2002 1.0 + 0.5 0.2 ± 0.15 2.0 Detail B Detail A 1.27 2.4 min. D 10 Detail C V43658R04V MOSEL VITELIC Lable Information Module Density MOSEL VITELIC Part Number Criteria of PC100 or PC133 (refer to MVI datasheet) DIMM manufacture date code V43658R04VXXX-XX 64MB CLX PC133U-XXX-542-A XXXX-XXXXXXX Assembly in Taiwan PC133 U -XXX UNBUFFERED DIMM A Gerber file Intel PC100 x16 Based CL= 3 or 2 (CLK) tRCD= 3 or 2 (CLK) tRP= 3 or 2 (CLK) V43658R04V Rev.1.0 March 2002 54 2 CAS Latency 2=CL2 3=CL3 JEDEC SPD Revision 2 tAC = 5.4 ns 11 V43658R04V MOSEL VITELIC WORLDWIDE OFFICES U.S.A. TAIWAN SINGAPORE UK & IRELAND 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 10 ANSON ROAD #23-13 INTERNATIONAL PLAZA SINGAPORE 079903 PHONE: 65-3231801 FAX: 65-3237013 NO 19 LI HSIN ROAD SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. 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MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC. V43658R04V Rev. 1.0 March 2002 12