MOSEL V436532S04VATG

MOSEL VITELIC
V436532S04VATG-75
3.3 VOLT 32M x 64 HIGH PERFORMANCE
PC133 UNBUFFERED SDRAM MODULE
The V436532S04VATG-75 memory module is
organized 33,554,432 x 64 bits in a 168 pin dual in
line memory module (DIMM). The 32M x 64
memory module uses 16 Mosel-Vitelic 128 Mbit,
16M x 8 SDRAM. The x64 modules are ideal for use
in high performance computer systems where
increased memory density and fast access times
are required.
Features
■ 168 Pin Unbuffered 33,554,432 x 64 bit
Oganization SDRAM Modules
■ Utilizes High Performance 128Mbit, 16M x 8
SDRAM in TSOPII-54 Packages
■ Fully PC Board Layout Compatible to INTEL’S
Rev 1.0 Module Specification
■ Single +3.3V (± 0.3V) Power Supply
■ Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
■ Auto Refresh (CBR) and Self Refresh
■ All Inputs, Outputs are LVTTL Compatible
■ 4096 Refresh Cycles every 64 ms
■ Serial Present Detect (SPD)
■ SDRAM Performance
Component Used
tCK
tAC
Clock Frequency (max.)
Clock Access Time CAS
Latency
-7
Units
CL=3
143
MHz
CL=2
100
MHz
CL=3
5.4
ns
CL=2
6.0
ns
■ Supported Latencies at 133 MHz Operation
CL
tRCD
tRP
tRC
3
3
3
8
CLK
2Description
V436532S04VATG-75 Rev. 1.4 September 2001
PRELIMINARY
1
MOSEL VITELIC
V436532S04VATG-75
Pin Configurations (Front Side/Back Side)
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VSS
I/O1
I/O2
I/O3
I/O4
VCC
I/O5
I/O6
I/O7
I/O8
I/O9
VSS
I/O10
I/O11
I/O12
I/O13
I/O14
VCC
I/O15
I/O16
CBO*
CB1*
VSS
NC
NC
VCC
WE
DQM0
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
DQM1
CS0
DU
VSS
A0
A2
A4
A6
A8
A10(AP)
BA1
VCC
VCC
CLK0
VSS
DU
CS2
DQM2
DQM3
DU
VCC
NC
NC
CB2*
CB3*
VSS
I/O17
I/O18
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
I/O19
I/O20
VCC
I/O21
NC
DU
CKE1
VSS
I/O22
I/O23
I/O24
VSS
I/O25
I/O26
I/O27
I/O28
VCC
I/O29
I/O30
I/O31
I/O32
VSS
CLK2
NC
WP
SDA
SCL
VCC
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
VSS
I/O33
I/O34
I/O35
I/O36
VCC
I/O37
I/O38
I/O39
I/O40
I/O41
VSS
I/O42
I/O43
I/O44
I/O45
I/O46
VCC
I/O47
I/O48
CB4*
CB5*
VSS
NC
NC
VCC
CAS
DQM4
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
DQM5
CS1
RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VCC
CLK1
NC
VSS
CKE0
CS3
DQM6
DQM7
DU
VCC
NC
NC
CB6*
CB7*
VSS
I/O49
I/O50
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
I/O51
I/O52
VCC
I/O53
NC
DU
NC
VSS
I/O54
I/O55
I/O56
VSS
I/O57
I/O58
I/O59
I/O60
VCC
I/O61
I/O62
I/O63
I/O64
VSS
CLK3
NC
SA0
SA1
SA2
VCC
Notes:
*
These pins are not used in this module.
Pin Names
VSS
Ground
Address Inputs
SCL
Clock for Presence Detect
I/O1–I/O64
Data Inputs/Outputs
SDA
RAS
Row Address Strobe
Serial Data OUT for Presence
Detect
CAS
Column Address Strobe
SA0–A2
WE
Read/Write Input
Serial Data IN for Presence
Detect
BA0, BA1
Bank Selects
CB0–CB7
Check Bits (x72 Organization)
CKE0, CKE1
Clock Enable
A0–A11
CS0–CS3
Chip Select
CLK0–CLK3
Clock Input
DQM0–DQM7
Data Mask
VCC
Power (+3.3 Volts)
V436532S04VATG-75 Rev. 1.3 September 2001
2
NC
No Connection
DU
Don’t Use
MOSEL VITELIC
V436532S04VATG-75
Part Number Information
V
4
3
65
32
S
0
4
V
G
T
A
-
75
MOSEL-VITELIC
MANUFACTURED
GOLD
SDRAM
TSOP
3.3V
-75 133 MHz
(PC133 3-3-3)
(PC133 2-2-2)
A VERSION
WIDTH
(x64 using 128 Mbit)
LVTTL
4 BANKS
DEPTH
168 PIN UNBUFFERED
DIMM X 8 COMPONENT
REFRESH
RATE 4K
Block Diagram
CS1
CS0
DQM CS
I/O1–I/O8 D0
DQM0
I/O1–I/O8
DQM CS
I/O1–I/O8 D8
DQM4
I/O33–I/O40
10Ω
DQM CS
I/O1–I/O8 D12
DQM CS
I/O1–I/O8 D5
DQM CS
I/O1–I/O8 D13
CS
DQM
I/O1–I/O8 D6
CS
DQM
I/O1–I/O8 D14
CS
DQM
I/O1–I/O8 D7
CS
DQM
I/O1–I/O8 D15
10Ω
DQM CS
I/O1–I/O8 D1
DQM1
I/O9–I/O16
DQM CS
I/O1–I/O8 D4
DQM CS
I/O1–I/O8 D9
DQM5
I/O41–I/O48
10Ω
10Ω
CS3
CS2
CS
DQM
I/O1–I/O8 D2
DQM2
I/O17–I/O24
CS
DQM
I/O1–I/O8 D10
DQM6
I/O49–I/O56
10Ω
10Ω
CS
DQM3
I/O25–I/O32
DQM
I/O1–I/O8
CS
DQM
I/O1–I/O8 D11
D3
DQM7
I/O57–I/O64
10Ω
10Ω
E2PROM SPD (256 WORD X 8 BIT)
SA0
SA1
SA2
SCL
SA0
SA1
SA2
SCL
A11-A0, BA0, BA1
D0-D15
SDA
VDD
VSS
WP
C0-C31
RAS, CAS, WE
47K
D0-D15
D0-D7
D0-D15
D0-D7
CKE0
VCC
10K
CKE1
CLOCK WIRING
32M X 64
CLK0
CLK1
CLK2
CLK3
V436532S04VATG-75 Rev. 1.3 September 2001
4 SDRAM +3.3pF
4 SDRAM +3.3pF
4 SDRAM +3.3pF
4 SDRAM +3.3pF
3
D9-D15
MOSEL VITELIC
V436532S04VATG-75
Serial Presence Detect Information
written into the E2PROM device during module production using a serial presence detect protocol (I2C
synchronous 2-wire bus)
A serial presence detect storage device - is assembled onto the module. Information about the module configuration, speed, etc. is
E2PROM
SPD-Table for 75 modules:
Hex Value
Byte Number
Function Described
SPD Entry Value
32Mx64
0
Number of SPD bytes
128
80
1
Total bytes in Serial PD
256
08
2
Memory Type
SDRAM
04
3
Number of Row Addresses (without BS bits)
12
0C
4
Number of Column Addresses (for x8 SDRAM)
10
0A
5
Number of DIMM Banks
2
02
6
Module Data Width
64
40
7
Module Data Width (continued)
0
00
8
Module Interface Levels
LVTTL
01
9
SDRAM Cycle Time at CL=3
7.5 ns
75
10
SDRAM Access Time from Clock at CL=3
5.4 ns
54
11
Dimm Config (Error Det/Corr.)
none
00
12
Refresh Rate/Type
Self-Refresh, 15.6µs
80
13
SDRAM width, Primary
x8
08
14
Error Checking SDRAM Data Width
n/a / x8
00
15
Minimum Clock Delay from Back to Back Random
Column Address
tccd = 1 CLK
01
16
Burst Length Supported
1, 2, 4, 8
0F
17
Number of SDRAM Banks
4
04
18
Supported CAS Latencies
CL = 3
04
19
CS Latencies
CS Latency = 0
01
20
WE Latencies
WL = 0
01
21
SDRAM DIMM Module Attributes
Non Buffered/Non Reg.
00
22
SDRAM Device Attributes: General
Vcc tol ± 10%
0E
23
Minimum Clock Cycle Time at CAS Latency = 2
Not Supported
00
24
Maximum Data Access Time from Clock for CL = 2
Not Supported
00
25
Minimum Clock Cycle Time at CL = 1
Not Supported
00
26
Maximum Data Access Time from Clock at CL = 1
Not Supported
00
27
Minimum Row Precharge Time
20 ns
14
28
Minimum Row Active to Row Active Delay tRRD
15 ns
0F
29
Minimum RAS to CAS Delay tRCD
20 ns
14
30
Minimum RAS Pulse Width tRAS
45 ns
2D
V436532S04VATG-75 Rev. 1.3 September 2001
4
MOSEL VITELIC
V436532S04VATG-75
SPD-Table for 75 modules: (Continued)
Hex Value
Byte Number
Function Described
SPD Entry Value
32Mx64
128 MByte
20
31
Module Bank Density (Per Bank)
32
SDRAM Input Setup Time
1.5 ns
15
33
SDRAM Input Hold Time
0.8 ns
08
34
SDRAM Data Input Setup Time
1.5 ns
15
35
SDRAM Data Input Hold Time
0.8 ns
08
62-61
Superset Information (May be used in Future)
62
SPD Revision
63
Checksum for Bytes 0 - 62
64
Manufacturer’s JEDEC ID Code
65-71
72
00
Revision 2
02
1E
Mosel Vitelic
40
Manufacturer’s JEDEC ID Code (cont.)
00
Manufacturing Location
73-90
Module Part Number (ASCII)
91-92
PCB Identification Code
93
Assembly Manufacturing Date (Year)
94
Assembly Manufacturing Date (Week)
V436532S04VATG-75
95-98
Assembly Serial Number
99-125
Reserved
00
126
Intel Specification for Frequency
64
127
Reserved
FD
128+
Unused Storage Location
00
DC Characteristics
TA = 0°C to 70°C; VSS = 0 V; VDD, VDDQ = 3.3V ± 0.3V
Limit Values
Symbol
Parameter
Min.
Max.
Unit
VIH
Input High Voltage
2.0
VCC +0.3
V
V IL
Input Low Voltage
–0.5
0.8
V
V OH
Output High Voltage (IOUT = –2.0 mA)
2.4
—
V
VOL
Output Low Voltage (IOUT = 2.0 mA)
—
0.4
V
II(L)
Input Leakage Current, any input
(0 V < VIN < 3.6 V, all other inputs = 0V)
–40
40
µA
V436532S04VATG-75 Rev. 1.3 September 2001
5
MOSEL VITELIC
V436532S04VATG-75
Limit Values
Symbol
Parameter
IO(L)
Output leakage current
(DQ is disabled, 0V < VOUT < VCC)
Min.
Max.
Unit
–40
40
µA
Capacitance
TA = 0°C to 70°C; VDD = 3.3V ± 0.3V, f = 1 MHz
Limit Values
Symbol
Parameter
Max. 32M x 64
Unit
CI1
Input Capacitance (A0 to A11, RAS, CAS, WE)
80
pF
CI2
Input Capacitance (CS0-CS3)
30
pF
CICL
Input Capacitance (CLK0-CLK3)
22
pF
CI3
Input Capacitance (CKE0, CKE1)
50
pF
CI4
Input Capacitance (DQM0-DQM7)
20
pF
CIO
Input/Output Capacitance (I/O1-I/064)
20
pF
CSC
Input Capacitance (SCL, SA0-2)
8
pF
CSD
Input/Output Capacitance (SA0-SA2)
10
pF
Operating Currents
TA = 0°C to 70°C, VCC = 3.3V ± 0.3V (Recommended operating conditions otherwise noted)
Max.
Symbol
ICC1
ICC2P
Parameter & Test Condition
ICC3P
ICC4
Note
1700
mA
7
1 bank operation
Precharge Standby Current in Power Down Mode
CS =VIH , CKE≤ VIL(max)
tCK = min.
60
mA
7
tCK = Infinity
40
mA
7
400
mA
60
mA
700
mA
64
mA
1700
mA
Precharge Standby Current in Non-Power Down Mode
CS =VIH , CKE≥ VIL(max)
tCK = min.
tCK = Infinity
ICC2NS
ICC3
Unit
Operating Current
tRC = tRCMIN., tRC = tCKMIN.
Active-precharge command cycling,
without Burst Operation
ICC2PS
ICC2N
-75
CKE ≥ VIH(MIN.)
No Operating Current
tCK = min, CS = VIH(min)
bank ; active state ( 4 banks)
CKE ≥ VIL(MAX.)
(Power down mode)
Burst Operating Current
tCK = min
Read/Write command cycling
V436532S04VATG-75 Rev. 1.3 September 2001
6
7,8
MOSEL VITELIC
V436532S04VATG-75
Max.
Symbol
Parameter & Test Condition
-75
Unit
Note
ICC5
Auto Refresh Current
tCK = min
Auto Refresh command cycling
1800
mA
7
ICC6
Self Refresh Current
Self Refresh Mode, CKE=0.2V
32
mA
13
mA
L-version
Notes:
1. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and
tRC. Input signals are changed one time during tCK.
2. These parameter depend on output loading. Specified values are obtained with output open.
V436532S04VATG-75 Rev. 1.3 September 2001
7
MOSEL VITELIC
V436532S04VATG-75
AC Characteristics
TA = 0° to 70°C; VSS = 0V; VCC = 3.3V ± 0.3V, tT = 1 ns
Limit Values
-75
#
Symbol
Parameter
Min.
Max.
Unit
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
7.5
10
–
–
s
ns
ns
Clock Frequency
CAS Latency = 3
CAS Latency = 2
–
–
133
100
MHz
MHz
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
–
_
5.4
6.0
ns
ns
Note
Clock and Clock Enable
1
2
3
tCK
tCK
tAC
2, 4
4
tCH
Clock High Pulse Width
2.5
–
ns
5
tCL
Clock Low Pulse Width
2.5
–
ns
6
tT
Transition Tim
0.3
1.2
ns
Setup and Hold Times
7
tIS
Input Setup Time
1.5
–
ns
5
8
tIH
Input Hold Time
0.8
–
ns
5
9
tCKS
Input Setup Time
1.5
–
ns
5
10
tCKH
CKE Hold Time
0.8
–
ns
5
11
tRSC
Mode Register Set-up Time
15
–
ns
12
tSB
0
7.5
ns
Row to Column Delay Time
15
–
ns
6
Power Down Mode Entry Time
Common Parameters
13
tRCD
14
tRP
Row Precharge Time
15
–
ns
6
15
tRAS
Row Active Time
42
100K
ns
6
16
tRC
Row Cycle Time
60
–
ns
6
17
tRRD
Activate(a) to Activate(b) Command Period
14
–
ns
6
18
tCCD
CAS(a) to CAS(b) Command Period
1
–
CLK
Refresh Period (4096 cycles)
—
64
ms
Self Refresh Exit Time
1
Refresh Cycle
19
tREF
20
tSREX
CLK
Read Cycle
21
tOH
Data Out Hold Time
3
–
ns
22
tLZ
Data Out to Low Impedance Time
1
–
ns
V436532S04VATG-75 Rev. 1.3 September 2001
8
2
MOSEL VITELIC
V436532S04VATG-75
AC Characteristics
TA = 0° to 70°C; VSS = 0V; VCC = 3.3V ± 0.3V, tT = 1 ns (Continued)
Limit Values
-75
#
Symbol
23
tHZ
24
Parameter
Min.
Max.
Unit
Note
Data Out to High Impedance Time
3
7
ns
7
tDQZ
DQM Data Out Disable Latency
–
2
CLK
25
tWR
Write Recovery Time
2
–
CLK
26
tDQW
DQM Write Mask Latency
0
–
CLK
Write Cycle
V436532S04VATG-75 Rev. 1.3 September 2001
9
MOSEL VITELIC
V436532S04VATG-75
Notes:
1. The specified values are valid when addresses are changed no more than once during tCK(min.) and when No
Operation commands are registered on every rising clock edge during tRC(min). Values are shown per module
bank.
2. The specified values are valid when data inputs (DQ’s) are stable during tRC(min.).
3. All AC characteristics are shown for device level.
An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed
by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin.
4. AC timing tests have VIL = 0.4V and V IH = 2.4V with the timing referenced to the 1.4V crossover point. The transition
time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit
shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with
a input signal of 1V / ns edge rate between 0.8V and 2.0V.
+ 1.4 V
tCH
2.4V
CLOCK
50 Ohm
0.4V
tCL
tSETUP
Z=50 Ohm
tT
I/O
tHOLD
50 pF
1.4V
INPUT
tAC
tAC
tLZ
I/O
tOH
50 pF
1.4V
OUTPUT
Measurement conditions for
tac and toh
tHZ
5. If clock rising time is longer than 1 ns, a time (tT/2 -0.5) ns has to be added to this parameter.
6. Rated at 1.5V
7. If tT is longer than 1 ns, a time (tT -1) ns has to be added to this parameter.
8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be
given to “wake-up” the device.
9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command
is registered.
10.
Referenced to the time which the output achieves the open circuit condition, not to output voltage levels.
11.
tDAL is equivalent to tDPL + tRP.
V436532S04VATG-75 Rev. 1.3 September 2001
10
MOSEL VITELIC
V436532S04VATG-75
Package Diagram
L-DIM-168-30
SDRAM DIMM Module Package
All measurements in mm
133.37
127.35
17.80
35.00
(4.0 max)
10
11
40
41
84
3.0
1
42.18
1.27 ± 0.100
63.68
A
94
95
124
125
168
4.0
85
B
D
6.35
2.50
2.0
4.45
Detail B
2.26
RADIUS
1.27 + 0.10
Tolerances: ± (0.13) unless otherwise specified.
V436532S04VATG-75 Rev. 1.3 September 2001
0.2 ± 0.15
2.0
3.175
Detail A
1.0 ± 0.05
1.27
3.125
3.125
6.35
11
Detail C
MOSEL VITELIC
V436532S04VATG-75
Label Information
MOSEL VITELIC
Part Number
Criteria of PC100 or PC133
(refer to MVI datasheet)
V436532S04VATG-75
PC133U-333-542-A
Taiwan XXXX-XXXXXXX
DIMM manufacture date code
Trace Code
PC133 U - 333 - 54 2 - A
UNBUFFERED DIMM
Gerberfile Intel® PC100 x 8 Based
CL = 3 (CLK)
tRCD = 3 (CLK)
tRP = 3 (CLK)
V436532S04VATG-75 Rev. 1.3 September 2001
JEDEC SPD Revision 2
tAC = 5.4 ns
12
MOSEL VITELIC
WORLDWIDE OFFICES
V436532S04VATG-75
U.S.A.
TAIWAN
SINGAPORE
UK & IRELAND
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0952
7F, NO. 102
MIN-CHUAN E. ROAD, SEC. 3
TAIPEI
PHONE: 886-2-2545-1213
FAX: 886-2-2545-1209
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SINGAPORE 079903
PHONE: 65-3231801
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SCIENCE BASED IND. PARK
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PHONE: 886-3-579-5888
FAX: 886-3-566-5888
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BUSINESS CENTRE
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PARK
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PHONE: 44-1698-748515
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FAX: 03-3537-1402
GERMANY
(CONTINENTAL
EUROPE & ISRAEL)
BENZSTRASSE 32
71083 HERRENBERG
GERMANY
PHONE: +49 7032 2796-0
FAX: +49 7032 2796 22
U.S. SALES OFFICES
NORTHWESTERN
SOUTHWESTERN
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0952
302 N. EL CAMINO REAL #200
SAN CLEMENTE, CA 92672
PHONE: 949-361-7873
FAX: 949-361-7807
© Copyright 2001, MOSEL VITELIC Inc.
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC
CENTRAL,
NORTHEASTERN &
SOUTHEASTERN
604 FIELDWOOD CIRCLE
RICHARDSON, TX 75081
PHONE: 214-352-3775
FAX: 214-904-9029
9/001
Printed in U.S.A.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461