CXA1702AR 4-channel REC/PB Amplifier for 8 mm VCR Description The CXA1702AR is a bipolar IC designed as recording/playback amplifiers for Hi8-compatible VCRs. Features Recording/playback system • Hi8-compatible wideband recording/playback amplifier. • Enables electric variable resistor (EVR) control. 64 pin LQFP (Plastic) • • Recording system • Feedback damping provided in the recording amplifier and its EVR control function facilitate printed circuit board design. • Five-input (Y, chroma, AFM, ATF, PCM) mix amplifier and EVR control function for Y/low-band recording level. • Ramp circuit for the recording amplifier output bias current. • Playback system • Feedback dumping provided in the playback amplifier facilitates printed circuit board design. • Middle-frequency tuner on chip; EVR permits independent adjustment of its center frequency fo, Q and boost amount by EVR. • RF AGC and dropout detection circuit. Application 8 mm VCR Structure Bipolar silicon monolithic IC Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VCC 7 V °C °C • Operating temperature Topr –10 to +75 • Storage temperature Tstg –65 to +150 • Allowable power dissipation PD 1010 mW (when mounted on board) Operating Condition Supply voltage VCC +0.5 4.75 –0.25 V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E93Z32-TE CXA1702AR REC1ACNT 34 HEAD 35 RAMP GEN PB1BIN 2B 36 VIDEOSW1 1A GND 1CH 37 MT (-6dB) 2A 39 40 41 PB2AIN REC2AOUT 2B RF AGC 40dB 15dB HEAD HEAD 40dB REC 2A BUFF 15dB RFAGCTC RFAGCOUT REFV T2 YLEV_MTG T1 LOWLEVEL YIN XDECK CIN GND2 AFMIN PCM VPSW2 RAMP GEN VIDEO PCM REC VPSW3 45 VIDEO PCM YGCA REC VPSW4 V/I REC 2B 1 1 RAMP GEN 46 RFAGCIN VPSW1 VIDEO 1 1 LOW GCA 1 VIDEO PCM 1 40dB 15dB HEAD 2 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 GND2B PBDUMP2B VREG VPPCMIN RECPCM VPVTRIN RECVTR GND IR1 IR VG2 PCMIN PCMREC ATFIN AFREC LOW GCA PB2BIN REC2BOUT 47 REC2BCNT DOCDET GND 48 VCC2CH AGCDET VIDEOSW2 V/I REC2ACNT DOP VIDEOSW3 (0dB) REC V/I RP_PB DOCDET 2CH MUTE RAMP GEN 44 GND2A 42 PBDUMP2A 43 PBDUMP1B 12dB 1B REC 1B GND1B MUTE V/I 38 REC1BOUT 1CH 2CH PCMSW2 2A REC REC1BCNT PCMSW3 (6dB) 1B 40dB REC 1A VCC1CH PCMSW1 1A 15dB 16 17 15 MTOUT 18 14 VCC2 19 13 PCMOUT 20 12 MTFØ 21 11 XHRFSWP 22 10 RFSWP 23 9 REC2B 24 8 REC2A 25 7 REC1B 26 6 VCC 27 5 REC1A 28 4 RAMP 29 3 MTQ 30 2 PBDUMP1A 31 1 GND1A 32 33 REC1AOUT PB1AIN Block Diagram and Pin Configuration —2— CXA1702AR Pin Description Pin No. 1 Symbol AFM IN (VCC, VCC2, VCC1CH, VCC2CH=4.75V, Ta=25°C) Pin voltage DC AC — 125mVp-p input Equivalent circuit Description Input pin for recording AFM signal. Input signal bias should be in the range from 1 V to 3.5 V. Connect to Vcc when the pin is not in use. 70µ 20p 1 140 50k 2.45V 2 3 GND2 CIN 0V 2.45V — 500mVp-p input GND pin Input pin for recording chroma signal. 3 140 50k 25µ 2.45V 4 5 XDECK 2.4V — (when pin is open) H: 4.3 V or more L: 0.6 V or less input YIN 2.45V 500mVp-p input DECK and NORM switching pin H : NORM (4ch) L : DECK (2ch) Open : 20µ } 100k 4 20µ 140 100k 2.9V 1.8V Input pin for recording Y signal. 40µ 5 140 50k 2.45V 6 LOW LEVEL 1.8V to 4.75V input — 270 6 21k 140 3.15V 90µ 7 8 T1 — YLEV_MTG 1.8V to 4.75V input 90µ — — — 270 8 140 270 23k 14k 90µ 90µ 3.2V 100µ 100µ 2.8V 1.75V YLEVEL —3— MTG EVR adjusting pin for low-band recording signal (chroma, AFM, video path ATF, PCM path ATF) level. Increasing the input voltage lowers the signal level. Test pin. Set the pin open. EVR adjusting pin for recording Y signal level and middle tune boost amount. Adjusts the former during recording and the latter during playback. Increasing the input voltage lowers recording Y signal level and boost amount. CXA1702AR Pin No. Symbol Pin voltage DC AC — 9 T2 — 10 REFV Hi8:4.45V Nor:3.6V input Equivalent circuit 60k 15k 140 40µ RFAGC OUT 1.9V Test pin. Connect decoupling capacitance between this pin and GND. EVR adjusting pin to decide the adjustment range of middle tune fo. Input the following: Hi8 : 4.45 V Nor: 3.6 V 270 10 11 Description 400mVp-p output 3.25V 40µ Output pin for playback Y signal. 40µ 11 2k 410µ 600µ 12 RFAGCTC 2.5V to 4.75V input (during EVR adjustment) — RFAGC time constant pin. 4700p 140 RFAGCTC 50µ 13 RFAGC IN — 50µ 25µ 25µ 220mVp-p input 13p 13 140 50k 50µ 3.25V 14 DOCDET 2.55V (when pin is open) VCC 12 12 — 26.5k 14 140 4.15V 42.5k —4— 50µ 470k RFAGC gain may be adjusted by EVR. Increasing the input voltage increases gain. Input pin for playback Y signal. Playback Y signal is separated from playback video signal output to Pin 17 (MTOUT), then input to Pin 13 (RFAGCIN). Set input signal bias in the range from 1 V to 3.5 V. Connect to Vcc when this pin is not in use. Pin for deciding dropout detection level. Connect decoupling capacitance between this pin and GND. For adjustment, input voltage proportional to Pin 52 (VREG) output voltage. Increasing the input voltage increases the detection level. CXA1702AR Pin No. 15 Symbol DOP Pin voltage DC H: 3.15V L: 0V output Equivalent circuit AC Description — Output pin for dropout detection signal. Goes High at the time of dropout. 150 15 3.15V 2.4k 1.3m 16 17 RP_PB MTOUT H: 2.3V or more L: 0.6V or less input 2.4V — 35µ 50k 5.4k 16 2.15V 140 220mVp-p (playback Y signal) output Input pin for REC/PB switching signal. H : PB L : REC Output pin for playback video signal. 40µ 17 4k 400µ 18 Vcc2 19 PCMOUT 4.75V 1.95V — 220mVp-p output 330µ Power supply pin. Output pin for playback PCM signal. 25µ 19 3.5k 360µ 20 MTF0 1.8V to 4.75V input 240µ — EVR adjusting pin for middle tune fo. Increasing the input voltage increases fo. 270 20 140 40µ 30k 11k 40µ —5— 2.85V 1.7V CXA1702AR Pin No. Symbol Pin voltage DC Equivalent circuit AC Description 21 XHRFSWP H: 2.3V or more L: 0.6V or less input — 22 — Same as for Pin 21 Input pin for RFSWP signal. — Same as for Pin 21 Goes L during recording and turns on 2Bch recording amplifier output bias current. — Same as for Pin 21 Goes L during recording and turns on 2Ach recording amplifier output bias current. — Same as for Pin 21 Goes L during recording and turns on 1Bch recording amplifier output bias current. 21 140 2.15V 26 RFSWP H: 2.3V or more L: 0.6V or less input REC2B H: 2.3V or more L: 0.6V or less input REC2A H: 2.3V or more L: 0.6V or less input REC1B H: 2.3V or more L: 0.6V or less input VCC 4.75V — 27 REC1A — Same as for Pin 21 28 RAMP — Same as for Pin 21 29 MTQ 23 24 25 H: 2.3V or more L: 0.6V or less input H: 2.3V or more L: 0.6V or less input 1.8V to 4.75V input Input pin for 1/2RFSWP signal. 35µ — Power supply pin for main blocks excluding recording and head amplifiers. Goes L during recording and turns on 1Ach recording amplifier output bias current. Goes H during after-recording and turns on recording amplifier output bias current. — EVR adjusting pin for middle tune Q. Increasing the input voltage increases Q. 270 29 140 40µ 37.5k 12.5k 40µ —6— 2.9V 1.8V CXA1702AR Pin No. Symbol 30 PBDUMP1A Pin voltage DC AC 2.6V — Equivalent circuit 120µ Description Dumping adjusting pin for 1Ach head amplifier. Increasing the external resistance reduces the peaking amount. 270 30 130µ 31 GND1A 0V — 32 PB1AIN 0.7V 200µVp-p input 30 40µ — PBDUMP1A GND pin for 1Ach recording and head amplifiers. Playback signal 1Ach input pin. 1.2m 1.5V 32 33 REC1A OUT (19mA output) (21mAp-p output) Recording signal 1Ach output pin. Open collector. 33 19m 34 REC1A CNT 1.8V to 4.75V input — EVR adjusting pin for 1Ach recording amplifier dumping. Increasing the input voltage increases the peaking amount. 270 34 140 52K 19K 40µ 35 Vcc1CH 4.75V — 36 REC1B CNT — 37 REC1B OUT PB1BIN 1.8V to 4.75V input (19mA output) 0.7V 38 40µ — Same as for Pin 34. (21mAp-p Same as for Pin 33. output) 200µVp-p Same as for Pin 32. input —7— 3.15V Power supply pin for 1Ach and 1Bch recording and head amplifiers. EVR adjusting pin for 1Bch recording amplifier dumping. Recording signal 1Bch output pin. Open collector. Playback signal 1Bch input pin. CXA1702AR Pin No. Symbol Pin voltage Equivalent circuit Description — GND pin for 1Bch recording and head amplifiers. DC AC 0V — 40 PBDUMP1B 2.6V — Same as for Pin 30. Dumping adjusting pin for 1Bch head amplifier. 41 PBDUMP2A 2.6V — Same as for Pin 30. Dumping adjusting pin for 2Ach head amplifier. — 39 GND1B 42 GND2A 0V 43 PB2AIN 0.7V 200µVp-p Same as for Pin 32. input Playback signal 2Ach input pin. 44 REC2AOUT (19mA output) (21mAp-p Same as for Pin 33. output) Recording signal 2Ach output pin. Open collector. 45 REC2ACNT 1.8V to 4.75V input 46 VCC2CH 4.75V 47 REC2BCNT 1.8V to 4.75V input 48 REC2BOUT (19mA output) — — Same as for Pin 34. — Same as for Pin 34. GND pin for 2Ach recording and head amplifiers. EVR adjusting pin for 2Ach recording amplifier dumping. Power supply pin for 2Ach and 2Bch recording and head amplifiers. EVR adjusting pin for 2Bch recording amplifier dumping. (21mAp-p Same as for Pin 33. output) Recording signal 2Bch output pin. Open collector. 200µVp-p Same as for Pin 32. input Playback signal 2Bch input pin. 49 PB2BIN 0.7V 50 GND2B 0V — 2.6V — 51 PBDUMP2B — — Same as for Pin 30. —8— GND pin for 2Bch recording and head amplifiers. Dumping adjusting pin for 2Bch head amplifier. CXA1702AR Pin No. 52 Symbol VREG Pin voltage DC AC 4.15V — Equivalent circuit Description Output pin for 4.15 V regulator. Connect decoupling capacitance between this pin and GND. Up to 0.5 mA current can be led outside IC. 52 53 VPPCMIN 2.45V 200mVp-p (recording PCM signal) input 20µ 53 140 50K 2.45V 54 RECPCM 2.4V 200mVp-p (recording PCM signal) output VPSW input pin for recording PCM path. Input Pin 54 (RECPCM) signal after cutting DC component with external capacitance. 40µ Output pin for recording PCM path. Outputs signal obtained by mixing recording PCM signal and recording ATF signal. 25µ 54 8K 180µ 220µ 55 VPVTRIN 2.45V 200mVp-p Same as for Pin 53. (recording Y signal) input 56 RECVTR 2.4V 200mVp-p (recording Y signal) output 40µ 56 8K 220µ 57 GND 0V — VPSW input pin for recording video path. Input Pin 56 (RECVTR) signal after cutting DC component with external capacitance. Output pin for recording video path. Outputs signal obtained by mixing recording Y signal, recording chroma signal, recording AFM signal and recording ATF signal. 300µ — —9— GND pin for main blocks excluding recording and head amplifiers. CXA1702AR Pin No 58 Symbol IR1 Pin voltage DC AC 1.95V — Equivalent circuit Description Pin for external reference current source. Connect external resistor 15kΩ between this pin and GND. Be careful not to cause cross talk. 130µ (when resistor is connected) 58 1K 58 IR1 58 IR1 59 IR 1.9V 15K 15K — Pin for external reference current source. Connect external resistor 18 kΩ between this pin and GND. Be careful not to cause cross talk. 100µ (when resistor is connected) 59 1K 59 IR 18K 59 60 VG2 2.45V — Pin for internal reference voltage source. Connect decoupling capacitance between this pin and GND. Not for outside IC use. 270 60 4K 600µ 61 PCMIN 2.45V 300mVp-p input Input pin for recording PCM signal. 70µ 61 140 50K 2.45V 62 PCMREC H: 2.3V or more L: 0.4V or less input — 35µ 62 140 2.15V 35K 70K 63 ATFIN 2.45V 64 AFREC H: 2.3V or more L: 0.6V or less input 125mVp-p Same as for Pin 61. input — Same as for Pin 21. —10— PCM recording switching pin. H: PCM recording also, RFAGC gain is held when Pin 16 (RP_PB):H and Pin 62 (PCMREC): H Input pin for recording ATF signal. After-recording mode switching pin. H: after-recording After-recording circuit current 3 —11— Recording AFM path secondary distortion 15 Low-band signal GCA (PCM, ATF path) minimum gain 14 Recording ATF (video path) gain 13 12 Recording AFM path gain 4 VREG pin voltage Recording system 5 Recording Y signal GCA minimum gain Recording Y signal GCA maximum 6 gain Recording Y signal GCA frequency 7 response Recording Y signal GCA secondary 8 distortion Low-band signal GCA (video, chroma 9 path) minimum gain Low-band signal GCA (video, chroma 10 path) maximum gain Recording chroma path secondary 11 distortion IPB Playback circuit current 2 5 3 3 3 DY GLVmin GLVmax DC GLPmin GVATF DAFM 63 63 1 1 5 VFY GAFM 5 5 GYmin GYmax — — — — 300KHz 300KHz 750KHz 500mVP-P 500mVP-P 500mVP-P 125mVP-P 125mVP-P 125mVP-P 100KHz 100KHz 1.7MHz 1.7MHz 7MHz 500mVP-P 125mVP-P A 14MHz, 300KHz 500mVP-P A A A A A A A A A A 300KHz 300KHz 500mVP-P S T J A1 200mVP-P — — — — — — — — 54 56 56 56 56 56 56 56 56 56 56 52 IVCC IVCC IVCC Measurement condition Measurement Input condition Control pin or Input pin Level Frequency logic ammeter name VREG IAFREC IREC Symbol Recording circuit current Item 6 (LOWLEVEL)=1.8 V gain at 6 (LOWLEVEL)=1.8 V gain at 6 (LOWLEVEL)=1.8 V gain at 6 (LOWLEVEL)=1.8 V gain at Pin 6 (LOWLEVEL)=4.75V When Pin maximum When Pin maximum When Pin maximum When Pin maximum Pin 6 (LOWLEVEL)=1.8V Pin 6 (LOWLEVEL)=4.75V 14 MHz level/300 kHz level Pin 8 (YLEV_MTG)=1.8V Pin 8 (YLEV_MTG)=4.75V Current consumption inside IC during recording (including recording amplifier output bias current) Current consumption inside IC during playback Current consumption inside IC during after-recording (including recording amplifier output bias current) Pin voltage measurement Measurement method — -14.5 — -14.5 — -14.5 — — -1.5 -4.0 — 3.95 68 44 45 Min. -31.8 -12.3 -55 -12.3 -50 -12.4 -31.9 -55 -0.5 -1.7 -16.3 4.15 96 63 64 Typ. -26.5 — — — — — -26.5 — 0.5 — -14.0 4.35 125 82 83 Max. Ratings dB dB dB dB dB dB dB dB dB dB dB V mA mA mA Unit (VCC, VCC2, VCC1CH, VCC2CH = 4.75 V, Ta = 25 °C, See the Electrical Characteristics Measurement Circuit and the Control Logic Truth Table. ∗Start taking measurement after making adjustment described in Notes on Measurement.) 1 NO Electrical Characteristics CXA1702AR Item Recording amplifier output bias current —12— 24 Ramp falling edge inclination Ramp rising edge 23 inclination 1 Recording amplifier 22 frequency response Recording amplifier 21 output current 20 16 IR1B 1B Toff Ton1 IR2B IR2A 2A VFR1A VFR2A VFR1B VFR2B IR1A 1A 1A 2A 1B 2B 1A 2A 1B 2B 1A 2A 1B 2B IB2B 2B 2B IB1B 1B See Measurement method. 27 24 25 23 27 24 25 23 10MHz 1MHz 1MHz — 200mVp-p 200mVp-p — 7MHz 300KHz 14MHz, 300KHz 100KHz 55 55 — 300mVp-p 61 DP IB2A 300mVp-p 61 VFP 2A 300mVp-p 61 GP IB1A 125mVp-p 63 A A1 A2 A3 A4 A4 A3 A2 A1 A4 A3 A2 A1 A A A A 33 44 37 48 33 44 37 48 33 44 37 48 37 48 44 33 IB2B IB1B IB2A IB1A 54 54 54 54 Measurement condition Measurement Input condition Control pin or Input pin Level Frequency logic ammeter name GLPmax Symbol 1A Low-band signal GCA (PCM, ATF path) maximum gain 17 Recording PCM path gain Recording PCM path frequency 18 response Recording PCM path secondary 19 distortion NO Inclination: Ton1 Output Input 2500µsec L H Inclination: Toff 10 MHz level/1 MHz level DC current measurement 34 pin (REC1ACNT), 45 pin (REC2ACNT), 36 pin (REC1BCNT), 47 pin (REC2BCNT)=3.55V 34 pin (REC1ACNT), 45 pin (REC2ACNT), 36 pin (REC1BCNT), 47 pin (REC2BCNT)=3.55V Output level (Vp-p)/51(Ω) 14 MHz level/300 kHz level Pin 6 (LOWLEVEL)=1.8V Measurement method — — — 18.1 14.55 — -0.7 -4.5 -14.5 Min. 32 32 -0.5 20.7 18.8 -55 0.1 -3.7 -12.6 Typ. — — — 23.3 23.05 — 0.9 -2.9 — Max. Ratings µA/µs µA/µs dB mAp-p mA dB dB dB dB Unit CXA1702AR Playback system Ramp rising edge inclination 2 Item Head amplifier PCMOUT gain —13— GAGCmax 32 RFAGC maximum gain GV1A GV2A GV1B GV2B GP1A GP2A GP1B GP2B VAGC1 VAGC2 VAGC3 GAGCmin 1A 2A 1B 2B 1A 2A 1B 2B 2B 1B 13 13 32 43 38 49 32 43 38 49 13 13 13 50mVp-p 1.2Vp-p 224mVp-p 56mVp-p 896mVp-p 200µVp-p 200µVp-p 7MHz 7MHz 7MHz 7MHz 7MHz 300KHz 300KHz See Measurement method. J J J K L M M J K L J J J U T S 28 2A Ton2 R 11 11 11 11 11 19 17 48 37 44 33 Measurement condition Measurement Input condition Control pin or Input pin Level Frequency logic ammeter name 1A Symbol 31 RFAGC minimum gain 28 RFAGC standard output 29 RFAGC cover range High 30 RFAGC cover range Low 27 Head amplifier MTOUT 26 gain 25 NO 2500µsec H L Measure output level, applying time constant to Pin 12 (RFAGCTC). Pin 10 (REFV)=4.45V Pin 12 (RFAGCTC)=2.7V, Pin 10 (REFV)=4.45V Pin 12 (RFAGCTC)=4.75V, Pin 10 (REFV)=4.45V Pin 8 (YLEV_MTG)=4.75V Inclination: Ton2 Output Input Measurement method — — 325 300 — 57.7 58.0 — Min. 20.1 -7.7 395 365 405 61.2 61.5 17 Typ. — — 465 — 475 64.7 65.0 — Max. Ratings dB dB mVp-p mVp-p mVp-p dB dB µA/µs Unit CXA1702AR KDO-OFF VDOP-L VDOP-H TDOP-ON TDOP-OFF 34 Dropout detection OFF level 35 Dropout pulse Low level 36 Dropout pulse High level 37 Dropout ON detection time 38 Dropout OFF detection time Symbol KDO-ON Item 33 Dropout detection ON level NO 13 13 See Measurement method. See Measurement method. J J 15 15 Measurement condition Measurement Input condition Control pin or Input pin Level Frequency logic ammeter name 224mVp-p VDOP-H ab VDOP-L KDO-ON=20log(a/224) KDO-OFF=20log(b/224) 7MHz TDOP-ON Output Input TDOP-OFF 50µsec 5KHz 7MHz/224mVp-p Apply time constant to Pin 12 (RFAGCTC). Output Input 10KHz Apply time constant to Pin 12 (RFAGCTC). Measurement method — — 2.9 0 -9.5 -15.5 Min. 2.0 1.1 3.15 0.01 -6.5 -12.5 Typ. — — 3.4 0.2 -3.5 -9.5 Max. Ratings µs µs V V dB dB Unit CXA1702AR —14— CXA1702AR Name of control logic condition Input condition and operation 16 RP_PB 27 REC1A 54 RECPCM VPSW1 VPSW2 VPSW3 VPSW4 33 REC1AOUT 37 REC1BOUT 44 REC2AOUT 48 REC2BOUT PBAmp1B PBAmp2A PBAmp2B 19 PCMOUT 17 MTOUT 11 RFAGCOUT DOCDET Control Logic Truth Table A L H H H H — — — — L — V P V V V V S S S S × × × × × × × × A1 A2 A3 A4 L L L L L H H H — — — H H L H — — — H L H H — — — H H H L — — — V V V V P P P P V V V V V V V V V V V V V V V V V S S S S S V S S V S S S S S V × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × B C D E L L L L L H H H — L H — H H V H H L H — H L — H H V H L H H — L L — H H V H H H L — H H — H H V P P P P P V V V V V P V V P V V V V V P P S S S S S P S S P S S S S S P × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × F G H I L L L L L H H H — H L H H — H H L H — H H H L — H H — H O,L V H L — H O,L V L L — H O,L V L H — H O,L V P P P P P V V V V P V V V V P V V V V P P S S S S P S S S S P S S S S P × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × J K L M H H H H — — — — — — — — — — — — — — — — — — — — H L L L H H L H L L L L L L L L H H H H × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × O O O O O O O O O O O O O O O O 2A 1B 2B 1A 1A 2A 1B 2B O O O O O O O O PB 1A 2A 1B 2B N O P Q H H H H — — — — — — — — — — — — — — — — — — — — H L H H L H L L L L L L L L L L O,L O,L O,L O,L × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × O O O O O O O O O O O O O O O O 1B 1A 2B 2A 1A 1B 2A 2B O O O O O O O O DECK PB 1A 1B 2A 2B R S T U H H H H — — — — — — — — — — — — — — — — H L H H H L H L L H H H H H H H H H H H H H H H × × × × P P P P P V V V V V P V V P V V V V V P P S S S S S P S S P S S S S S P × O O O O O O Mu Mu O × O Mu Mu × O O Mu Mu O O × Mu Mu O O O O O O O O PCM afterrecording 1A 2A 1B 2B V W X Y H H H H — — — — — — — — — — — — — — — — H H H H H L H L L H L H H H H H H H H H O,L O,L O,L O,L × × × × P P P P P V V V V P V V V V P V V V V P P S S S S P S S S S P S S S S P × O O O O O O Mu Mu × O O Mu Mu O × O Mu Mu O O × Mu Mu O O O O O O O O Control logic input condition Operation of each section under respective input condition — — — — L L L L Playback PBAmp1A 4 XDECK — — — — 56 RECVTR 62 PCMREC 64 AFREC 21 XHRFSWP 22 RFSWP 28 RAMP 23 REC2B 24 REC2A 25 REC1B Recording Operation Mode Video REC (power save) Video REC 1A 2A 1B 2B PCM REC DECK PCM REC 1A 2A 1B 2B REC 1A 1B 2A 2B PB DECK PCM afterrecording PCM after1A recording 1B 2A 2B During DECK PCM after-recording 4 XDECK=O…… Inclination of the rising edge of the recording amplifier output bias current 32µA/µs (typ.) 4 XDECK=L…… Inclination of the rising edge of the recording amplifier output bias current 17µA/µs (typ.) 1. Description of input conditions H … Control logic input voltage 2.3 V or more L … Control logic input voltage 0.6 V or less —… Independent of H and L Only for 4 XDECK H … Control logic input voltage 4.3 V or more (Vcc = 4.75 V) L … Control logic input voltage 0.6 V or less (Vcc = 4.75 V) O … Open Only for 62 PCMREC H … Control logic input voltage 2.3 V or more L … Control logic input voltage 0.4 V or less 2. Description of operation mode O …Operating S… Recording amplifier standby. × …Not operating Output bias current is not V …Video signal is output. flowing. P …PCM signal is output. 1A …1Ach playback signal is output. 1B…1Bch playback signal is output. 2A …2Ach playback signal is output. 2B…2Bch playback signal is output. Mu…Playback signal is muted during PCM after-recording and, at the same time, RFAGC gain is held. —15— CXA1702AR Rising/Falling Edge Inclination of Recording Amplifier Output Bias Current (typ.) (See the Control Logic Truth Table.) Mode Operation Pin 4 (XDECK) Rising-edge inclination Falling-edge inclination REC — — 32µA/µs 32µA/µs PCM after-recording PCM after-recording DECK PCM after-recording H O L 17µA/µs 32µA/µs 17µA/µs 32µA/µs 32µA/µs 32µA/µs Notes on Measurement Start taking measurement after making the following adjustment: Adjust the voltage input to Pin 8 (YLEV_MTG) so that the output level of Pin 56 (RECVTR) reaches 200 mVp-p under the same control logic condition (A) and input condition as those of measurement No. 5. The voltage adjusted here is called Vylev. The voltage input to Pin 8 (YLEV_MTG) is changed in measurement No. 5, 6, and 26. In the other measurement items, set the voltage back to Pin 8 (YLEV_MTG) = Vylev. —16— PB1BIN REC1BOUT REC1BCNT PB2AIN REC2ACNT 100µ 0.1µ 10µ IB2B A REC2BOUT REC2BCNT 49 49 IB1B A 100µ 0.1µ 10µ IB1A A IB2A A REC2AOUT 4.75V GND IVCC A REC1ACNT REC1AOUT GND GND GND GND 51 REC1AOUT ∗ 5.6µ REC1BOUT 51 ∗ REC1BCNT Vcc1CH REC1ACNT 0.01µ PB1BIN GND1B GND2A 0.01µ PB2AIN 51 REC2AOUT ∗ 5.6µ 0.022µ 390 PBDUMP2A 0.022µ 390 PBDUMP1B 1 1 33 34 35 36 37 38 39 40 41 42 43 44 REC2ACNT 45 51 REC2BOUT ∗ REC2BCNT VCC2CH 46 47 48 PB1AIN 40dB REC REC 1 50 40dB HEAD REC 2B REC REC REC 2A HEAD 40dB 40dB HEAD REC 1B 49 31 HEAD REC 1A 32 GND 30 51 15dB V/I RAMP GEN V/I RAMP GEN 15dB 15dB V/I RAMP GEN V/I RAMP GEN 15dB PBDUMP2B 49 49 390 GND1A GND2B 0.022µ 390 PBDUMP1A 0.022µ MTQ 52 29 GND 28 RAMP 27 53 GND VPSW4 54 25 55 REC2A 24 PCM VIDEO PCM VIDEO PCM VIDEO PCM GND 56 VIDEO GND 57 VIDEOSW3 (0dB) MUTE 1CH 2CH GND MUTE 2CH GND VPSW3 VPSW2 26 REC1B PCMSW3 (6dB) 1CH VPSW1 2B VIDEOSW2 2A 1B VIDEOSW1 1A 2B PCMSW2 2A 1B PCMSW1 1A 0.01µ 0.1µ MTQ VREG 10µ RAMP VPPCMIN 10µ 0.01µ 1 VPVTRIN 0.01µ VPPCMIN 51 0.1µ VCC VPVTRIN REC1A RECPCM 10µ 51 REC1A RECPCM REC1B RECVTR RECVTR 58 YGCA MT (-6dB) 23 IR1 GND RFSWP 59 1 1 2 1 RF AGC 22 GND 60 LOW GCA LOW GCA AGCDET 21 GND 61 1 1 12dB 20 1 GND MTF0 GND ∗ REC2A GND REC2B REC2B 15k GND 62 18 63 BUFF DOCDET 19 GND 10µ GND ∗ 0.01µ 5.6µ PB1AIN 5.6µ 0.01µ PB2BIN PB2BIN 10µ RFSWP IR 18k XHRFSWP XHRFSWP VG2 0.01µ 0.01µ PCMIN 51 GND 0.1µ PCMOUT PCMPEC MTF0 PCMIN PCMOUT PCMPEC VCC2 ATFIN GND 64 17 MTOUT AFREC 0.1µ 10µ 0.01µ ATFIN 51 0.01µ AFMIN GND2 CIN 0.01µ XDECK YIN LOWLEVEL T1 YLEV_MTG T2 REFV RFAGCOUT 0.1µ RFAGCTC 0.01µ 51 51 0.01µ 0.01µ 51 10µ RFAGCIN AFMIN CIN XDECK YIN LOWLEVEL YLEV_MTG REFV RFAGCOUT 4700P 470K 51 0.1µ RP_PB 0.01µ DOP GND RFAGCTC 0.01µ RFAGCIN DOCDET DOP RP_PB 0.01µ 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GND GND GND GND GND GND GND GND MTOUT AFREC GND —17— GND Electrical Characteristics Measurement Circuit ∗→Resistance accuracy 1% input pin. a value obtained at the signal The input level is specified by • Other inputs: a value attenuated to 1/50. The input level is specified by PB2BIN): (PB1AIN, PB1BIN, PB2AIN, • Head amplifier input (signal source impedance 50Ω) →Signal input pin (measurement point) →Signal output pin →EVR adjusting pin →Control logic pin CXA1702AR GND 1ACH HEAD 1BCH HEAD 2ACH HEAD 2BCH HEAD 10µ 100µ 0.1µ 10µ 100µ 0.1µ 0.01µ 0.01µ 0.01µ 0.01µ 49 40dB 50 HEAD REC 2B REC REC REC 2A HEAD 40dB 40dB HEAD REC 1B REC REC REC 1A 40dB HEAD 51 15dB V/I RAMP GEN V/I RAMP GEN 15dB 15dB V/I RAMP GEN V/I RAMP GEN 15dB 52 28 27 1B 53 0.01µ 10µ 54 VPSW4 55 PCM VIDEO PCM VPSW3 VIDEO PCM VIDEO PCM 0.01µ 56 VIDEO GND VPSW2 25 24 57 VIDEOSW3 (0dB) 1CH 2CH MUTE GND VPSW1 2B VIDEOSW2 2A 1B VIDEOSW1 1A 2B PCMSW2 2A 10µ PCMSW3 (6dB) 1CH 2CH MUTE 26 58 YGCA MT (-6dB) 23 1 1 59 2 1 RF AGC 22 60 LOW GCA LOW GCA AGCDET 21 61 1 1 12dB 20 1 62 10µ 18 63 BUFF DOCDET 19 64 17 RFAGCIN DOCDET DOP RP_PB RFAGCTC 0.01µ 0.01µ 0.01µ AFMIN GND2 CIN 0.01µ XDECK YIN 0.01µ LOWLEVEL 0.01µ T1 YLEV_MTG T2 REFV RFAGCOUT 4700P 470k 0.1µ Y Y/C SEP 10µ C 0.1µ 10µ Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party and other right due to same. REC2BOUT REC2BCNT VCC2CH REC2ACNT REC2AOUT 0.01µ PB2AIN GND2A 0.022µ 390 PBDUMP2A PBDUMP1B 0.022µ 390 GND1B 0.01µ PB1BIN REC1BOUT REC1BCNT Vcc1CH REC1ACNT REC1AOUT 33 34 35 36 37 38 39 40 41 42 43 44 45 46 0.01µ PB1AIN 0.01µ PB2BIN 47 48 GND1A GND2B 0.01µ VREG 390 0.022µ PBDUMP1A 0.022µ 390 PBDUMP2B MTQ 10µ RAMP VPPCMIN 0.1µ VCC VPVTRIN PCMSW1 1A 0.1µ REC1A RECPCM REC1B RECVTR 29 ∗ REC2A GND REC2B IR1 15k 30 ∗ 31 VG2 RFSWP IR 18k XHRFSWP 10µ 0.01µ MTF0 PCMIN 0.01µ 32 0.1µ PCMOUT PCMPEC 0.1µ VCC2 0.01µ ATFIN MTOUT AFREC 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 —18— 1 Application Circuit SIGNAL OUT SIGNAL IN ∗→Resistance accuracy 1% REC PCM REC ATF REC AFM REC C RF REC Y RF REC DUMP 2B REC DUMP 2A REC DUMP 1B REC DUMP 1A LOWLEVEL EVR CONTROL YLEVEL/MTG MTF0 MTQ REF V DOP PB C RF PB Y RF PB RF PB PCM XDECK AFREC PCMREC RAMP RP PB 1/2RF SWP CONTROL LOGIC RF SWP REC 2B REC 2A REC 1B REC 1A RP GND RP VCC CXA1702AR CXA1702AR Description of Operation <Mix amplifier + recording level adjustment> Y, chroma, AFM, ATF and PCM signals are input at specified levels so that they are mixed internally to achieve an appropriate current value at the head. The video path signal (Y + chroma + AFM + ATF) is output to Pin 56 (RECVTR) and the PCM path signal (PCM + ATF) to Pin 54 (RECPCM). The Y level is EVRadjusted at Pin 8 (YLEV_MTG) and the low band (chroma, AFM, ATF) level at Pin 6 (LOWLEVEL). The lowband levels of the video path and the PCM path are interlocked in adjustment. <SW + recording amplifier> The video path signal and the PCM path signal, which underwent recording level adjustment, are switched at a correct timing, then converted to a current to drive the head. A feedback dumping circuit is incorporated to inhibit head resonance, and the peaking amount can be adjusted by EVR at Pin 34 (REC1ACNT), Pin 36 (REC1BCNT), Pin 45 (REC2ACNT) and Pin 47 (REC2BCNT). During recording, the output capacitance is about 12 pF including that of the head amplifier. <Head amplifier> The playback signal from the head is amplified with low noise and high gain. A feedback dumping circuit is incorporated to inhibit head resonance, and the peaking amount can be adjusted by external resistors connected to Pin 30 (PBDUMP1A), Pin 40 (PBDUMP1B), Pin 41 (PBDUMP2A) and Pin 51 (PBDUMP2B). During playback, the input capacitance is about 20 pF including that of the recording amplifier. —19— CXA1702AR Gain <SW + middle tune> This section switches the playback signals of 1A, 1B, 2A and 2B channels at the correct timing and outputs 3dB Boost amount =6dB the playback video signal to Pin 17 (MTOUT) and the playback PCM signal to Pin 19 (PCMOUT). In the PCM after-recording mode, both playback video signal and f2 playback PCM signal are muted during the PCM f1 recording period. Center frequency f0=8MHz Q=f0/(f2-f1)=2.5 The middle tune circuit corrects the frequency response of the playback video signal. Frequency The center frequency can be adjusted by EVR at Pin 20 (MTF0), Q at Pin 26 (MTQ) and the boost amount at Pin 8 (YLEV_MTG). The figure to the right shows the center condition that sets fo = 8 MHz, Q = 2.5 and the boost amount = 6 dB. Each control characteristic shown in "Example of Representative Characteristics" is obtained when two of their amount are fixed to the center condition. <RFAGC> This circuit inputs the playback Y signal separated from the playback video signal using an external circuit and outputs it at a constant level of 395 mVp-p. In the PCM after-recording mode, RFAGC gain is kept unchanged during PCM recording period. <Dropout detection> A dropout is detected in the playback Y signal, and a dropout pulse is output. The detection level is optimized using 224 mVp-p input as a reference. If necessary, the detection level can be adjusted by inputting a DC voltage to Pin 14 (DOCDET). To make this adjustment, input a voltage proportional to the output voltage of Pin 52 (VREG). <Control logic block> This IC exercises power-saving control of circuit blocks which are not in immediate need for operation. The IC also incorporates a logic circuit for controlling a number of SWs which change inputs and outputs at complicated timing. The combinations of input and output in the basic operation are shown in the Control Logic Truth Table. <Reference voltage in the IC> VG2 2.45 V and VREG 4.15 V are generated as a reference voltages used in the IC. VG2 cannot be used outside the IC. VREG cannot also be used outside the IC except for adjusting the dropout detection level at Pin 14 (DOCDET). —20— CXA1702AR Notes on Operation 1. This IC is characterized by high-voltage gain (about 61 dB in the playback system). Be careful of the following when using the IC: 1) Use reinforced power supply and ground lines. Decouple the power supply pin with a coil and a capacitor. Connect the decoupling capacitor as close to the pin as possible. 2) Use of a regulator power supply is recommended. 3) Connecting a capacitive load to the output may cause oscillation. 4) Take particular care not to make capacitive coupling between the head amplifier input and the playback output. Also be careful not to make capacitive coupling between the recording input and the recording amplifier output. 5) Use of decoupling capacitors is recommended between the following DC voltage input pins and GND. When the control voltage source is at high impedance, aggravation of cross talk or oscillation is feared to occur. Pin 6 (LOWLEVEL), Pin 8 (YLEV_MTG), Pin 10 (REFV), Pin 12 (RFAGCTC) [not when time constant is connected], Pin 14 (DOCDET), Pin 20 (MTF0), Pin 29 (MTQ), Pin 34 (REC1ACNT), Pin 36 (REC1BCNT), Pin 45 (REC2ACT), Pin 47 (REC2BCNT) 6) When a decoupling capacitor is necessary for other pins (not power supply pin), it is recommended to connect each decoupling capacitor as close to the pin as possible. 2. The voltage input to the EVR adjusting pin should be proportional to the supply voltage Vcc. Control the input voltage in the range from 1.8 V to 4.75 V when Vcc = 4.75 V. For EVR adjustment at Pin 12 (RFAGCTC), control the input voltage in the range from 2.5 V to 4.75 V. 3. During normal playback, Pin 16 (RP_PB) is set H, and Pin 64 (AFREC) is set L. At this time, be careful that taking the signal H at Pin 62 (PCMREC) holds RFAGC gain. —21— CXA1702AR Low-band signal GCA (video, chroma path) gain control Y signal GCA gain control –10 –5 –10 –15 –20 2 3 4 5 Pin 8 (YLEV_MTG) voltage (V) (VCC = 4.75V) Pin 3 (CIN) input→Pin 56 (RECVTR) output gain (dB) Pin 5 (YIN) input→Pin 56 (RECVTR) output gain (dB) 0 –15 –20 –25 –30 2 Low-band signal GCA (PCM, ATF path) gain control Pin 63 (ATFIN) input→Pin 54 (RECPCM) output gain (dB) –10 –15 –20 –25 –30 2 3 Pin 6 (LOWLEVEL) voltage (V) 4 5 (VCC = 4.75V) —22— 3 4 5 Pin 6 (LOWLEVEL) voltage (V) (VCC = 4.75V, Pin 8 YLEV_ MTG = Vylev) CXA1702AR Middle tune Q control Middle tune f0 control 7 20 6 5 4 Q f0 -Center frequency (MHz) 15 Pin 10 (REFV) voltage=4.45V 3 3.60V 2 10 1 0 2 5 3 4 Pin 29 (MTQ) voltage (V) 5 (VCC = 4.75V) 0 2 3 4 5 Pin 20 (MTF0) voltage (V) (VCC = 4.75V) Middle tune boost amount control 20 Boost amount (dB) 15 10 5 0 2 3 Pin 8 (YLEV_MTG) voltage (V) 4 5 (VCC = 4.75V) —23— CXA1702AR Package Outline Unit : mm 64PIN LQFP (PLASTIC) 12.0 ± 0.2 ∗ 10.0 ± 0.1 48 33 32 64 17 (0.22) 0.5 ± 0.2 (11.0) 49 A 1 0.5 ± 0.08 + 0.08 0.18 – 0.03 16 + 0.2 1.5 – 0.1 + 0.05 0.127 – 0.02 0.1 0° to 10° 0.5 ± 0.2 0.1 ± 0.1 NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY / PHENOL RESIN SONY CODE LQFP-64P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE ∗QFP064-P-1010-A LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 0.3g JEDEC CODE —24—