CXA2032Q 2-channel REC/PB Amplifier for 8 mm VTR Description The CXA2032Q is a bipolar IC designed as recording/playback amplifiers for 8 mm VTRs. Features Recording system • Supports EVR control for recording Y/low-band recording level • Feedback damping circuit provided in the recording amplifier Playback system • Feedback damping circuit provided in the playback amplifier facilitates printed circuit board design • RFAGC and dropout detection circuit Applications 8 mm VTR 32 pin QFP (Plastic) Absolute Maximum Ratings (Ta=25 °C) • Supply voltage VCC 7 V • Operating temperature Topr –10 to +75 °C • Storage temperature Tstg –65 to +150 °C • Allowable power dissipation PD 450 mW Operating Condition Supply voltage VCC 4.5 to 5.25 V Structure Bipolar silicon monolithic IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E95840-TE Block Diagram and Pin Configuration 17 18 19 20 21 22 23 24 GND1 PBDUMP1 PBDUMP2 GND2 PB2IN REC2OUT VCC1 16 40dB —2— REC 1 1 CGCA YGCA CXA2032Q RFAGC DOCDET LOGIC BUFF RFAGCTC RFAGCOUT DOCDET DOP BOTH REC RFSWP RP PB YLEVEL 8 7 6 5 4 3 2 1 REC2CH 15dB 6dB VCC 12 2ND 2CH PBRFOUT 11 HEAD 15dB REC1IN 14 2ND VOUT1 13 RFSW 1CH AGCDET 9 40dB HEAD REC VREG 10 PB1IN RECDUMP1 15 REC1CH RFAGCIN REC1OUT CXA2032Q 32 YIN 31 CLEVEL 30 CIN 29 GND 28 VOUT2 27 REC2IN 26 RECDUMP2 25 VCC2 CXA2032Q Pin Description Pin No. 1 Symbol YLEVEL (VCC, VCC1ch, VCC2ch=4.75 V Ta=25 °C) Pin voltage DC AC 0V to 4.75 V input Equivalent circuit Description — 1 79.5k 140 37µ EVR adjusting pin for Y signal level during recording. The control voltage is from 0 V to 4.75 V. Increasing the input voltage increases the Y signal level. 10µ 2 RP PB H: 2.3 V or more L: 0.6 V or less input 2 — Input pin for REC/PB mode switching signal. 80k 140 H: PB L: REC 1.4V 10µ 3 RFSWP H: 2.3 V or more L: 0.6 V or less input 3 — 80k 140 Input pin for RFSWP signal. 1.4V 10µ 4 BOTH REC H: 2.3 V or more L: 0.6 V or less input 4 — Alternate recording/both channel recording switching pin. 80k 140 H: Both channel recording L: Alternate recording 1.4V —3— CXA2032Q Pin No. Symbol Pin voltage DC AC Equivalent circuit Description 150 5 DOP H: 3.15 V L: 0.0 V output — Output pin for dropout detection signal. Goes High during dropout. 5 2.4k 3.1V 6 Pin for deciding dropout detection level. Connect decoupling capacitance between this pin and GND. For adjustment, input voltage proportional to Pin 10 (VREG) output voltage. Increasing the input voltage increases the detection level. 7 Output pin for playback Y signal. 4.15V 26.3k 6 DOCDET 2.6 V (when pin is open) — 140 43.4k 50µ 40µ 7 RFAGCOUT 2.8 V 100 400mVp-p output 600µ 410µ RFAGC time constant pin. 8 2.5 V to 4.75 V RFAGCTC input (during EVR adjustment) VCC 470k 8 8 140 — 25µ 25µ —4— 50µ 50µ 4700P RFAGC gain can be adjusted by EVR. Increasing the input voltage increases the gain. CXA2032Q Pin No. 9 Symbol RFAGCIN Pin voltage DC AC — Equivalent circuit Description Input pin for playback Y signal. Playback Y signal is separated from playback video signal output to Pin 11 (PBRFOUT), then input to Pin 9 (RFAGCIN). 9 220mVp-p input 13P 140 50k 50µ 3.25V Output pin for 4.15 V regulator. Connect decoupling capacitance between this pin and GND. 10 10 VREG 4.15 V — 35µ 11 PBRFOUT 2.0 V 100 220mVp-p (playback Y signal output) 11 Output pin for playback video signal. 360µ 290µ 12 VCC 4.75 V Power supply pin for main blocks excluding recording and head amplifiers. — —5— CXA2032Q Pin No. Symbol Pin voltage DC AC Equivalent circuit Description 100 13 VOUT1 3.4 V 184mVp-p (recording Y signal output) 13 150µ 400µ 300µ 14 REC1IN 0.7 V 120 µAp-p input 100 14 100 Recording video signal 1ch output pin. The signal obtained by mixing the recording Y, recording C, recording AFM and recording ATF signals is output. Recording video signal 1ch REC AMP input pin. Pin 13 (VOUT1) output is V/I converted by external resistor, then input to Pin 14 (REC1IN). 300µ 4.15V 7.5k 7.5k 15 RECDUMP1 1.4 V — 15 7.5k 16 VCC1 4.75 V Damping adjusting pin for 1ch recording amplifier. Damping is adjusted by attaching damping resistor between Pin 15 and GND. Decreasing the resistance value increases the damping. Power supply pin for 1ch recording and head amplifiers. — —6— CXA2032Q Pin No. Symbol Pin voltage DC AC Equivalent circuit Description 17 17 REC1OUT 16.5 mA output Recording signal 1ch output pin. This pin is an open collector. 19 mAp-p output 100µ 16.5m 18 PB1IN 0.7 V 200 µVp-p input Playback signal 1ch input pin. 18 1.5V 1.2m 19 GND1 0V GND pin for 1ch recording and head amplifiers. — 270 120µ 20 20 PBDUMP1 2.6 V Damping adjusting pin for 1ch head amplifier. — 40µ 130µ —7— CXA2032Q Pin No. Symbol Pin voltage DC AC Description Equivalent circuit 270 120µ 21 21 PBDUMP2 2.6 V Damping adjusting pin for 2ch head amplifier. — 40µ 130µ 22 GND2 0V — 23 PB2IN 0.7 V 200 µVp-p input GND pin for 2ch recording and head amplifiers. 23 Playback signal 2ch input pin. 1.5V 1.2m 24 24 REC2OUT 16.5 mA output 19 mAp-p output 100µ 16.5m —8— Recording signal 2ch output pin. This pin is an open collector. CXA2032Q Pin No. Symbol 25 VCC2 Pin voltage DC AC 4.75 V Description Equivalent circuit — Power supply pin for 2ch recording and head amplifiers. — Damping adjusting pin for 2ch recording amplifier. Damping is adjusted by attaching damping resistor between Pin 26 and GND. Decreasing the resistance value increases the damping. 4.15V 7.5k 7.5k 26 RECDUMP2 1.4 V 26 7.5k 300µ 27 REC2IN 0.7 V 120 µAp-p input Recording video signal 2ch REC AMP input pin. Pin 28 (VOUT2) output is V/I converted by external resistor, then input to Pin 27 (REC2IN). 100 27 100 300µ 100 28 VOUT2 3.4 V 184mVp-p (recording Y signal output) 28 150µ 400µ —9— Recording video signal 2ch output pin. The signal obtained by mixing the recording Y, recording C, recording AFM and recording ATF signals is output. CXA2032Q Pin No. Symbol 29 GND 30 CIN Pin voltage DC AC 0V 3.45 V Equivalent circuit Description — GND pin for main blocks excluding recording and head amplifiers. 136mVp-p (recording C signal input) Input pin for recording C, recording AFM and recording ATF signals. These three signals are mixed by external resistor, then input to Pin 30 (CIN). 140 30 50k 50k 3.45V 25µ 31 CLEVEL 0.0 V to 4.75 V input 25µ — 31 79.5k 140 37µ 32 YIN 3.05 V 140 500mVp-p 32 50k 50k 100µ —10— 3.05V EVR adjusting pin for lowband recording signal (C, AFM, ATF) level. The control voltage is from 0 V to 4.75 V. Increasing the input voltage increases the lowband recording signal level. Input pin for recording Y signal. —11— VREG pin voltage VFC DC Recording C signal GCA secondary distortion (maximum gain) 11 G CMAX G CMIN DY V FY G YMAX G YMIN Recording C signal GCA frequency response (center) Recording Y signal GCA secondary distortion (center gain) Recording C signal GCA minimum gain Recording C signal GCA maximum gain Recording Y signal GCA frequency response (center) Recording Y signal GCA minimum gain Recording Y signal GCA maximum gain V REG I pb I rec Symbol 10 9 8 7 6 5 4 Item Circuit current during recording Circuit current during playback Recording system 3 2 1 No. Electrical Characteristics Target Values — — — — — — 7 MHz 10 MHz 60 mVp-p 30 90 mVp-p 30 136 mVp-p 30 700 kHz 2 MHz 300 kHz 30 305 mVp-p 300 kHz 32 500 mVp-p 32 500 mVp-p 32 225 mVp-p 300 kHz 32 1120 mVp-p 300 kHz — — — B B B B B B B B B F B 3.95 16 20 Min. –1.3 10 MHz level/300 kHz level Pin 1 (YLEVEL) = Vylev (center gain) 2 MHz level/300 kHz level Pin 31 (CLEVEL) = Cylev (center gain) 13 Pin 31 (CLEVEL) = 4.75 V –0.5 Pin 31 (CLEVEL) = 4.75 V 13 13 –2.4 Pin 31 (CLEVEL) = 0 V 13 — — Pin 1 (YLEVEL) = Vylev (center gain) 13 — –1.7 Pin 1 (YLEVEL) = 4.75 V 13 — Pin 1 (YLEVEL) = 0 V 13 4.15 23 29 Typ. 4.35 30 38 Max. V mA mA Unit — 0.7 — –56 0 0.6 — 0.5 — –17.8 –16.4 –50 –0.3 0.9 –17.2 –15.7 dB dB dB dB dB dB dB dB (∗1: Including recording amplifier 1ch output bias current) Pin voltage measurement Current consumption inside IC during switching recording ∗1 Current consumption inside IC during playback Measurement method 13 10 IVCC IVCC Measurement Measurement conditions pin or Input conditions Log Pin Level Frequency ic ammeter name ∗See the Control Logic Truth Table for control logic. (VCC=4.75 V, Ta=25 °C, See the Electrical Characteristics Measurement Circuit.) CXA2032Q Item —12— RFAGC cover range Low Dropout detection ON level Dropout detection OFF level K DO-OFF Dropout pulse Low level Dropout pulse High level 19 20 21 22 23 V DOP-H V DOP-L K DO-ON V AGC3 V AGC2 RFAGC cover range High 18 V AGC1 GV1 GV2 896 mVp-p 56 mVp-p 224 mVp-p 200 µVp-p 200 µVp-p 184 mVp-p 184 mVp-p 184 mVp-p 184 mVp-p — 90 mVp-p 7 MHz 7 MHz 7 MHz 300 kHz 300 kHz 1 MHz 1 MHz 10 MHz 10 MHz — 1.7 MHz See Measurement method (figure to right). 9 9 9 18 23 14 27 14 27 I R1 I R2 ∆R1 ∆R2 RFAGC standard output Playback amplifier, RFSW gain — 30 IB1, 2 D AFM Symbol 17 16 12 Recording AFM signal secondary distortion (maximum gain) Recording amplifier output 13 bias current Recording amplifier output 14 current Recording amplifier 15 frequency response Playback system No. F F F F F F F F E B B B B B B Output level (mVp-p)/51 Ω Output level (mVp-p)/51 Ω 10 MHz level/1 MHz level 10 MHz level/1 MHz level 17 24 17 24 5 5 5 5 7 7 7 Pin 5 Output Pin 9 Input VDOP-H a b 224mVp-p 7MHz VDOP-L KDO-ON=20log (a/224) KDO-OFF=20log (b/224) 10kHz Apply time constant to Pin 8 (RFAGCTC). Measure output level, applying time constant to Pin 8 (RFAGCTC). DC current measurement IB1, 2 11 11 Pin 31 (CLEVEL) = 4.75 V Measurement method 13 Measurement Measurement conditions pin or Input conditions Log Pin Level Frequency ic ammeter name 425 375 400 495 — 470 64.9 — 21.4 20.2 — Max. 2.9 0 –8.5 3.15 0.01 –5.5 3.4 0.2 –2.5 –13.5 –10.5 –7.5 — 310 330 61.4 0 — 57.9 19 16.5 –55 Typ. 16.6 12.7 — Min. V dB mV p-p dB dB mA p-p mA dB Unit CXA2032Q Item Dropout ON detection time Dropout OFF detection time No. 24 25 T DOP -OFF T DOP -ON Symbol See Measurement method (figure to right). F F 5 5 Measurement Measurement conditions pin or Input conditions Log ammeter name Pin Level Frequency ic TDOP-ON Pin 5 Output Pin 9 Input TDOP-OFF 50µsec 5kHz 7MHz/224mVp-p Apply time constant to Pin 8 (RFAGCTC). Measurement method — — Min. 2 1 Typ. — — Max. µs Unit CXA2032Q —13— CXA2032Q Control Logic Truth Table Input Control Operation of each section under conditions logic input respective input conditions and conditions Recording system Playback system operation R R B V V R R P P P R D P F O O O E E B B B F O P S T U U C C 1 2 R A C B W H T T 1 2 c c F G D P R 1 2 O O h h O C E Name of E U U A A U O T C T T M M T U control logic T P P conditions 2 3 4 13 28 17 24 11 7 L L L V V ∆ V × × × × × A Operation B L H L V V V ∆ × × × × × VIDEO EACH REC ↓ ↓ C L L H V V V V × × × × × VIDEO BOTH REC D L H H V V V V × × × × × ↓ ↓ E H L — × × × × O O CH2 O O PB O ↓ ↓ F H H — × × × × O O CH1 O REC (Description of input conditions) H · · · Control logic input voltage of 2.3 V or more L · · · Control logic input voltage of 0.6 V or less — · · · Don’t care. (Description of operation mode) O · · · Operating × · · · Not operating V · · · Video signal is output. ∆ · · · Operating but bias current is OFF. CH1 · · · CH1 signal is output. CH2 · · · CH2 signal is output. —14— Mode PB IB1 A 21 GND —15— 22 GND 5.6µ 0.01µ REC2OUT 20 2ND REC2CH REC 15dB 40dB HEAD 15dB 2CH 6dB 1 1 23 . CGCA YGCA CXA2032Q LOGIC DOCDET 2 1 0.01µ YIN 31 30 29 28 VCC2 15k 4.75V GND IVCC 51 19 A 15k 18 3 REC2OUT 0.1µ 40dB 10µ PBRFOUT 0.01µ 12 10µ VCC 4 PB2IN 17 49 VCC1 5 PB2IN 16 CIN YIN YLEVEL RP PB RFSWP BOTH REC DOP DOCDET RFAGCTC RFAGCOUT 0.01µ 0.1µ 0.01µ 470k 4700P Signal input pin (signal source impedance 50Ω) Signal output pin (measurement point) EVR adjusting pin Control logic pin • Head amplifier input (PB1IN, PB2IN): The input level is specified by a value attenuated to 1/50. YLEVEL RP PB RFSWP BOTH REC DOP RFAGCOUT RFAGCTC GND PBDUMP2 GND2 0.01µ 1.5k BUFF 0.01µ 390 390 13 RFAGC 11 6 0.022µ 0.022µ VOUT1 7 PBDUMP1 100µ 2ND 8 GND1 10µ GND 1 GND 14 REC1IN RECDUMP1 15 47k HEAD VOUT1 1 GND 10 VREG 0.01µ 51 9 5.6µ REC1IN RFAGCIN AGCDET 51 PB1IN GND 49 PBRFOUT RFSW 1CH 0.1µ REC GND REC1CH 10µ REC1OUT PB1IN RFAGCIN REC1OUT GND A Electrical Characteristics Measurement Circuit CXA2032Q GND 51 32 GND 0.01µ GND CLEVEL CLEVEL 0.01µ CIN 51 GND GND GND VOUT2 VOUT2 1.5k 0.01µ 27 REC2IN REC2IN RECDUMP2 51 GND 47k 26 25 100µ 24 10µ 0.1µ GND 51 GND IB2 GND 100µ VCC1 16 RECDUMP1 15 15k 17 18 19 20 21 22 1CH HEAD —16— 23 REC 2ND 15dB 1 1 CGCA YGCA CXA2032Q 12 REC2CH REC1IN 15dB 2CH 6dB 11 RFAGC LOGIC DOCDET BUFF AGCDET 3 2 1 32 0.01µ YIN 31 29 25 VCC2 24 2CH HEAD 0.01µ CLEVEL 2k 0.1µ 30 3.3k 0.1µ CIN 3.3k 0.1µ GND 28 0.01µ 1.5k VOUT2 27 47k REC2IN 26 RECDUMP 15k 100µ 10µ 0.1µ YLEVEL RP PB RFSWP BOTH REC DOP DOCDET RFAGCOUT RFAGCTC C 0.01µ 0.1µ 470k 4700P Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 0.01µ REC2OUT 14 4 HEAD VOUT1 40dB 47k 5 PB2IN 13 6 PBDUMP2 GND2 0.1µ 1.5k 0.01µ 40dB VCC 2ND 10µ 7 GND1 PBDUMP1 0.1µ 10 0.01µ 10µ VREG HEAD PBRFOUT RFSW 1CH 10µ REC 0.1µ 9 PB1IN REC1OUT 10µ RFAGCIN REC1CH Y Y/C SEP 8 0.022µ 390 0.022µ 390 Application Circuit REC Y RF REC C RF REC ATF REC AFM CLEVEL YLEVEL RP PB RFSWP BOTH REC PB RF PB C RF PB Y RF DOP RP GND RP VCC SIGNAL IN EVR CONTROL CONTROL LOGIC SIGNAL OUT CXA2032Q 10µ 0.1µ CXA2032Q Description of Operation <Recording level adjustment> Y, chroma, AFM and ATF signals are adjusted at specified levels so that they are mixed internally to achieve an appropriate value at the head, then output to Pins 13 (VOUT1) and 28 (VOUT2). The Y level is EVR adjusted at Pin 1 (YLEVEL) and the low-band level (chroma, AFM, ATF) at Pin 31 (CLEVEL). <Recording amplifier> The signal, which underwent recording level adjustment, is V/I converted by external resistor, then input to Pins 14 (REC1IN) and 27 (REC2IN). The current of the input signal is amplified by the recording amplifier, and this signal is then output from Pins 17 (REC1OUT) and 24 (REC2OUT) to drive the head. A feedback damping circuit is incorporated into the recording amplifier to inhibit head resonance, and the peaking amount can be adjusted by external resistors attached to Pins 15 (RECDUMP1) and 26 (RECDUMP2). During recording, the output capacitance is about 12 pF including that of the playback amplifier. <Playback amplifier> The playback signal from the head is amplified with low noise and high gain. A feedback damping circuit is incorporated to inhibit head resonance, and the peaking amount can be adjusted by external resistors attached to Pins 20 (PBDUMP1) and 21 (PBDUMP2). During playback, the output capacitance is approximately 20 pF including that of the recording amplifier. <RFSW> This section switches the playback signals of channels 1 and 2 at the correct timing and outputs the playback video signal to Pin 11 (PBRFOUT). Switching is performed at Pin 3 (RFSWP). <RFAGC> This section inputs the playback Y signal separated from playback video signal using an external circuit and outputs it at a constant level of 400 mVp-p. <Dropout detection> A dropout is detected in the playback Y signal, and a dropout pulse is output. The detection level is optimized using 224 mVp-p input as a reference. <Control logic> In order to save power consumption, this IC exercises power-saving control of circuit blocks which are not in need for operation depending on the mode. The IC also incorporates a logic circuit for controlling the built-in switches which change inputs and outputs. The combinations of input and output required for basic operation are shown in the Control Logic Truth Table. <Reference voltage in the IC> VREG 4.15 V is generated as the reference voltage used in the IC. —17— CXA2032Q Notes on Operation 1. This IC is characterized by high-voltage gain (approximately 61 dB in the playback system). Be careful of the following when using the IC. 1) Use a reinforced power supply and ground lines. Decouple the power supply pin with a coil and a capacitor. Connect each decoupling capacitor as close to the pin as possible. 2) Use of a regulator power supply is recommended. 3) Connecting a capacitive load to the output may cause oscillation. 4) Take particular care not to make capacitive coupling between the head amplifier input and the playback output. Also be careful not to make capacitive coupling between the recording input and the recording amplifier output. 5) Use of decoupling capacitors is recommended between the following DC voltage input pins and GND. When the control voltage source is at high impedance, aggravation of cross talk or oscillation may occur. Pin 1 (YLEVEL), Pin 31 (CLEVEL) 6) When a decoupling capacitor is necessary for other pins (not power supply pin), it is recommended to connect each decoupling capacitor as close to the pin as possible. 7) The voltage input to EVR adjusting pins should be proportional to the supply voltage VCC. Control the input voltage in the range from 0 to 4.75 V when VCC = 4.75 V. For EVR adjustment at Pin 8 (RFAGCTC), control the input voltage in the range of 2.5 V to 4.75 V. —18— CXA2032Q Characteristics Graphs Y signal GCA gain control (dB) 2 Pin 30 (CIN) → Pin 13 (VOUT1) and Pin 28 (VOUT2) I/O gain Pin 32 (YIN) → Pin 13 (VOUT1) and Pin 28 (VOUT2) I/O gain 0 –2 –4 –6 –8 –10 –12 –14 VCC=4.75V VIN=225mVp-p 300kHz –16 0 –2 –4 –6 –8 –10 –12 –14 VCC=4.75V VIN=60mVp-p 100kHz –16 –18 –18 1 2 3 Pin 1 (YLEVEL) voltage (V) 4 5 RFAGC gain control (dB) (with EVR adjustment at Pin 8) 20 Pin 9 (RFAGCIN) → Pin 7 (RFAGCOUT) I/O gain C signal GCA gain control (dB) 2 10 0 VCC=4.75V VIN=50mVp-p 7MHz –10 2.5 3.0 3.5 4.0 Pin 8 (RFAGCTC) voltage (V) 4.5 4.75 —19— 1 2 3 Pin 31 (CLEVEL) voltage (V) 4 5 CXA2032Q Package Outline Unit : mm 32PIN QFP (PLASTIC) 9.0 ± 0.2 24 0.1 + 0.35 1.5 – 0.15 + 0.3 7.0 – 0.1 17 16 32 9 (8.0) 25 1 + 0.2 0.1 – 0.1 0.8 0.24 M + 0.1 0.127 – 0.05 0° to 10° PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP-32P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE QFP032-P-0707 LEAD MATERIAL 42 ALLOY PACKAGE MASS 0.2g JEDEC CODE —20— 0.50 8 + 0.15 0.3 – 0.1