Preliminary VN16118 SERDES Gigabit Ethernet Transceiver Applications • • Gigabit Ethernet Up-links High Speed Proprietary interface • • Backplane Serialization Bus Extender General Description The VN16118 is a single chip,1.25 Gigabits per second Ethernet transceiver. It performs all the functions of the Physical Medium Attachment (PMA) portion of the Physical layer, as specified by the IEEE 802.3z Gigabit Ethernet standard. These functions include parallel-to-serial and serial-to-parallel conversion, clock generation, clock data recovery, and word synchronization. In addition, an internal loopback function is provided for system debugging. The VN16118 is ideal for Gigabit Ethernet, serial backplane and proprietary point-to-point applications. The device supports both 1000BASE-LX and 1000BASE-SX fiber-optic media, and 1000BASE-CX copper media. The transmitter section of the VN16118 accepts 10-bit wide parallel TTL data and converts it to a high speed serial data stream. The parallel data is encoded in 8b/10b format. This incoming parallel data is latched into an input register, and synchronized on the rising edge of the 125 MHz reference clock supplied by the user. A phase locked loop (PLL) locks to the 125 MHz clock. The clock is then multiplied by 10 to produce a 1.25 GHz serial clock that is used to provide the high speed serial data output. The output is sent through a Pseudo Emitter Coupled Logic (PECL) driver. This output connects directly to a copper cable in the case of 1000BASE-CX medium, or to a fiber optic module in the case of 1000BASE-LX or 1000BASE SX fiber optic medium. The receiver section of the VN16118 accepts a serial PECL-compatible data stream at a 1.25 Gbps rate, recovers the original 10-bit wide parallel data format, and retimes the data. A Phase Lock Loop (PLL) locks on to the incoming serial data stream, and recovers the 1.25 GHz high speed serial clock and data. This is accomplished by continually frequency locking on to the 125 MHz reference clock, and by phase locking on to the incoming data stream. The serial data is converted back to parallel data format. The ‘comma’ character is used to establish byte alignment. Two 62.5 MHz clocks, 180 degrees out of phase, are recovered. These clocks are alternately used to clock out the parallel data on the rising edge. This parallel data is sent to the user in TTL-compatible form. Features • • • • • IEEE 802.3z Gigabit Ethernet Compliant Supports 1.25 Gbps Using NRZ Coding over uncompensated twin-coax cable Fully integrated CMOS IC Low Power Consumption ESD rating >2000V (Human Body Model) or >200V (Machine Model) 1999-12-15 • • • Page 1 5-Volt Input Tolerance Fully Compatible with HP HDMP1636/HDMP-1646 and Vitesse VCS7135 transceivers Available in both 10 mm x 10 mm and 14 mm x 14 mm LQFP Packages MDSN-0001-00 Vaishali Semiconductor l 747 Camden Avenue l Campbell l CA 95008 l Ph. 408.379.2900 l Fax 408.379.2937 Preliminary VN16118 Figure 1. Functional Block Diagram EWRAP 10 TX<9:0> 10 Input Data Latch DOUT+ Shift Registers DOUT- TX PLL Clock Generator TX_CLK 62.5 MHz RX_CLK<1> ÷2 RX_CLK<0> 62.5 MHz 125 MHz RX<9:0> 10 RX PLL Clock Recovery Output Latch EN_CDET COM_DET 1999-12-15 FRAME ENABLE 10 Shift Registers INPUT SELECTOR 10 Page 2 Vaishali Semiconductor l 747 Camden Avenue l Campbell l CA 95008 l Ph. 408.379.2900 l Fax 408.379.2937 DIN+ DIN- MDSN-0001-00 Preliminary VN16118 NC VCC_RXF GND_RXF DIN- VCC_RX_ESD DIN+ VCC_RX_ESD GND_RX_ESD VCC_RXA GND_RXA VCC_RXA VCC_TX_ECL DOUT- DOUT+ VCC_TX_HS GND_TX_HS Figure 2. Pin Configuration (Top View) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 GND_ESD 1 48 NC TX<0> 2 47 COM_DET TX<1> 3 46 GND_RXT TX<2> 4 45 RX<0> VCC_ESD 5 44 RX<1> TX<3> 6 43 RX<2> TX<4> 7 42 VCC_RXT TX<5> 8 41 RX<3> TX<6> 9 40 RX<4> VCC_ESD 10 39 RX<5> TX<7> 11 38 RX<6> TX<8> 12 37 VCC_RXT TX<9> 13 36 RX<7> GND_ESD 14 35 RX<8> GND_TXA 15 34 RX<9> NC 16 33 GND_RXT GND_RX RX_CLK<0> RX_CLK<1> VCC_RX NC VCC_RXD SIG_DET GND_RXD EN_CDET TX_CLK VCC_RXD VCC_TXD GND_TXD EWRAP NC 1999-12-15 VCC_TXA 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Page 3 Vaishali Semiconductor l 747 Camden Avenue l Campbell l CA 95008 l Ph. 408.379.2900 l Fax 408.379.2937 MDSN-0001-00 Preliminary VN16118 Table 1. Pin Description Name Pin # GND_ESD 1, 14 VCC_ESD 5, 10 TX<0> 2 TX<1> 3 TX<2> 4 TX<3> 6 TX<4> 7 TX<5> 8 TX<6> 9 TX<7> 11 TX<8> 12 TX<9> 13 GND_TXA 15 VCC_TXA 18 NC 16, 17, 27, 48, 49 Type Description Power Power and ground pairs for pad ESD structure. TTL Input 10-bit parallel data input pins. This data should be 10b/8b encoded. The least significant bit is TX<0> and is transmitted first. Power Power and ground pair for TX PLL analog circuits. No Connect These pins are bonded to isolated pads and have no connection to internal circuits. EWRAP 19 TTL Input Wrap Enable. This pin is active HIGH. When asserted, the high-speed serial data are internally wrapped from the transmitter serial data output back to the receiver data input. Also, when asserted, DOUT± are held static at logic 1. When deasserted, DOUT± and DIN± are active. VCC_TXD 20 Power Power and ground pair for TX digital circuits. GND_TXD 21 TX_CLK 22 TTL Input Reference clock and transmit byte clock. This is a 125 MHz system clock supplied by the host system. On the positive edge of the clock, the input data, TX<9:0>, are latched into the register. This clock is multiplied by 10 internally, to generate the transmit serial bit clock. VCC_RXD 23 28, Power Power and ground pair for digital circuits in the receiver portion. GND_RXD 25 EN_CDET 24 TTL Input Comma Detect Enable. This pin is active HIGH. When asserted, the internal byte alignment function is turned on, to allow the clock to synchronize with the comma character (0011111XXX). When de-asserted, the function is disabled and will not align the clock and data. In this mode COM_DET is set to LOW. SIG_DET 26 TTL Output Signal Detect. This pin is active HIGH. It indicates the loss of input signal on the high-speed serial inputs, DIN±. SIG_DET is set to LOW when differential inputs are less than 50 mV. VCC_RX GND_RX 29 32 Power Power and ground pair for the clock signal of the receiver portion. RX_CLK<1> RX_CLK<0> 30 31 TTL Output Receiver Byte Clocks. Two 180 degrees out-of-phase 62.5 MHz clock signals that are recovered by the receiver section. The received bytes are alternately clocked by the rising edges of these signals. The rising edge of RX_CLK<1> aligns with a comma character when detected. 1999-12-15 Page 4 Vaishali Semiconductor l 747 Camden Avenue l Campbell l CA 95008 l Ph. 408.379.2900 l Fax 408.379.2937 MDSN-0001-00 Preliminary VN16118 Table1. (Continued) Name Pin# Type Description GND_RXT VCC_RXT 33 46, 37, 42 Power Power and ground pairs for ESD structure. RX<9> RX<8> RX<7> RX<6> RX<5> RX<4> RX<3> RX<2> RX<1> RX<0> 34 35 36 38 39 40 41 43 44 45 TTL Output Received Parallel Data Output. RX<0> is the least significant bit and is received first. When DIN± lose input data, all RX pins will be held HIGH. COM_DET 47 TTL Output Comma detect. This pin is active HIGH. When asserted, it indicates the detection of comma character (0011111XXX). It is active only when EN_CEDT is enabled. VCC_RXF GND_RXF 50 51 Power Power and ground pair for the front-end of the receiver section. DIN+ DIN- 52 54 Input High-speed serial data input. Serial data input is received when EWRAP is disabled. VCC_RXESD GND_RXESD 53,55 56 Power Power and ground pair for ESD structure. VCC_RXA GND_RXA 57, 59 58 Power Power and ground pair for analog circuits of the receiver section. VCC_TX_ECL 60 Power Power supply to line driver circuits. Ground supply is from pin 64. DOUTDOUT+ 61 62 Output High-speed serial data output. These pins are active when EWRAP is disabled and are held static at logic 1 when EWRAP is enable. VCC_TX_HS 63 Power GND_TX_HS 64 Power and ground pair for high-speed transmit logic in the parallel-to-serial section. 1999-12-15 Page 5 Vaishali Semiconductor l 747 Camden Avenue l Campbell l CA 95008 l Ph. 408.379.2900 l Fax 408.379.2937 MDSN-0001-00 Preliminary VN16118 Functional Block Description Input Data Latch The input data latch block latches the 10-bit TTL input parallel byte, TX<9:0>, on the rising edge of the 125 MHz user-provided TX_CLK into the holding registers. Parallel-to-Serial Converter The received 10-bit TTL parallel input byte is converted to serial PECL level data stream by the parallel-to-serial block, and is transmitted differentially to the line driver block at 1.25 Gbps. The 8b/10b encoded data is transmitted sequentially with bit 0 being sent first. Clock Generator The 1250 MHz signal used for clocking the serial outputs is generated by the TX PLL block based on the user-provided TX_CLK. This clock should have a ±100 ppm tolerance. Internal Loopback When EWRAP is set to a logic HIGH, the serial data stream generated by the transmitter is looped back to the receiver path, instead of going out to the DOUT± pins. When in loopback mode, a static logic 1 is transmitted at the line driver (DOUT+ is HIGH and DOUT- is LOW). Signal Detect Signal detect block is used to sense the serial input data stream at pins DIN±. If the serial input is lower than 50 mV differentially, this block deasserts SIG_DET and sets the output, RX<9:0>, to all logic ones. When the serial input at pins DIN± is greater than 50 mV, the signal is directed to the receive path. Equalizer and Slicer The signal received from the line (DIN± pins) is distorted by the cable bandwidth. In order to maintain a low bit-error rate, an equalizer is used to compensate for the signal loss. The slicer recovers the differential low-level signal to a CMOS-level single-ended signal, for clock recovery and data re-timing. Clock Recovery The serial input data stream contains both data and clock. The clock recovery block is used to extract both data and clocks from this input. In addition to data, two clocks of 62.5 MHz are recovered. Table 2. Absolute Maximum Ratings Symbol Parameter Min. Max. Units Vcc Supply voltage -0.5 5.0 V VIN,TTL TTL Input Voltage -0.7 Vcc + 2.8 V VIN,HS_IN HS_IN Input Voltage 2.0 Vcc V I O,TTL TTL Output Source Current 13 mA Tstg Storage Temperature -65 +150 °C Tj Junction Operating Temperature 0 +150 °C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and correct functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. 1999-12-15 Page 6 Vaishali Semiconductor l 747 Camden Avenue l Campbell l CA 95008 l Ph. 408.379.2900 l Fax 408.379.2937 MDSN-0001-00 Preliminary VN16118 Table 3. Guaranteed Operating Rates TA = 0 oC to +70oC, V CC = 3.15 V to 3.45 V Parallel Clock Rate (MHz) Min. Max. Serial Baud Rate (Mbaud) Min. Max. 124.0 1240 126.0 1260 Table 4. AC Electrical Characteristics TA = 0°C to +70°C, V CC = 3.15 V to 3.45 V Symbol Parameter Min. Typ. Max . Unit t r,REFCLK REFCLK Rise Time, 0.8 to 2.0 Volts 2.4 nsec t f,REFCLK REFCLK Fall Time, 2.0 to 0.8 Volts 2.4 nsec t r,TTLin Input TTL Rise Time, 0.8 to 2.0 Volts 2 nsec t f,TTLin Input TTL Fall Time, 2.0 to 0.8 Volts 2 nsec t r,TTLout Output TTL Rise Time, 0.8 to 2.0 Volts, 10 pF Load 1.5 2.4 nsec t f,TTLout Output TTL Fall Time, 2.0 to 0.8 Volts, 10 pF Load 1.1 2.4 nsec t rs,HS_OUT HS_OUT Single-Ended (DOUT+) Rise Time 85 225 327 psec t fs,HS_OUT HS_OUT Single-Ended (DOUT+) Fall Time 85 200 327 psec t rd,HS_OUT HS_OUT Differential Rise Time 85 327 psec t fd,HS_OUT HS_OUT Differential Fall Time 85 327 psec HS_IN Input Peak-to-Peak Differential Voltage 200 1200 2000 mV HS_OUT Output Peal-to-Peak Differential Voltage 1200 1600 2000 mV Typ. Max . Unit VIP,HS_IN VOP,HS_OUT (1) Note: 1. Output Peak-to-Peak Differential Voltage specified as DOUT+ minus DOUT- Table 5. DC Electrical Characteristics TA = 0°C to +70°C, V CC = 3.15 V to 3.45 V Symbol Parameter Min. VIH,TTL TTL Input High Voltage Level, Guaranteed High Signal for All Inputs 2 5.5 V VIL,TTL TTL Input Low Voltage Level, Guaranteed Low Signal for All Inputs 0 0.8 V VOH,TTL TTL Output High Voltage Level, IOH = -400 µA 2.2 VCC V VOL,TTL TTL Output Low Voltage Level, IOL = 1 mA 0 0.6 V I IH,TTL Input High Current, VIN = 2.4 V, VCC = 3.45 V 40 µA I IL,TTL Input Low Current, VIN = 0.4 V, VCC = 3.45 V -600 µA I CC,TRX[1,2] Transceiver VCC Supply Current, TA = 25°C 220 mA Notes: 1. Measurement Conditions: Tested sending 1250 MBd PRBS 27-1 sequence from a serial Bit Error Rate Tester (BERT) with DOUT± outputs terminated with 150 Ω resistors to GND. 2. Typical values are at Vcc = 3.3 volts. 1999-12-15 Page 7 Vaishali Semiconductor l 747 Camden Avenue l Campbell l CA 95008 l Ph. 408.379.2900 l Fax 408.379.2937 MDSN-0001-00 Preliminary VN16118 Table 6. Transceiver Reference Clock Requirements TA = 0°C to +70°C, V CC = 3.15 V to 3.45 V Symbol Parameter Min. Typ. Max. f Nominal Frequency (for gigabit Ethernet Compliance) 125 F tol Frequency Tolerance -100 +100 Symm Symmetry (Duty Cycle) 40 60 Unit MHz ppm % Table 7. Transmitter Timing Characteristics TA = 0°C to +70°C, V CC = 3.15 V to 3.45 V Parameter Symbol Min. Typ. Max. Unit t setup Setup Time to Rising Edge of REFCLK 1.5 nsec t hold Hold Time to Rising Edge of REFCLK 1.0 nsec t_txlat [1] Transmitter Latency 3.5 nsec 4.4 bits Note: 1. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered by the rising edge of the transmit by clock, REFCLK) and the transmission of the first serial bit of that parallel word (defined by the rising edge of the first bit transmitted). 1.4 V TX_CLK 2.0 V TX<9:0> DATA DATA DATA DATA DATA DATA 0.8 V tSETUP tHOLD Figure 3. Transmitter Section Timing DATA BYTE A DATA BYTE B DOUT± T5 T6 T7 T8 T9 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T0 T1 T2 T3 T4 T5 t_TXLAT TX<9:0> DATA BYTE B DATA BYTE C 1.4 V TX_CLK Figure 4. Transmitter Latency 1999-12-15 Page 8 Vaishali Semiconductor l 747 Camden Avenue l Campbell l CA 95008 l Ph. 408.379.2900 l Fax 408.379.2937 MDSN-0001-00 Preliminary VN16118 Table 8. Receiver Timing Characteristics TA = 0°C to +70°C, Vcc = 3.15 V to 3.45 V Symbol Parameter Min. Typ. Max. Unit b_sync[1] Bit Sync Time 2500 bits f_lock Frequency Lock at Powerup 500 µs t SETUP Data Setup Before Rising Edge of RX_CLK 2.5 nsec t HOLD Data Hold After Rising Edge of RX_CLK 1.5 nsec t DUTY RX_CLK Duty Cycle 40 60 % RX_CLK Skew 7.5 8.5 nsec t A-B [2] T_rxlat Receiver Latency 22.4 nsec 28.0 bits Notes: 1. This is the recovery for input phase jumps. 2. The receiver latency as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word (defined as the first edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive byte clock, either RBC1 or RBC0). tSETUP tHOLD RX_CLK<1> 1.4 V 2.0 V RX<9:0> K28.5 DATA DATA DATA DATA 0.8 V 2.0 V COM_DET 0.8 V RX_CLK<0> 1.4 V tA-B Figure 5. Receiver Section Timing DATA BYTE C DIN± DATA BYTE D R5 R6 R7 R8 R9 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R2 R3 R4 R5 t_rxlat RX<9:0> DATA BYTE A DATA BYTE D 1.4 V RX_CLK<1>/<0> Figure 6. Receiver Latency 1999-12-15 Page 9 Vaishali Semiconductor l 747 Camden Avenue l Campbell l CA 95008 l Ph. 408.379.2900 l Fax 408.379.2937 MDSN-0001-00 Preliminary VN16118 c b E1 E L1 e TOP VIEW A2 A D D A1 Figure 7. Mechanical Dimensions All dimensions are in millimeters PART D1/E1 D/E NUMBER VN16118L1 10 12 VN16118L2 14 16 Package follows JEDEC Standards b e L1 c A2 A1 A 0.2 0.35 0.5 0.8 1.0 1.0 0.127 0.127 1.4 1.4 0.1 0.1 1.5 1.5 Ordering Information Part Number VN16118L1 No. of Pins 64 Package LQFP Temperature 0°C to +70°C VN16118L2 64 LQFP 0°C to +70°C 1999-12-15 Page 10 Vaishali Semiconductor l 747 Camden Avenue l Campbell l CA 95008 l Ph. 408.379.2900 l Fax 408.379.2937 MDSN-0001-00