AGILENT HDMP-1526

Fibre Channel Transceiver Chip
Technical Data
HDMP-1526 Transceiver
Features
• ANSI X3.230-1994 Fibre
Channel Compatible (FC-0)
• Supports Full Speed
(1062.5 MBd) Fibre Channel
• Conforms to “Fibre Channel
10-Bit Interface”
Specification
• Transmitter and Receiver
Functions Incorporated onto
a Single IC
• 10-Bit Wide Parallel TTL
Compatible I/Os
• Single +5.0 V Power Supply
Applications
• 1062.5 MBd Fibre Channel
Interface
• Mass Storage System I/O
Channel
• Work Station/Server I/O
Channel
• High Speed Proprietary
Interface
Description
The HDMP-1526 transceiver is a
single silicon bipolar integrated
circuit packaged in an EDQuad
package. It provides a low-cost,
low-power physical layer solution
for 1062.5 MBd Fibre Channel or
proprietary link interfaces. It
provides complete FC-0 functionality for copper transmission,
incorporating both the Fibre
Channel FC-0 transmit and
682
receive functions into a single
device.
This chip is used to build a highspeed interface (as shown in
Figure 1) while minimizing board
space, power and cost. It is
compatible with both the ANSI
X3.230-1994 document and the
“Fibre Channel 10-bit Interface”
specification.
The transmitter section accepts
10-bit wide parallel TTL data and
multiplexes this data into a highspeed serial data stream. The
parallel data is expected to be
8B/10B encoded data, or
equivalent. This parallel data is
latched into the input register of
the transmitter section on the
rising edge of the 106.25 MHz
reference clock (used as the
transmit byte clock).
The transmitter section’s PLL
locks to this user supplied 106.25
MHz byte clock. This clock is
multiplied by 10, to generate the
1062.5 MHz serial signal clock
used to generate the high-speed
output. The high-speed outputs
are capable of interfacing directly
to copper cables for electrical
transmission or to a separate
fiber-optic module for optical
transmission.
The receiver section accepts a
serial electrical data stream at
1062.5 MBd and recovers the
original 10-bit wide parallel data.
The receiver PLL locks onto the
incoming serial signal and
recovers the high-speed serial
clock and data. The serial data is
converted back into 10-bit
parallel data, recognizing the
8B/10B comma character to
establish byte alignment.
The recovered parallel data is
presented to the user at TTL
compatible outputs. The receiver
section also recovers two 53.125
MHz receiver byte clocks that are
180 degrees out of phase with
each other. The parallel data is
aligned with the rising edge of
alternating clocks.
The transceiver provides for onchip local loop-back functionality,
controlled through an external
input pin. Additionally, the byte
synchronization feature may be
disabled. This may be useful in
proprietary applications that use
alternative methods to align the
parallel data.
5964-6897E (5/96)
HDMP-1526 Block Diagram
HDMP-1526
TRANSMITTER SECTION
SERIAL DATA OUT
PLL
PROTOCOL DEVICE
PLL
SERIAL DATA IN
RECEIVER SECTION
BYTSYNC
REFCLK
ENBYTSYNC
-LCKREF
DATA BYTE
TX[0-9]
INPUT
LATCH
Figure 1. Typical Application Using the HDMP-1526.
FRAME
MUX
OUTPUT
SELECT
INTERNAL
LOOPBACK
TXCAP0
TXCAP1
TX
PLL/CLOCK
GENERATOR
INTERNAL
Tx CLOCKS
REFCLK
-LCKREF
RXCAP0
RXCAP1
RBC0
RBC1
RX
PLL/CLOCK
RECOVERY
OUTPUT
DRIVER
DATA BYTE
RX[0-9]
INPUT
SELECT
FRAME
DEMUX
AND
BYTE SYNC
BYTSYNC
INTERNAL
Rx CLOCKS
INPUT
SAMPLER
ENBYTSYNC
Figure 2. HDMP-1526 Transceiver Block Diagram.
± DOUT
LOOPEN
± DIN
The HDMP-1526 was designed to
transmit and receive 10-bit wide
parallel data over a single highspeed line, as specified for the FC-0
layer of the Fibre Channel standard.
The parallel data applied to the
transmitter is expected to be
encoded per the Fibre Channel
specification, which uses an 8B/10B
encoding scheme with special
reserve characters for link
management purposes. In order to
accomplish this task, the HDMP1526 incorporates the following:
• TTL Parallel I/Os
• High-Speed Phase Lock Loops
• Clock Generation/Recovery
Circuitry
• Parallel-to-Serial Converter
• High-Speed Serial Clock-and-Data
Recovery Circuitry
• Comma Character Recognition
Circuitry
• Byte Alignment Circuitry
• Serial-to-Parallel Converter
INPUT LATCH
The transmitter accepts 10-bit wide
TTL parallel data at inputs TX[0..9].
The user-provided reference clock
signal, REFCLK, is also used as the
transmit byte clock. The TX[0..9]
and REFCLK signals must be
properly aligned, as shown in
Figure 3.
TX PLL/CLOCK GENERATOR
The transmitter Phase Lock Loop
and Clock Generator (TX PLL/
CLOCK GENERATOR) block is
responsible for generating all
internal clocks needed by the
transmitter section to perform its
functions. These clocks are based on
the supplied reference byte clock
(REFCLK). REFCLK is used as both
the frequency reference clock for
the PLL and the transmit byte clock
for the incoming data latches. It is
expected to be 106.25 MHz and
properly aligned to the incoming
683
parallel data (see Figure 3). This
clock is multiplied by 10 to
generate the 1062.5 MHz clock
necessary for the high-speed
serial outputs.
FRAME MUX
The FRAME MUX accepts the 10bit wide parallel data from the
INPUT LATCH. Using internally
generated high-speed clocks, this
parallel data is multiplexed into
the 1062.5 MBd serial data
stream. The data bits are
transmitted sequentially, from the
least significant bit (TX[0]) to the
most significant bit (TX[9]).
OUTPUT SELECT
The OUTPUT SELECT block
provides for an optional internal
loopback of the high-speed serial
signal, for testing purposes.
In normal operation, LOOPEN is
set low and the serial data stream
is placed at ± DOUT. When wrapmode is activated by setting
LOOPEN high, the ± DOUT pins
are held static and the serial
output signal is internally
wrapped to the INPUT SELECT
box of the receiver section.
INPUT SELECT
The INPUT SELECT block
determines whether the signal at
± DIN or the internal loop-back
serial signal is used. In normal
operation, LOOPEN is set low
and the serial data is accepted at
± DIN. When LOOPEN is set
high, the high-speed serial signal
is internally looped-back from the
transmitter section to the receiver
section. This feature allows for
loop-back testing exclusive of the
transmission medium.
684
RX PLL/CLOCK RECOVERY
The RX PLL/CLOCK RECOVERY
block is responsible for frequency
and phase locking onto incoming
serial data stream and recovering
the bit and byte clocks.
In order to accomplish this, upon
startup, the user should set
-LCKREF low for a period of at
least 500 µsec. This allows the
PLL to first frequency lock onto
the 106.25 MHz reference clock
provided at the REFCLK input.
The RX PLL/CLOCK RECOVERY
circuitry multiplies this reference
clock by 10 to generate an
internal 1062.5 MHz clock. After
500 µsec, the user should set
-LCKREF high. This will allow the
receiver to frequency and phase
lock the internal 1062.5 MHz
clock onto the incoming serial
data stream. Once locked, the
receiver will recover the two
53.125 MHz receiver byte clocks
(RBC1/RBC0). These byte clocks
are approximately 180° out of
phase with each other and are
alternately used to clock the
10-bit parallel output data.
INPUT SAMPLER
The INPUT SAMPLER is
responsible for converting the
serial input signal into a retimed
serial bit stream. In order to
accomplish this, it uses the high
speed serial clock recovered from
the RX PLL/CLOCK RECOVERY
block. This serial bit stream is
sent to the FRAME DEMUX and
BYTE SYNC block.
FRAME DEMUX AND BYTE
SYNC
The FRAME DEMUX AND BYTE
SYNC block is responsible for
restoring the 10-bit parallel data
from the high speed serial bit
stream. This block is also
responsible for recognizing the
comma character (or a K28.5
character) of positive disparity
(0011111xxx). When recognized,
the FRAME DEMUX AND BYTE
SYNC block works with the RX
PLL/CLOCK RECOVERY block to
properly align the receive byte
clocks to the parallel data. When
a comma character is detected
and realignment of the receiver
byte clocks (RBC1/RBC0) is
necessary, these clocks are
stretched, not slivered, to the
next possible correct alignment
position. These clocks will be
fully aligned by the start of the
second 4-byte ordered set. The
second comma character received
shall be aligned with the rising
edge of RBC1. Comma characters
should not be transmitted in
consecutive succession to allow
the receiver byte clocks to
maintain their proper recovered
frequencies.
OUTPUT DRIVERS
The OUTPUT DRIVERS present
the 10-bit parallel recovered data
byte properly aligned to the
receive byte clocks (RBC1/
RBC0), as shown in Figure 4.
These output data buffers provide
TTL compatible signals.
HDMP-1526 (Transmitter Section)
Timing Characteristics
TC = 0°C to +85°C, VCC = 4.5 V to 5.25 V
Symbol
Parameter
tsetup
Setup Time
thold
Hold Time
[1]
t_txlat
Transmitter Latency
Units
nsec
nsec
nsec
bits
Min.
2
1.5
Typ.
Max.
6.25
6.64
12.2
13.0
Note:
1. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered
by the rising edge of the transmit byte clock, REFCLK) and the transmission of the first serial bit of that parallel word (defined by the
rising edge of the first bit transmitted).
,
,,,,
,,
1.4 V
REFCLK
TX[0]-TX[9]
DATA
DATA
DATA
DATA
2.0 V
DATA
0.8 V
t-SETUP
t-HOLD
Figure 3. Transmitter Section Timing.
,,
,,
DATA BYTE A
± DOUT
T5
T6
T7
T8
T9
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T0
DATA BYTE B
T1
T2
T3
T4
T5
t_TXLAT
TX[0]-TX[9]
REFCLK
DATA BYTE B
DATA BYTE C
1.4 V
Figure 4. Transmitter Latency.
685
HDMP-1526 (Receiver Section)
Timing Characteristics
TC = 0°C to +85°C, VCC = 4.5 V to 5.25 V
Symbol
Parameter
[1,2]
b_sync
Bit Sync Time
[2]
f_lock
Frequency Lock Time
(from Time of Setting -LCKREF = 0)
f_lock_rate[2]
Frequency Lock Rate (when -LCKREF = 0)
tvalid_before
Time Data Valid Before Rising Edge of RBC
tvalid_after
Time Data Valid After Rising Edge of RBC
tduty
RBC Duty Cycle
tA-B[3]
Rising Edge Time Difference
[4]
t_rxlat
Receiver Latency
Units
bits
µsec
kHz/µsec
nsec
nsec
%
nsec
nsec
bits
Min.
Typ.
Max.
2500
500
200
5.8
3.3
3
1.5
40
8.9
60
9.9
33.9
36
9.4
25.0
26.6
Notes:
1. This is the recovery time for input phase jumps, per the FC-PH specification Ref 4.1, Sec 5.3.
2. Tested using CPLL = 0.01 µF.
3. The RBC clock skew is calculated as tA-B(max) - tA-B(min).
4. The receiver latency, as shown in Figure 5, is defined as the time between receiving the first serial bit of a parallel data word (as
defined as the first edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive
byte clock, either RBC1 or RBC0).
,
,
,,
,
,,
,,
,,
,,
t-VALID BEFORE
t-VALID AFTER
RBC1
1.4 V
2.0 V
RX[0]-RX[9]
K28.5
DATA
DATA
DATA
DATA
0.8 V
2.0 V
BYTSYNC
0.8 V
1.4 V
RBC0
Figure 5. Receiver Section.
DATA BYTE C
± DIN
R5
R6
R7
R8
DATA BYTE D
R9
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R2
R3
R4
R5
t_RXLAT
RX[0]-RX[9]
RBC1/0
Figure 6. Receiver Latency.
686
DATA BYTE A
DATA BYTE D
1.4 V
HDMP-1526 (TRx)
Absolute Maximum Ratings
TA = 25°C, except as specified. Operation in excess of any one of these conditions may result in permanent
damage to this device.
Symbol
VCC
VIN,TTL
VIN,HS_IN
IO,TTL
Tstg
Tj
Parameter
Units
V
V
V
mA
°C
°C
°C
Supply Voltage
TTL Input Voltage
HS_IN Input Voltage
TTL Output Source Current
Storage Temperature
Junction Operating Temperature
Maximum Assembly Temperature (for 10 seconds maximum)
Min.
-0.5
-0.7
2.0
-40
0
Max.
6.0
VCC + 0.7
VCC
13
+130
+130
+260
HDMP-1526 (TRx)
Recommended Operating Conditions
Symbol
Parameter
VCC
Supply Voltage
TC
Case Temperature
Units
V
°C
Min.
4.5
0
Max.
5.25
85
HDMP-1526 (TRx)
Transceiver Reference Clock Requirements
TC = 0°C to +85°C, VCC = 4.5 V to 5.25 V
Symbol
f
Ftol
Symm
Parameter
Nominal Frequency (for Fibre Channel Compliance)
Frequency Tolerance
Symmetry (Duty Cycle)
Unit
MHz
ppm
%
Min.
106.20
-100
40
Typ.
106.25
Max.
106.30
+100
60
HDMP-1526 (Trx)
DC Electrical Specifications
TC = 0°C to +85°C, VCC = 4.5 V to 5.25 V
Symbol
VIH,TTL
VIL,TTL
VOH,TTL
VOL,TTL
IIH,TTL
IIL-TTL
ICC,TRx[1,2]
Parameter
TTL Input High Voltage Level, Guaranteed High Signal
for All TTL Inputs
TTL Input Low Voltage Level, Guaranteed Low Signal for
All TTL Inputs
TTL Output High Voltage Level, IOH = -400 µA
TTL Output Low Voltage Level, IOL = 1 mA
Input High Current (Magnitude), VIN = VCC
Input Low Current (Magnitude), VIN = 0 Volts
Transceiver VCC Supply Current, TA = 25°C
Unit
V
Min.
2
Typ.
V
0
0.8
V
V
µA
µA
mA
2.4
0
VCC
0.6
40
600
475
0.004
295
375
Max.
VCC
Notes:
1. Measurement Conditions: Tested sending 1062.5 MBd PRBS 27-1 sequence with both DOUT outputs biased with 270 Ω resistors
and the receiver TTL outputs driving 10 pF loads.
2. Typical specified with VCC = 5.0 volts, maximum specified with VCC = 5.25 volts.
687
HDMP-1526 (TRx)
AC Electrical Specifications
TC = 0°C to +85°C, VCC = 4.5 V to 5.25 V
Symbol
Parameter
tr,TTLin
Input TTL Rise Time, 0.8 to 2.0 Volts
tf,TTLin
Input TTL Fall Time, 2.0 to 0.8 Volts
tr,TTLout
Output TTL Rise Time, 0.8 to 2.0 Volts, 10 pF Load
tf,TTLout
Output TTL Fall Time, 2.0 to 0.8 Volts, 10 pF Load
[1,2]
trs,HS_OUT
HS_OUT Single-Ended (+DOUT) Rise Time
tfs,HS_OUT[1,2]
HS_OUT Single-Ended (+DOUT) Fall Time
[1,2,3]
trd,HS_OUT
HS_OUT Differential Rise Time
tfd,HS_OUT[1,2,3]
HS_OUT Differential Fall Time
[3,4]
VIP,HS_IN
HS_IN Input Peak-to-Peak Differential Voltage
VOP,HS_OUT[1,3]
HS_OUT Output Peak-to-Peak Differential Voltage
Units
nsec
nsec
nsec
nsec
psec
psec
psec
psec
mV
mV
Notes:
1. Each output is measured with a 270 Ω bias resistor to ground and a 50 Ω AC load.
2. Specified between 20% and 80% points of full voltage swing.
3. Output Peak-to-Peak Differential Voltage specified as DOUT+ minus DOUT-.
4. Measured using a 50 Ω load.
TIME BASE UNITS
TIME BIT PERIOD
BIT RATE
1.06250 0BITS/s
FC1063
SCALE
2.000 BIT
POSITION
218.01994 BIT
REFERENCE
LEFT CENTER
t
188.2 ps/div
f1 250 mU/div
205.1952 ns
TIME BASE WINDOWING...
a. Differential HS_OUT Output (Dout+ Minus Dout-).
TIME BASE UNITS
X1
TIME BIT PERIOD
BIT RATE
1.06250 0BITS/s
FC1063
SCALE
2.000 BIT
POSITION
218.68931 BIT
REFERENCE
LEFT CENTER
X2
t
100.2 ps/div
f1 150 mU/div
205.0252 ns
b. Single-Ended HS_OUT Output (Dout+).
Figure 7. Transmitter DOUT Eye Diagrams.
688
TIME BASE WINDOWING...
Min.
200
1200
Typ.
2
2
1.1
1.5
190
170
180
230
1200
1740
Max.
2.4
2.4
400
400
2200
2200
HDMP-1526 (Transmitter Section)
Output Jitter Characteristics
TC = 0°C to +85°C, VCC = 4.5 V to 5.25 V
Symbol
Parameter
RJ[1]
Random Jitter at DOUT, the High Speed Electrical Data Port, specified as
1 sigma deviation of the 50% crossing point
[1]
DJ
Deterministic Jitter at DOUT, the High Speed Electrical Data Port
Units
ps
Typ.
8
ps
35
Note:
1. Defined by Fibre Channel Specification Rev 4.1, Annex A, Section A.4 and tested using measurement method shown in Figure 8.
HP70841B
PATTERN
GENERATOR*
HP70311A
CLOCK SOURCE
HP70841B
PATTERN
GENERATOR*
HP83480A
OSCILLOSCOPE
+K28.5, -K28.5
0000011111
+ DATA
- DATA 106.25 MHz
1.0625 GHz
CH1
1.0625 GHz
+DOUT
HP83480A
OSCILLOSCOPE
CH2
HP70311A
CLOCK SOURCE
BIAS
TEE
+ DATA
- DATA
TRIGGER
-DOUT
DIVIDE
BY 10
CIRCUIT
(DUAL
OUTPUT)
DIVIDE
BY 2
CIRCUIT
TRIGGER
CH1
CH2
HDMP-1526
REFCLK LOOPEN
Tx[0..9]
* PATTERN
GENERATOR
PROVIDES A
DIVIDE BY
10 FUNCTION.
1.4 V
0011111000
(STATIC K28.7)
+DOUT
VARIABLE
DELAY
-DOUT
HDMP-1526
106.25 MHz
ENBYTSYNC
LOOPEN
REFCLK
Tx[0..9]
a. Block Diagram of RJ Measurement Method.
-DIN
+DIN
Rx[0..9]
b. Block Diagram of DJ Measurement Method.
Figure 8. Transmitter Jitter Measurement Method.
HDMP-1526 (TRx)
Thermal and Power Temperature Characteristics,
TC = 0°C to +85°C, VCC = 4.5 V to 5.25 V
Symbol
Parameter
[1,2]
PD,TRx
Transceiver Power Dissipation, Outputs Open, Parallel Data
has 5 Ones and 5 Zeroes
PD,TRx[1,2,3]
Transceiver Power Dissipation, Outputs Connected per
Recommended Bias Terminations
[4]
Θjc
Thermal Resistance, Junction to Case
Units
Watt
Typ.
1.6
Max.
Watt
1.8
2.4
°C/Watt
7
Notes:
1. PD is calculated by multiplying the max VCC by the max ICC and subtracting the power dissipated outside the chip at the high speed
bias resistors.
2. Typical specified with VCC = 5 volts, maximum specified with VCC = 5.25 volts.
3. Specified with high speed outputs biased with 270 Ω resistors and receiver TTL outputs driving 10 pF loads. Pattern is PRBS 27-1.
4. Based on independant package testing by HP.
689
I/O Type Definitions
I/O Type
I-TTL
O-TTL
HS_OUT
HS_IN
C
S
Definition
Input TTL. Floats High When Left Open.
Output TTL
High Speed Output. ECL Compatible
High Speed Input, Internally Biased, High Input Resistance
External Circuit Node
Power Supply or Ground
HDMP-1526 (TRx)
Pin Input Capacitance
Symbol
CINPUT
Parameter
Pin Input Capacitance
Units
pF
O_TTL
Typ.
1.6
Max.
4.0
I_TTL
VCC_TTL
VCC_TTL
800
VCC_TX
or
VCC_RX
72
10 k
10 k
36
6k
VBB 1.4 V
GND
GND_TTL
ESD
PROTECTION
ESD
PROTECTION
GND_TTL
Figure 9. O-TTL and I-TTL Simplified Circuit Schematic.
HS_OUT
HS_IN
VCC_RXHS
VCC_TXHS
VCC_TXECL
2V +
–
+ 2V
–
3.2 K
VCC_TX
VCC_RX
3.2 K
+DOUT
75
Zo = 75 Ω
0.01 µF
+DIN
75
0.01 µF
270
75
-DOUT
75
Zo = 75 Ω
-DIN
0.01 µF
60 µA
60 µA
GND
ESD
PROTECTION
GND
ESD
270
PROTECTION
GND_TXHS
GND_RXHS
Figure 10. HS_OUT and HS_IN Simplified Circuit Schematic.
Notes:
1. HS_IN inputs should never be connected to ground as permanent damage to the device may result.
2. 75 Ω serial padding resistors are optional, the serial resistors should be matched to the receiver input bias resistors.
690
RXCAP1
VCC_RXA
-DIN
GND_RXA
VCC_RXHS
VCC_RXHS
+DIN
GND
VCC_RX
GND_RXHS
VCC_TXHS
+DOUT
-DOUT
VCC_TXECL
VCC_TX
GND_TXHS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
GND_TXTTL
1
48
TX[0]
TX[1]
2
3
47
RXCAP0
BYTSYNC
46
GND_RXTTL
TX[2]
4
RX[0]
VCC_TXTTL
TX[3]
5
6
45
44
43
TX[4]
TX[5]
7
42
VCC_RXTTL
8
9
41
40
RX[3]
RX[4]
RX[5]
TX[6]
VCC_TXTTL
TX[7]
TX[8]
TX[9]
GND_TXTTL
GND_TXA
TXCAP1
10
11
12
HDMP-1526
xxxx YYWW
hp
39
38
COUNTRY
13
14
15
RX[2]
RX[6]
37
VCC_RXTTL
36
35
RX[7]
RX[8]
RX[9]
34
33
16
RX[1]
GND_RXTTL
RBC0
GND_RXTTL
VCC_RX
VCC_RXTTL
RBC1
N/C
-LCKREF
VCC_RX
ENBYTSYNC
GND
TXCAP0
VCC_TXA
LOOPEN
VCC_TX
GND
REFCLK
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
xxxx = WAFER LOT NUMBER
YYWW = DATE CODE (YY = YEAR, WW = WORK WEEK)
COUNTRY = COUNTRY OF MANUFACTURE
Figure 11. HDMP-1526 (TRx) Package Layout and Marking, Top View.
691
TRx I/O Definition
Name
GND_TXTTL
GND_TXA
Pin
1
14
2
3
4
6
7
8
9
11
12
13
5
10
15
TXCAP1
TXCAP0
VCC_TXA
16
17
18
C
LOOPEN
19
I-TTL
VCC_TX
20
59
S
GND
21
25
58
22
S
TX[0]
TX[1]
TX[2]
TX[3]
TX[4]
TX[5]
TX[6]
TX[7]
TX[8]
TX[9]
VCC_TXTTL
REFCLK
VCC_RX
Type
S
I-TTL
S
S
S
I-TTL
ENBYTSYNC
23
28
57
24
I-TTL
-LCKREF
27
I-TTL
692
S
Signal
TTL Transmitter Ground: Normally 0 volts. Used for the TTL input cells
of the transmitter section.
Data Inputs: One, 10 bit, pre-encoded data byte. TX[0] is the first bit
transmitted. TX[0] is the least significant bit.
TTL Power Supply: Normally 5 volts. Used for all TTL transmitter input
buffer cells.
Analog Ground: Normally 0 volts. Used to provide a clean ground plane
for the PLL and high-speed analog cells.
Loop Filter Capacitor: A loop filter capacitor must be connected across
the TXCAP1 and TXCAP0 pins (typical value = 0.01 µF).
Analog Power Supply: Normally 5 volts. Used to provide a clean supply
line for the PLL and high-speed analog cells.
Loopback Enable Input: When set high, the high-speed serial signal is
internally wrapped from the transmitter’s serial loopback outputs back
to the receiver’s loopback inputs. Also, when in loopback mode, the
± DOUT outputs are held static. When set low, ± DOUT outputs and
± DIN inputs are active.
Logic Power Supply: Normally 5 volts. Used for internal transmitter
PECL logic. It should be isolated from the noisy TTL supply as well as
possible.
Logic Ground: Normally 0 volts. This ground is used for internal PECL
logic. It should be isolated from the noisy TTL ground as well as possible.
Reference Clock and Transmit Byte Clock: A 106.25 MHz clock supplied
by the host system. The transmitter section accepts this signal as the
frequency reference clock. It is multiplied by 10 to generate the serial bit
clock and other internal clocks. The transmit side also uses this clock as
the transmit byte clock for the incoming parallel data TX[0]..TX[9]. It
also serves as the reference clock for the receive portion of the
transceiver. When -LCKREF is activated, the receiver PLL frequency
locks to this reference signal.
Logic Power Supply: Normally 5 volts. Used for internal receiver PECL
logic. It should be isolated from the noisy TTL supply as well as possible.
Enable Byte Sync Input: When high, enables the internal byte sync
function to allow clock synchronization to a comma character (or a
K28.5 character) of positive disparity (0011111010). When the line is
low, the function is disabled and will not reset registers and clocks, or
strobe the BYTSYNC line.
Lock to Reference: When low, causes the PLL to acquire frequency lock
on the external reference, supplied at REFCLK.
TRx I/O Definition (cont’d.)
Name
VCC_RXTTL
RBC1
RBC0
GND_RXTTL
Pin
29
37
42
30
31
RX[0]
RX[1]
RX[2]
RX[3]
RX[4]
RX[5]
RX[6]
RX[7]
RX[8]
RX[9]
BYTSYNC
32
33
46
45
44
43
41
40
39
38
36
35
34
47
RXCAP0
RXCAP1
48
49
VCC_RXA
50
GND_RXA
51
-DIN
+DIN
VCC_RXHS
52
54
53
55
GND_RXHS
VCC_TXECL
56
60
VCC_TXHS
63
-DOUT
+DOUT
61
62
GND_TXHS
64
Type
S
Signal
TTL Power Supply: Normally 5 volts. Used for all TTL receiver output
buffer cells.
O-TTL
Receiver Byte Clocks: The receiver section recovers two 53.125 MHz
receive byte clocks. These two clocks are approximately 180 degrees out
of phase. The receiver parallel data outputs are alternatively clocked on
the rising edge of these clocks. RBC1 aligns and outputs the comma
character (for byte alignment) when detected.
TTL Receiver Ground: Normally 0 volts. Used for the TTL output cells
of the receiver section.
S
O-TTL
Data Outputs: One 10 bit data byte. RX[0] is the first bit received.
RX[0] is the least significant bit.
O-TTL
Byte Sync Output: An active high output. Used to indicate detection of
either a comma character or a K28.5 special character of positive
disparity. It is only active when ENBYTSYNC is enabled.
C
Loop Filter Capacitor: A loop filter capacitor for the internal PLL is
connected across the RXCAP0 and RXCAP1 pins.
(typical value = 0.01 µF).
S
Analog Power Supply: Normally 5 volts. Used to provide a clean supply
line for the PLL and high-speed analog cells.
S
Analog Ground: Normally 0 volts. Used to provide a clean ground
plane for the receiver PLL and high-speed analog cells.
HS_IN Serial Data Inputs: High-speed inputs. Serial data is accepted from the
± DIN inputs when LOOPEN is low.
S
High-Speed Supply: Normally 5 volts. Used only for the high-speed
receiver cell (HS_IN). Noise on this line should be minimized for best
operation.
S
Ground: Normally 0 volts.
S
High-Speed ECL Supply: Normally 5 volts. Used only for the last stage
of the high-speed transmitter output cell (HS_OUT) as shown in
Figure 9. Due to high current transitions, this VCC should be well
bypassed to a ground plane.
S
High-Speed Supply: Normally 5 volts. Used by the transmitter side
for the high-speed circuitry. Noise on this line should be minimized
for best operation.
HS_OUT Serial Data Outputs: High-speed outputs. These lines are active when
LOOPEN is set low. When LOOPEN is set high, these outputs are held
static.
S
Ground: Normally 0 volts.
693
VCC
VCC
VCC
Transceiver Power
Supply Bypass and Loop
Filter Capacitors
Transceiver Package
Information
The HDMP-1526 is constructed
of a single integrated circuit
packaged in a 14x14 mm
EDQuad package. This package
was designed to provide
enhanced power dissipation, thus
allowing for smaller package
dimensions. The package
conforms to the industry standard
JEDEC land pattern for 14x14
mm devices. As shown in Figure
12, the die is attached to a
copper heatsink using thermally
conductive epoxy. This allows for
694
VCC
VCC
VCC_RXA
RXCAP1
GND_RXA
VCC_RXHS
VCC_RXHS
GND_RXHS
GND
VCC_RX
VCC_TXECL
VCC_TX
GND_TXTTL
VCC_TXHS
GND_TXHS
CPLLR
RXCAP0
GND_RXTTL
VCC_TXTTL
VCC_RXTTL
VCC
VCC_RXTTL
VCC
GND
VCC_RX
TXCAP0
VCC_TXA
GND
VCC_TXTTL
GND_TXTTL
GND_TXA
GND_RXTTL
VCC
VCC_RX
VCC_RXTTL
TOP VIEW
TXCAP0
VCC_TX
Bypass capacitors should be
liberally used and placed as close
as possible to the appropriate
power supply pins of the HDMP1526 as shown on the schematic
of Figure 11. All bypass chip
capacitors are 0.1 µF. The
VCC_RXA and VCC_TXA pins are
the analog power supply pins for
the PLL sections. The voltage into
these pins should be clean with
minimum noise. The PLL loop
filter capacitors and their pin
locations are also shown on
Figure 11. Notice that only two
capacitors are required: CPLLT for
the transmitter and CPLLR for the
receiver. Nominal capacitance is
0.01 µF. The voltage across the
capacitors is on the order of 1
volt, so the capacitor can be a
low voltage type and physically
small. The PLL capacitors are
placed physically close to the
appropriate pins on the HDMP1526. Keeping the lines short will
prevent them from picking up
stray noise from surrounding
lines or components.
VCC*
GND_RXTTL
CPLLT
VCC*
VCC
VCC
VCC
* SUPPLY VOLTAGE INTO VCC_RXA AND VCC_TXA SHOULD
BE FROM A LOW NOISE SOURCE. ALL BYPASS CAPACITORS
ARE 0.1 µF. THE PLL FILTER CAPACITORS ARE 0.01 µF.
Figure 12. Power Supply Bypass.
the power dissipated by the IC to
be directly connected to the
ambient environment, thereby
minimizing the Θjc of the device.
COPPER HEATSINK
NICKEL PLATING
CERAMIC
LEAD
WIRE BOND
DIE
Figure 13. Package Cross Section of HDMP-1526.
EDQuad Package Information
Item
Package Material
Lead Finish Material
Lead Finish Thickness
Lead Coplanarity
Details
Plastic (with copper heat slug)
85% Tin, 15% Lead
300-800 µm
0.10 mm max
Mechanical Dimensions
PIN #1 ID
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
3
4
5
6
7
8
9
HDMP-1526
48
47
46
45
44
43
42
41
40
TOP VIEW
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
17.20
± 0.25
14.00
± 0.10
0.17 MAX.
0.35
± 0.05
0.25
0.80 BASIC
14.00 ± 0.10
0.88 ± 0.15
17.20 ± 0.25
2.00 ± 0.10
2.35 MAX.
0.25 MAX.
ALL DIMENSIONS ARE IN MILLIMETERS.
Figure 14. Mechanical Dimensions of HDMP-1526.
Assembly Handling
Information
Caution: Parts must be kept in
dry pack, or baked out before IR
reflow. Refer to package moisture
label for more details.
695