ETC HDMP

Fibre Channel Transceiver Chip
Technical Data
HDMP-1536A Transceiver
HDMP-1546A Transceiver
Features
• ANSI X3.230-1994 Fibre
Channel Compatible (FC-0)
• Supports Full Speed
(1062.5 MBd) Fibre Channel
• Compatible with “Fibre
Channel 10-Bit Interface”
Specification
• Low Power Consumption,
630 mW
• Transmitter and Receiver
Functions Incorporated onto
a Single IC
• Auto Frequency Lock
• Small Package Profile
HDMP-1536A, 10x10 mm
QFP
HDMP-1546A, 14x14 mm
QFP
• 10-Bit Wide Parallel TTL
Compatible I/Os
• Single +3.3 V Power Supply
• 5 Volt Tolerant I/Os
• 2 kV ESD Protection on All Pins
• High Speed Proprietary
Interface
• High Speed Backplane
Interface
Description
The HDMP-1536/46A transceiver
is a single silicon bipolar
integrated circuit packaged in a
plastic QFP package. It provides
a low-cost, low-power physical
layer solution for 1062.5 MBd
Fibre Channel or proprietary link
interfaces. It provides complete
FC-0 functionality for copper
transmission, incorporating both
the Fibre Channel FC-0 transmit
and receive functions into a
single device.
Applications
This chip is used to build a highspeed interface (as shown in
Figure 1) while minimizing board
space, power, and cost. It is
compatible with both the ANSI
X3.230-1994/AM 1 - 1996
document and the “Fibre Channel
10-bit Interface” specification.
• 1062.5 MBd Fibre Channel
Interface
• FC Interface for Disk Drives
and Arrays
• Mass Storage System I/O
Channel
• Work Station/Server I/O
Channel
The transmitter section accepts
10-bit wide parallel TTL data and
multiplexes this data into a highspeed serial data stream. The
parallel data is expected to be
8B/10B encoded data, or
equivalent. This parallel data is
latched into the input register of
the transmitter section on the
rising edge of the 106.25 MHz
reference clock (used as the
transmit byte clock).
The transmitter section’s PLL
locks to this user supplied 106.25
MHz byte clock. This clock is
then multiplied by 10, to generate
the 1062.5 MHz serial signal
clock used to generate the highspeed output. The high-speed
outputs are capable of interfacing
directly to copper cables for
electrical transmission or to a
separate fiber-optic module for
optical transmission.
The receiver section accepts a
serial electrical data stream at
1062.5 MBd and recovers the
original 10-bit wide parallel data.
The receiver PLL locks onto the
incoming serial signal and
2
HDMP-15x6A
TRANSMITTER SECTION
SERIAL DATA OUT
PLL
PROTOCOL DEVICE
RBC0
RBC1
PLL
SERIAL DATA IN
RECEIVER SECTION
BYTSYNC
REFCLK
ENBYTSYNC
DATA BYTE
TX[0-9]
INPUT
LATCH
Figure 1. Typical Application Using the HDMP-15x6A.
FRAME
MUX
OUTPUT
SELECT
INTERNAL
LOOPBACK
TXCAP0
TXCAP1
TX
PLL/CLOCK
GENERATOR
INTERNAL
TX CLOCKS
REFCLK
RXCAP0
RXCAP1
RBC0
RBC1
OUTPUT
DRIVER
DATA BYTE
RX[0-9]
RX
PLL/CLOCK
RECOVERY
FRAME
DEMUX
AND
BYTE SYNC
BYTSYNC
ENBYTSYNC
Figure 2. HDMP-15x6A Transceiver Block Diagram.
INTERNAL
RX CLOCKS
INPUT
SAMPLER
± DOUT
LOOPEN
INPUT
SELECT
± DIN
SIGNAL
DETECT
SIG_DET
3
recovers the high-speed serial
clock and data. The serial data is
converted back into 10-bit
parallel data, recognizing the
8B/10B comma character to
establish byte alignment.
• Parallel to Serial Converter
• Comma Character Recognition
Circuitry
• Byte Alignment Circuitry
• Serial to Parallel Converter
OUTPUT SELECT
The OUTPUT SELECT block
provides for an optional internal
loopback of the high speed serial
signal, for testing purposes.
The recovered parallel data is
presented to the user at TTL
compatible outputs. The receiver
section also recovers two
53.125 MHz receiver byte clocks
that are 180 degrees out of phase
with each other. The parallel data
is properly aligned with the rising
edge of alternating clocks.
INPUT LATCH
The transmitter accepts 10-bit
wide TTL parallel data at inputs
TX[0..9]. The user-provided
reference clock signal, REFCLK,
is also used as the transmit byte
clock. The TX[0..9] and REFCLK
signals must be properly aligned,
as shown in Figure 3.
In normal operation, LOOPEN is
set low and the serial data stream
is placed at ± DOUT. When wrapmode is activated by setting
LOOPEN high, the ± DOUT pins
are held static at logic 1 and the
serial output signal is internally
wrapped to the INPUT SELECT
box of the receiver section.
For test purposes, the transceiver
provides for on-chip local loopback functionality controlled
through an external input pin.
Additionally, the byte synchronization feature may be disabled. This
may be useful in proprietary applications which use alternative
methods to align the parallel data.
HDMP-1536/46A Block
Diagram
The HDMP-1536/46A was
designed to transmit and receive
10-bit wide parallel data over a
single high-speed line, as
specified for the FC-0 layer of the
Fibre Channel standard. The
parallel data applied to the
transmitter is expected to be
encoded per the Fibre Channel
specification, which uses an
8B/10B encoding scheme with
special reserve characters for link
management purposes. In order
to accomplish this task, the
HDMP-1536/46A incorporates
the following:
• TTL Parallel I/Os
• High Speed Phase Lock Loops
• High Speed Serial Clock and
Data Recovery Circuitry
TX PLL/CLOCK GENERATOR
The transmitter Phase Lock Loop
and Clock Generator (TX PLL/
CLOCK GENERATOR) block is
responsible for generating all
internal clocks needed by the
transmitter section to perform its
functions. These clocks are based
on the supplied reference byte
clock (REFCLK). REFCLK is used
as both the frequency reference
clock for the PLL and the transmit byte clock for the incoming
data latches. It is expected to be
106.25 MHz and properly aligned
to the incoming parallel data (see
Figure 3). This clock is multiplied
by 10 to generate the 1062.5
MHz clock necessary for the high
speed serial outputs.
FRAME MUX
The FRAME MUX accepts the 10bit wide parallel data from the
INPUT LATCH. Using internally
generated high speed clocks, this
parallel data is multiplexed into
the 1062.5 MBd serial data
stream. The data bits are transmitted sequentially, from the
least significant bit (TX[0]) to the
most significant bit (TX[9]).
INPUT SELECT
The INPUT SELECT block determines whether the signal at ± DIN
or the internal loop-back serial
signal is used. In normal operation, LOOPEN is set low and the
serial data is accepted at ± DIN.
When LOOPEN is set high, the
high-speed serial signal is
internally looped-back from the
transmitter section to the receiver
section. This feature allows for
loop-back testing exclusive of the
transmission medium.
RX PLL/CLOCK RECOVERY
The RX PLL/CLOCK RECOVERY
block is responsible for frequency
and phase locking onto the incoming serial data stream and recovering the bit and byte clocks. An
automatic locking feature allows
the Rx PLL to lock onto the input
data stream without external
PLL training controls. It does
this by continually frequency
locking onto the 106.25 MHz
clock, and then phase locking
onto the input data stream. An
internal signal detection circuit
monitors the presence of the
input, and invokes the phase
detection as the data stream
appears. Once bit locked, the
receiver generates the high speed
4
sampling clock at 1062.5 MHz
for the input sampler, and
recovers the two 53.125 MHz
receiver byte clocks
(RBC1/RBC0). These clocks are
180 degrees out of phase with
each other, and are alternately
used to clock the
10-bit parallel output data.
INPUT SAMPLER
The INPUT SAMPLER is
responsible for converting the
serial input signal into a re-timed
serial bit stream. In order to
accomplish this, it uses the high
speed serial clock recovered from
the RX PLL/CLOCK RECOVERY
block. This serial bit stream is
sent to the FRAME DEMUX and
BYTE SYNC block.
FRAME DEMUX AND BYTE
SYNC
The FRAME DEMUX AND BYTE
SYNC block is responsible for
restoring the 10-bit parallel data
from the high speed serial bit
stream. This block is also
responsible for recognizing the
comma character (or a K28.5
character) of positive disparity
(0011111xxx). When recognized,
the FRAME DEMUX AND BYTE
SYNC block works with the RX
PLL/CLOCK RECOVERY block to
properly align the receive byte
clocks to the parallel data. When
a comma character is detected
and realignment of the receiver
byte clocks (RBC1/RBC0) is
necessary, these clocks are
stretched, not slivered, to the
next possible correct alignment
position. These clocks will be
fully aligned by the start of the
second 4-byte ordered set. The
second comma character received
shall be aligned with
the rising edge of RBC1. As per
the 8B/10B encoding scheme,
comma characters should not be
transmitted in consecutive bytes
to allow the receiver byte clocks
to maintain their proper
recovered frequencies.
OUTPUT DRIVERS
The OUTPUT DRIVERS present
the 10-bit parallel recovered data
byte properly aligned to the
receiver byte clocks (RBC1/RBC0),
as shown in Figure 5. These
output data buffers provide TTL
compatible signals.
SIGNAL DETECT
The SIGNAL DETECT block
examines the differential
amplitude of the inputs ± DIN.
When this input signal is too
small, it outputs a logic 0 at
SIG_DET (refer to SIG_DET
pin definition for detection
thresholds), and at the same
time, forces the parallel output
RX[0]..RX[9] to all logic one
(1111111111). The main
purpose of this circuit is to
prevent the generation of random
data when the serial input lines
are disconnected. When the
signal at ± DIN is of a valid
amplitude, SIG_DET is set to
logic 1, and the output of the
INPUT SELECT block is passed
through.
5
HDMP-1536/46A (Transmitter Section)
Timing Characteristics
TA[1] = 0°C to +70°C, VCC = 3.15 V to 3.45 V
Symbol
Parameter
tsetup
Setup Time
thold
Hold Time
t_txlat[2]
Transmitter Latency
Units
nsec
nsec
nsec
bits
Min.
2
1.5
Typ.
Max.
3.5
4.4
Notes:
1. Device tested and characterized under TA conditions specified, with TC monitored at approximately 20° higher than TA.
2. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered
by the rising edge of the transmit byte clock, REFCLK) and the transmission of the first serial bit of that parallel word (defined by
the rising edge of the first bit transmitted).
1.4 V
REFCLK
2.0 V
TX[0]-TX[9]
DATA
DATA
DATA
DATA
DATA
0.8 V
tsetup
thold
Figure 3. Transmitter Section Timing.
DATA BYTE A
± DOUT
T5
T6
T7
T8
T9
T0
T1
T2
T3
T4
T5
DATA BYTE B
T6
T7
T8
T9
T0
T1
T2
T3
T4
T5
t_txlat
TX[0]-TX[9]
REFCLK
Figure 4. Transmitter Latency.
DATA BYTE B
DATA BYTE C
1.4 V
6
HDMP-1536/46A (Receiver Section)
Timing Characteristics
TA[1] = 0°C to +70°C, VCC = 3.15 V to 3.45 V
Symbol
Parameter
[2,3]
b_sync
Bit Sync Time
tvalid_before
Time Data Valid Before Rising Edge of RBC
tvalid_after
Time Data Valid After Rising Edge of RBC
tduty
RBC Duty Cycle
[4]
tA-B
Rising Edge Time Difference between
RBC0 and RBC1.
t_rxlat[5]
Receiver Latency
Units
bits
nsec
nsec
%
nsec
Min.
Typ.
3
1.5
40
8.9
Max.
2500
60
9.9
9.4
nsec
bits
24.5
26
Notes:
1. Device tested and characterized under TA conditions specified, with TC monitored at approximately 20° higher than TA.
2. This is the recovery time for input phase jumps, per the FC-PH specification Ref 4.1, Sec 5.3.
3. Tested using CPLL = 0.1 µF.
4. The RBC clock skew is calculated as t A-B(max) - tA-B(min).
5. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word
(defined as the first edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive
byte clock, either RBC1 or RBC0).
tvalid_before
tvalid_after
RBC1
1.4 V
2.0 V
RX[0]-RX[9]
K28.5
DATA
DATA
DATA
DATA
0.8 V
2.0 V
BYTSYNC
0.8 V
1.4 V
RBC0
tA-B
Figure 5. Receiver Section Timing.
DATA BYTE C
± DIN
R5
R6
R7
R8
DATA BYTE D
R9
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R2
R3
R4
R5
t_rxlat
RX[0]-RX[9]
RBC1/0
Figure 6. Receiver Latency.
DATA BYTE A
DATA BYTE D
1.4 V
7
Absolute Maximum Ratings
TA = 25°C, except as specified. Operation in excess of any one of these conditions may result in permanent
damage to this device.
Symbol
VCC
VIN,TTL
VIN,HS_IN
IO,TTL
Tstg
Tj
Parameter
Supply Voltage
TTL Input Voltage
HS_IN Input Voltage
TTL Output Source Current
Storage Temperature
Junction Operating Temperature
Units
V
V
V
mA
°C
°C
Min.
-0.5
-0.7
2.0
-65
0
Max.
5.0
VCC + 2.8
VCC
13
+150
+150
Guaranteed Operating Rates
TA [1] = 0°C to +70°C, VCC = 3.15 V to 3.45 V
Parallel Clock Rate (MHz)
Serial Baud Rate (MBaud)
Min.
Max.
Min.
Max.
106.20
106.30
1062.0
1063.0
Note:
1. Device tested and characterized under TA conditions specified, with TC monitored at
approximately 20° higher than TA.
Transceiver Reference Clock Requirements
TA[1] = 0°C to +70°C, VCC = 3.15 V to 3.45 V
Symbol
Parameter
f
Nominal Frequency (for Fibre Channel Compliance)
Ftol
Frequency Tolerance
Symm
Symmetry (Duty Cycle)
Unit
MHz
ppm
%
Min.
106.20
-100
40
Typ.
106.25
Max.
106.30
+100
60
Note:
1. Device tested and characterized under TA conditions specified, with TC monitored at approximately 20° higher than TA.
DC Electrical Specifications
TA[1] = 0°C to +70°C, VCC = 3.15 V to 3.45 V
Symbol
Parameter
VIH,TTL
TTL Input High Voltage Level, Guaranteed High Signal
for All Inputs
VIL,TTL
TTL Input Low Voltage Level, Guaranteed Low Signal for
All Inputs
VOH,TTL
TTL Output High Voltage Level, IOH = -400 µA
VOL,TTL
TTL Output Low Voltage Level, IOL = 1 mA
IIH,TTL
Input High Current (Magnitude), VIN = 2.4 V, VCC = max
IIL-TTL
Input Low Current (Magnitude), VIN = 0.4 V, VCC = max
ICC,TRx[2,3] Transceiver VCC Supply Current, TA = 25°C
Unit
V
Min.
2
Typ.
Max.
VCC
V
0
0.8
V
V
µA
µA
mA
2.2
0
VCC
0.6
40
-600
205
Notes:
1. Device tested and characterized under TA conditions specified, with TC monitored at approximately 20° higher than TA.
2. Measurement Conditions: Tested sending 1062.5 MBd PRBS 27-1 sequence from a serial BERT with ± DOUT outputs biased with
150 Ω resistors.
3. Typical specified with VCC = 3.3 volts, maximum specified with VCC = 3.45 volts.
8
AC Electrical Specifications
TA[1] = 0°C to +70°C, VCC = 3.15 V to 3.45 V
Symbol
Parameter
tr,REFCLK
REFCLK Rise Time, 0.8 to 2.0 volts
tf,REFCLK
REFCLK Fall Time, 2.0 to 0.8 volts
tr,TTLin
Input TTL Rise Time, 0.8 to 2.0 Volts
tf,TTLin
Input TTL Fall Time, 2.0 to 0.8 Volts
tr,TTLout
Output TTL Rise Time, 0.8 to 2.0 Volts, 10 pF Load
tf,TTLout
Output TTL Fall Time, 2.0 to 0.8 Volts, 10 pF Load
trs,HS_OUT
HS_OUT Single-Ended (+DOUT) Rise Time
tfs,HS_OUT
HS_OUT Single-Ended (+DOUT) Fall Time
trd,HS_OUT
HS_OUT Differential Rise Time
tfd,HS_OUT
HS_OUT Differential Fall Time
VIP,HS_IN
HS_IN Input Peak-to-Peak Differential Voltage
VOP,HS_OUT[2]
HS_OUT Output Peak-to-Peak Differential Voltage
Units
nsec
nsec
nsec
nsec
nsec
nsec
psec
psec
psec
psec
mV
mV
Min.
0.7
0.7
200
1200
Typ.
2
2
1.5
1.1
225
200
225
200
1200
1600
Notes:
1. Device tested and characterized under TA conditions specified, with TC monitored at approximately 20° higher than TA.
2. Output Peak-to-Peak Differential Voltage specified as DOUT+ minus DOUT-.
200.0 ps/div
22.0680 ns
Yaxis = 400 mV/DIV
a. Differential HS_OUT Output (Dout+ Minus Dout-).
200.0 ps/div
22.0680 ns
Yaxis = 200 mV/DIV
b. Single-Ended HS_OUT Output (Dout+).
Eye Diagrams of the High-Speed Serial Outputs from the HDMP-1536/46A
as Captured on the HP 83480A Digital Communications Analyzer. Tested with PRBS = 27-1.
Figure 7. Transmitter DOUT Eye Diagrams.
Max.
2.4
2.4
2.4
2.4
375
375
2000
2200
9
Output Jitter Characteristics
T A = 0° to +70°C, V CC = 3.15 V to 3.45 V
Symbol
Parameter
[1]
RJ
Random Jitter at DOUT, the High Speed Electrical Data Port, specified as
1 sigma deviation of the 50% crossing point (RMS)
DJ[1]
Deterministic Jitter at DOUT, the High Speed Electrical Data Port (pk-pk)
Units
ps
Typ.
8
ps
15
Note:
1. Defined by Fibre Channel Specification Rev 4.1, Annex A, Section A.4 and tested using measurement method shown in Figure 8.
HP70841B
PATTERN
GENERATOR*
HP70311A
CLOCK SOURCE
+K28.5, -K28.5
HP70841B
PATTERN
GENERATOR*
HP83480A
OSCILLOSCOPE
+ DATA
- DATA
1.0625 GHz
0000011111
+ DATA
- DATA 106.25 MHz
CH1
1.0625 GHz
HP83480A
OSCILLOSCOPE
TRIGGER
CH2
HP70311A
CLOCK SOURCE
+DOUT
BIAS
TEE
DIVIDE
BY 2
CIRCUIT
TRIGGER
CH1
+DOUT
HDMP-1536A
Tx[0..9]
VARIABLE
DELAY
TTL
-DOUT
HDMP-1536A
106.25 MHz
REFCLK
Tx[0..9]
1.4 V
CH2
-DOUT
REFCLK LOOPEN
* PATTERN
GENERATOR
PROVIDES A
DIVIDE BY
10 FUNCTION.
DIVIDE
BY 10
CIRCUIT
(DUAL
OUTPUT)
-DIN
+DIN
ENBYTSYNC
LOOPEN
Rx[0..9]
0011111000
(STATIC K28.7)
a. Block Diagram of RJ Measurement Method.
b. Block Diagram of DJ Measurement Method.
Figure 8. Transmitter Jitter Measurement Method.
Thermal and Power Temperature Characteristics,
TA[1] = 0°C to +70°C, VCC = 3.15 V to 3.45 V
Symbol
Parameter
[2,3]
PD,TRx
Transceiver Power Dissipation, Outputs Open, Parallel Data
has 5 Ones and 5 Zeroes
PD,TRx[2,3,4]
Transceiver Power Dissipation, Outputs Connected per
Recommended Bias Terminations with Idle Pattern
[5]
Θjc
Thermal Resistance, Junction to Case
HDMP-1536A
HDMP-1546A
Units
mW
Typ.
630
Max.
850
mW
675
900
°C/Watt
11
8
Notes:
1. Device tested and characterized under TA conditions specified, with TC monitored at approximately 20° higher than TA.
2. PD is obtained by multiplying the max VCC by the max ICC and subtracting the power dissipated outside the chip at the high speed
bias resistors.
3. Typical value specified with VCC = 3.3 volts, maximum value specified with VCC = 3.45 volts.
4. Specified with high speed outputs biased with 150 Ω resistors and receiver TTL outputs driving 10 pF loads.
5. Based on independent package testing by HP. Θja for these devices is 56°C/Watt for the HDMP-1536A and 51°C/Watt for the
HDMP-1546A. Θja is measured on a standard 3x3" FR4 PCB in a still air environment. To determine the actual junction temperature
in a given application, use the following: Tj = TC + (Θjc x Pd), where TC is the case temperature measured on the top center of the
package and PD is the power being dissipated.
10
I/O Type Definitions
I/O Type
I-TTL
O-TTL
HS_OUT
HS_IN
C
S
Definition
Input TTL, Floats High When Left Open
Output TTL
High Speed Output, ECL Compatible
High Speed Input
External Circuit Node
Power Supply or Ground
Pin Input Capacitance
Symbol
C INPUT
Parameter
Input Capacitance on TTL Input Pins
Units
pF
O_TTL
Typ.
1.6
Max.
I_TTL
VCC_RXTTL
R
VCC
VCC
R
R
R
R
VBB 1.4 V
GND
*ESD
PROTECTION
GND_RXTTL
*ESD
PROTECTION
GND
Figure 9. O-TTL and I-TTL Simplified Circuit Schematic.
HS_OUT
HS_IN
VCC
VCC_TXHS
VCC_TXECL
+
–
+
–
R
VCC
VCC
R
+DOUT
Zo = 75 Ω
0.01 µF
+DIN
RPAD
150
-DOUT
150
RPAD
Zo = 75 Ω
0.01 µF
GND
*ESD
PROTECTION
-DIN
GND
*ESD
150
PROTECTION
GND_TXHS
GND
Figure 10. HS_OUT and HS_IN Simplified Circuit Schematic.
Notes:
1. HS_IN inputs should never be connected to ground as permanent damage to the device may result.
2. The optional series padding resistors (R pad) help dampen load reflections. Typical Rpad values for mismatched loads range between
25-75 Ω.
* Enhanced ESD Protection.
RXCAP1
VCC_RXA
-DIN
GND_RXA
VCC*
VCC*
+DIN
GND*
GND
VCC
VCC
GND_TXHS
VCC_TXHS
+DOUT
-DOUT
VCC_TXECL
11
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
*GND
TX[0]
TX[1]
1
48
2
3
47
46
TX[2]
4
5
6
45
44
43
*VCC
TX[3]
TX[4]
TX[5]
TX[6]
*VCC
7
8
9
TX[8]
10
11
12
TX[9]
*GND
GND_TXA
TXCAP1
13
14
15
16
TX[7]
HDMP-15x6A
xxxx-x Rz.zz
S
YYWW
RXCAP0
BYTSYNC
GND_RXTTL
RX[0]
RX[1]
RX[2]
42
41
40
VCC_RXTTL
RX[3]
RX[4]
39
38
RX[5]
RX[6]
37
VCC_RXTTL
36
35
RX[7]
34
33
RX[8]
RX[9]
GND_RXTTL
RBC0
GND_RXTTL
VCC
VCC_RXTTL
RBC1
SIG_DET
*N/C
VCC
ENBYTSYNC
GND
GND
REFCLK
TXCAP0
VCC_TXA
LOOPEN
VCC
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
xxxx-x = WAFER LOT NUMBER–BUILD NUMBER
Rz.zz = DIE REVISION
S = SUPPLIER CODE
YYWW = DATE CODE (YY = YEAR, WW = WORK WEEK)
COUNTRY = COUNTRY OF MANUFACTURE
(MARKED ON BACK OF DEVICE)
Figure 11. HDMP-1536/46A (TRx) Package Layout and Marking, Top View.
*N/C: This pin is connected to an isolated pad and has no functionality. It can be left open, however, TTL levels can also be
applied to this pin.
*VCC : This pin is bonded to an isolated pad and has no functionality. However, it is recommended that this pin be connected to
VCC in order to conform with the X3T11 “10-bit specification,” and to help dissipate heat.
*GND: This pin is bonded to an isolated pad and has no functionality. However, it is recommended that this pin be connected
to GND in order to conform with the X3T11 “10-bit specification,” and to help dissipate heat.
12
TRx I/O Definition
Name
BYTSYNC
Pin
47
-DIN
+DIN
-DOUT
+DOUT
52
54
61
62
ENBYTSYNC
24
GND
21
25
58
1
14
56
51
*GND
GND_RXA
GND_RXTTL
Type
O-TTL
Signal
Byte Sync Output: An active high output. Used to indicate detection of
a comma character (0011111XXX). It is only active when ENBYTSYNC
is enabled.
HS_IN Serial Data Inputs: High-speed inputs. Serial data is accepted from the
± DIN inputs when LOOPEN is low.
HS_OUT Serial Data Outputs: High-speed outputs. These lines are active when
LOOPEN is set low. When LOOPEN is set high, these outputs are held
static at logic level 1.
I-TTL Enable Byte Sync Input: When high, turns on the internal byte sync
function to allow clock synchronization to a comma character
(0011111XXX). When the line is low, the function is disabled and
will not reset registers and clocks, or strobe the BYTSYNC line.
S
Logic Ground: Normally 0 volts. This ground is used for internal PECL
logic. It should be isolated from the noisy TTL ground as well as possible.
S
S
GND_TXA
32
33
46
15
GND_TXHS
LOOPEN
64
19
S
I-TTL
*N/C
27
RBC1
RBC0
30
31
O-TTL
REFCLK
22
I-TTL
S
This pin is bonded to an isolated pad and has no functionality. However,
it is recommended that this pin be connected to GND in order to conform
with the X3T11 “10-bit specification,” and to help dissipate heat.
Analog Ground: Normally 0 volts. Used to provide a clean ground
plane for the receiver PLL and high-speed analog cells.
TTL Receiver Ground: Normally 0 volts. Used for the TTL output cells
of the receiver section.
Analog Ground: Normally 0 volts. Used to provide a clean ground plane
for the PLL and high-speed analog cells.
Ground: Normally 0 volts.
Loopback Enable Input: When set high, the high-speed serial signal is
internally wrapped from the transmitter’s serial loopback outputs back
to the receiver’s loopback inputs. Also, when in loopback mode, the
± DOUT outputs are held static at logic level 1. When set low, ± DOUT
outputs and ± DIN inputs are active.
This pin is connected to an isolated pad and has no functionality. It can be
left open, however, TTL levels can also be applied to this pin.
Receiver Byte Clocks: The receiver section recovers two 53.125 MHz
receive byte clocks. These two clocks are 180 degrees out of phase.
The receiver parallel data outputs are alternatively clocked on the
rising edge of these clocks. The rising edge of RBC1 aligns with the
output of the comma character (for byte alignment) when detected.
Reference Clock and Transmit Byte Clock: A 106.25 MHz clock
supplied by the host system. The transmitter section accepts this signal
as the frequency reference clock. It is multiplied by 10 to generate the
serial bit clock and other internal clocks. The transmit side also uses this
clock as the transmit byte clock for the incoming parallel data
TX[0]..TX[9]. It also serves as the reference clock for the receive
portion of the transceiver.
13
TRx I/O Definition (cont’d.)
Name
RX[0]
RX[1]
RX[2]
RX[3]
RX[4]
RX[5]
RX[6]
RX[7]
RX[8]
RX[9]
RXCAP0
RXCAP1
SIG_DET
Pin
45
44
43
41
40
39
38
36
35
34
48
49
26
TX[0]
TX[1]
TX[2]
TX[3]
TX[4]
TX[5]
TX[6]
TX[7]
TX[8]
TX[9]
TXCAP1
TXCAP0
VCC
2
3
4
6
7
8
9
11
12
13
16
17
20,23
28
57,59
50
I-TTL
S
S
VCC_TXA
5
10
53,55
29
37
42
18
VCC_TXECL
60
S
VCC_TXHS
63
S
VCC_RXA
*VCC
VCC _RXTTL
Type
O-TTL
C
O-TTL
C
S
S
S
Signal
Data Outputs: One 10 bit data byte. RX[0] is the first bit received.
RX[0] is the least significant bit.
Loop Filter Capacitor: A loop filter capacitor for the internal PLL must
be connected across the RXCAP0 and RXCAP1 pins. (typical value = 0.1 µF).
Signal Detect: Indicates a loss of signal on the high-speed differential inputs,
± DIN, as in the case where the transmission cable becomes disconnected.
If ± DIN > = 200 mV peak-to-peak, SIG_DET = logic 1.
If ± DIN < = 200 mV and ± DIN > 50 mV, SIG_DET = undefined.
If ± DIN < = 50 mV, SIG_DET = logic 0, RX[0:9] = 1111111111.
Data Inputs: One, 10 bit, pre-encoded data byte. TX[0] is the first bit
transmitted. TX[0] is the least significant bit.
Loop Filter Capacitor: A loop filter capacitor must be connected across
the TXCAP1 and TXCAP0 pins (typical value = 0.1 µF).
Logic Power Supply: Normally 3.3 volts. Used for internal receiver
PECL logic. It should be isolated from the noisy TTL supply as well as
possible.
Analog Power Supply: Normally 3.3 volts. Used to provide a clean
supply line for the PLL and high-speed analog cells.
This pin is bonded to an isolated pad and has no functionality. However,
it is recommended that this pin be connected to VCC in order to conform
with the X3T11 “10-bit specification,” and to help dissipate heat.
TTL Power Supply: Normally 3.3 volts. Used for all TTL receiver output
buffer cells.
Analog Power Supply: Normally 3.3 volts. Used to provide a clean
supply line for the PLL and high-speed analog cells.
High-Speed ECL Supply: Normally 3.3 volts. Used only for the last stage
of the high-speed transmitter output cell (HS_OUT) as shown in
Figure 10. Due to high current transitions, this VCC should be well
bypassed to a ground plane.
High-Speed Supply: Normally 3.3 volts. Used by the transmitter side for the
high-speed circuitry. Noise on this line should be minimized for best operation.
14
VCC**
VCC
Transceiver Power
Supply Bypass and Loop
Filter Capacitors
RXCAP1
VCC_RXA
GND_RXA
VCC*
VCC*
GND*
GND
VCC
GND*
VCC_TXECL
VCC
GND_TXHS
VCC_TXHS
CPLLR
RXCAP0
GND_RXTTL
VCC*
VCC_RXTTL
VCC
TOP VIEW
VCC*
GND_RXTTL
GND
VCC
VCC
GND
TXCAP0
VCC_TXA
TXCAP1
VCC
VCC_RXTTL
VCC_RXTTL
GND*
GND_TXA
GND_RXTTL
CPLLT
VCC
VCC**
* IT IS RECOMMENDED THAT THESE PINS BE CONNECTED TO THE APPROPRIATE
SUPPLY LINE, EITHER VCC OR GND, EVEN THOUGH THE PIN IS BONDED TO AN ISOLATED
PAD. REFER TO THE I/O DEFINITIONS SECTION FOR THESE PINS FOR MORE DETAILS.
** SUPPLY VOLTAGE INTO VCC_RXA AND VCC_TXA SHOULD BE FROM A LOW NOISE
SOURCE. ALL BYPASS CAPACITORS AND PLL FILTER CAPACITORS ARE 0.1 µF.
Bypass capacitors should be used
and placed as close as possible to
the appropriate power supply
pins of the HDMP-1536/46A as
shown on the schematic of Figure
12. All bypass chip capacitors are
0.1 µF. The VCC _RXA and
VCC_TXA pins are the analog
power supply pins for the PLL
sections. The voltage into these
pins should be clean with
minimum noise. The PLL loop
filter capacitors and their pin
locations are also shown on
Figure 12. Notice that only two
capacitors are required: CPLLT for
the transmitter and CPLLR for the
receiver. Nominal capacitance is
0.1 µF. The voltage across the
capacitors is on the order of
1 volt maximum, so the capacitor
can be a low voltage type and
physically small. The PLL
capacitors are placed physically
close to the appropriate pins on
the HDMP-1536/46A. Keeping
the lines short will prevent them
from picking up stray noise from
surrounding lines or components.
Figure 12. Power Supply Bypass.
Start-up Procedure:
The transceiver start-up
procedure(s) use the following
conditions: VCC = +3.3 V ± 5%
and REFCLK = 106.25 MHz
± 100 ppm. After the above
conditions have been met, apply
valid data using a balanced code
such as 8B/10B. Frequency lock
occurs within 500 µs. After
frequency lock, phase lock
occurs within 2500 bit times.
CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in handling and
assembly of this component to prevent damage and/or degradation which may be induced by electrostatic
discharge (ESD).
15
Package Information
Item
Package Material
Lead Finish Material
Lead Finish Thickness
Lead Coplanarity
Details
Plastic
85% Tin, 15% Lead
300-800 µm
HDMP-1536A: 0.08 mm max.
HDMP-1546A: 0.10 mm max.
Mechanical Dimensions
PIN #1 ID
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
3
4
5
6
7
8
9
48
47
46
45
44
43
42
41
40
HDMP-15x6A
A1
A2
TOP VIEW
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
B4
B1
A1
B5
B2
B3
A2
C1
C3
C2
Part
Number
A1
A2
B1
B2
B3
B4
B5
C1
C2
C3
HDMP-1536A
10.00
13.20
0.22
0.50
0.60
0.17
0.25
2.00
0.25 min.
2.45
HDMP-1546A
14.00
17.20
0.35
0.80
0.88
0.17
0.25
2.00
0.25 max. 2.35
Tolerance
± 0.10
± 0.25 ± 0.05
Basic +0.15/ max.
-0.10
Figure 13. Mechanical Dimensions of HDMP-1536/46A.
+0.10/-0.05
max.
For technical assistance or the location of
your nearest Hewlett-Packard sales office,
distributor or representative call:
Americas/Canada: 1-800-235-0312 or
408-654-8675
Far East/Australasia: Call your local HP
sales office.
Japan: (81 3) 3335-8152
Europe: Call your local HP sales office.
Data subject to change.
Copyright © 1997 Hewlett-Packard Co.
Obsoletes 5966-0232E
Printed in U.S.A.
5966-2717E (11/97)