Revised April 1999 74F322 Octal Serial/Parallel Register with Sign Extend General Description The 74F322 is an 8-bit shift register with provision for either serial or parallel loading and with 3-STATE parallel outputs plus a bi-state serial output. Parallel data inputs and parallel outputs are multiplexed to minimize pin count. State changes are initiated by the rising edge of the clock. Four synchronous modes of operation are possible: hold (store), shift right with serial entry, shift right with sign extend and parallel load. An asynchronous Master Reset (MR) input overrides clocked operation and clears the register. Features ■ Multiplexed parallel I/O ports ■ Separate serial input and output ■ Sign extend function ■ 3-STATE outputs for bus applications Ordering Code: Order Number Package Number 74F322PC N20A Package Description 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS009516.prf www.fairchildsemi.com 74F322 Octal Serial/Parallel Register with Sign Extend April 1988 74F322 Unit Loading/Fan Out Pin Names U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL Description RE Register Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA S/P Serial (HIGH) or Parallel (LOW) Mode Control Input 1.0/1.0 20 µA/−0.6 mA SE Sign Extend Input (Active LOW) 1.0/3.0 20 µA/−1.8 mA S Serial Data Select Input 1.0/2.0 20 µA/−1.2 mA D 0 , D1 Serial Data Inputs 1.0/1.0 20 µA/−0.6 mA CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA MR Asynchronous Master Reset Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA OE 3-STATE Output Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA Q0 Bi-State Serial Output 50/33.3 −1 mA/−20 mA I/O0–I/O 7 Multiplexed Parallel Data Inputs or 3.5/1.083 70 µA/−0.65 mA 150/40 (33.3) −3 mA/24 mA (20 mA) 3-STATE Parallel Data Outputs Functional Description nal on SE enables serial entry from either D0 or D1, as determined by the S input. A LOW signal on SE enables shift right but Q7 reloads its contents, thus performing the sign extend function required for the 74F384 Twos Complement Multiplier. A HIGH signal on OE disables the 3STATE output buffers, regardless of the other control inputs. In this condition the shifting and loading operations can still be performed. The 74F322 contains eight D-type edge triggered flip-flops and the interstage gating required to perform right shift and the intrastage gating necessary for hold and synchronous parallel load operations. A LOW signal on RE enables shifting or parallel loading, while a HIGH signal enables the hold mode. A HIGH signal on S/P enables shift right, while a LOW signal disables the 3-STATE output buffers and enables parallel loading. In the shift right mode a HIGH sig- Mode Select Table Inputs Mode Clear Parallel Outputs L L L Z Z L I1 I0 I0 O3 O2 O1 O1 O3 O2 O1 O1 O4 O3 O2 O1 O1 NC NC NC NC NC X L X L L L L L L X H X Z Z Z Z Z Z X X I7 I6 I5 I4 I3 I2 D0 O7 O6 O5 O4 D1 O7 O6 O5 O4 O7 O7 O6 O5 NC NC NC NC S/P SE S L X X X L X X X H L L X Load Shift H L H H L L Right H L H H H L Sign H L H L X L H H X X X L Extend Hold Q0 CP RE I/O7 I/O0 OE (Note 1) MR I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance Output State = LOW-to-HIGH Transition NC = No Change Note: I7–I 0 = The level of the steady-state input at the respective I/O terminal is loaded into the flip-flop while the flip-flop outputs (except Q0) are isolated from the I/O terminal. Note: D0, D 1 = The level of the steady-state inputs to the serial multiplexer input. Note: O7–O0 = The level of the respective Qn flip-flop prior to the last Clock LOW-to-HIGH transition. Note 1: When the OE input is HIGH all I/On terminals are at the high impedance state; sequential operation or clearing of the register is not affected. www.fairchildsemi.com 2 74F322 Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74F322 Absolute Maximum Ratings(Note 2) Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 3) −0.5V to +7.0V Input Current (Note 3) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Current Applied to Output twice the rated IOL (mA) in LOW State (Max) Note 3: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage Min Typ Units V Recognized as a HIGH Signal 0.8 V Recognized as a LOW Signal −1.2 V 2.0 10% VCC 2.5 10% VCC 2.4 5% VCC 2.7 5% VCC 2.7 VCC Max Min Conditions IIN = −18 mA IOH = −1 mA (Q0, I/On) V Min V Min IOH = −3 mA (I/On) IOH = −1 mA (Q0, I/On) IOH = −3 mA (I/On) 10% VCC 0.5 10% VCC 0.5 IOL = 20 mA (Q0) IOL = 24 mA (I/On) IIH Input HIGH Current 5.0 µA Max VIN = 2.7V IBVI Input HIGH Current Breakdown Test 7.0 µA Max VIN = 7.0V (Non-I/O Inputs) IBVIT Input HIGH Current Breakdown Test (I/O) 0.5 mA Max VIN = 5.5V (I/On) ICEX Output HIGH Leakage Current 50 µA Max VOUT = VCC VID Input Leakage V 0.0 IID = 1.9 µA 3.75 µA 0.0 VIOD = 150 mV −0.6 mA Max VIN = 0.5V (RE, S/P, Dn, CP, MR, OE) −1.2 mA Max VIN= 0.5V (S) −1.8 mA Max VIN= 0.5V (SE) Output Leakage Current 70 µA Max VI/O = 2.7V (I/On) Output Leakage Current −650 µA Max VI/O = 0.5V (I/On) −150 mA Max VOUT = 0V 500 µA 0.0V VOUT = 5.25V 90 mA Max 4.75 Test IOD Output Leakage IIL Input LOW Current All Other Pins Grounded Circuit Current IIH + All Other Pins Grounded IOZH IIL + IOZL IOS Output Short-Circuit Current IZZ Bus Drainage Test ICC Power Supply Current www.fairchildsemi.com −60 60 4 74F322 AC Electrical Characteristics Symbol Parameter TA = +25°C TA = −55°C to +125°C TA = 0°C to +75°C VCC = +5.0V CL = 50 pF CL = 50 pF CL = 50 pF Max Min Max Min Typ fMAX Maximum Clock Frequency 70 90 tPLH Propagation Delay 3.5 7.0 7.5 3.5 9.5 3.5 8.5 tPHL CP to I/On 5.0 8.5 11.0 3.5 10.0 5.0 12.0 tPLH Propagation Delay 3.5 7.0 9.0 3.5 11.0 3.5 10.0 tPHL CP to Q0 3.5 7.0 8.0 3.5 10.0 3.5 9.0 tPHL Propagation Delay 6.0 10.0 13.0 6.0 15.0 6.0 14.0 ns 5.5 7.5 12.0 5.5 14.0 5.5 13.0 ns ns 50 Min Units Max 70 MHz ns MR to I/On tPHL Propagation Delay MR to Q0 tPZH Output Enable Time 3.0 6.5 9.0 3.0 12.5 3.0 10.0 tPZL OE to I/On 4.0 8.5 11.0 4.0 14.5 4.0 12.0 tPHZ Output Disable Time 2.0 4.5 6.0 2.0 8.0 2.0 7.0 tPLZ OE to I/On 2.0 5.0 7.0 2.0 10.0 2.0 8.0 tPZH Output Enable Time 4.5 8.0 10.5 4.5 13.5 4.5 11.5 tPZL S/P to I/On 5.5 10.0 14.0 5.5 17.0 5.5 15.0 tPHZ Output Disable Time 5.0 9.0 11.5 5.0 16.5 5.0 12.5 tPLZ S/P to I/On 6.0 12.0 15.5 6.0 19.5 6.0 16.5 ns AC Operating Requirements TA = +25°C Symbol Parameter TA = −55°C to +125°C TA = 0C to +75°C VCC = +5.0V Min Max Units Min Max Min tS(H) Setup Time, HIGH or LOW 6.0 14.0 7.0 tS(L) RE to CP 14.0 18.0 16.0 tH(H) Hold Time, HIGH or LOW 0 0 0 tH(L) RE to CP 0 0 0 tS(H) Setup Time, HIGH or LOW 6.5 8.5 7.5 tS(L) D0, D1 or I/On to CP 6.5 8.5 7.5 tH(H) Hold Time, HIGH or LOW 2.0 3.0 3.0 tH(L) D0, D1 or I/On to CP 2.0 3.0 3.0 tSH) Setup Time, HIGH or LOW 7.0 9.0 8.0 tS(L) SE to CP 2.5 11.0 3.5 tH(H) Hold Time, HIGH or LOW 2.0 2.0 2.0 tH(L) SE to CP 0.0 1.0 0.0 tS(H) Setup Time, HIGH or LOW 11.0 13.0 12.0 tS(L) S/P to CP 13.5 21.0 15.5 tS(H) Setup Time, HIGH or LOW 6.5 8.5 7.5 tS(L) S to CP 9.0 11.0 10.0 tH(H) Hold Time, HIGH or LOW 0 1.0 0 tH(L) S or S/P to CP 0 0 0 tW(H) CP Pulse Width, HIGH or LOW 7.0 8.0 7.0 tW(L) MR Pulse Width, LOW 5.5 7.5 6.5 tREC Recovery Time 8.0 12.0 8.0 Max ns ns ns ns ns ns ns ns ns ns tW(L) ns MR to CP 5 www.fairchildsemi.com 74F322 Octal Serial/Parallel Register with Sign Extend Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. 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