Revised October 2000 74F569 4-Bit Bidirectional Counter with 3-STATE Outputs General Description Features The 74F569 is a fully synchronous, reversible counter with 3-STATE outputs. The 74F569 is a binary counter, featuring preset capability for programmable operation, carry lookahead for easy cascading, and a U/D input to control the direction of counting. For maximum flexibility there are both synchronous and master asynchronous reset inputs as well as both Clocked Carry (CC) and Terminal Count (TC) outputs. All state changes except Master Reset are initiated by the rising edge of the clock. A HIGH signal on the Output ■ Synchronous counting and loading ■ Lookahead carry capability for easy cascading ■ Preset capability for programmable operation ■ 3-STATE outputs for bus organized systems Enable (OE) input forces the output buffers into the high impedance state but does not prevent counting, resetting or parallel loading. Ordering Code: Order Number Package Number Package Description 74F569SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F569SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F569PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC FAST is a registered trademark of Fairchild Semiconductor Corporation. © 2000 Fairchild Semiconductor Corporation DS009565 www.fairchildsemi.com 74F569 4-Bit Bidirectional Counter with 3-STATE Outputs April 1988 74F569 Unit Loading/Fan Out Pin Names P0–P3 CEP Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL Parallel Data Inputs 1.0/1.0 20 µA/−0.6 mA Count Enable Parallel Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA Count Enable Trickle Input (Active LOW) 1.0/1.0 20 µA/−1.2 mA CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA PE Parallel Enable Input (Active LOW) 1.0/1.0 20 µA/−1.2 mA U/D Up/Down Count Control Input 1.0/1.0 20 µA/−0.6 mA OE Output Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA MR Master Reset Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA SR Synchronous Reset Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA CET 150/40(33.3) −3 mA/24 mA (20 mA) TC Terminal Count Output (Active LOW) 50/33.3 −1 mA/20 mA CC Clocked Carry Output (Active LOW) 50/33.3 −1 mA/20 mA O0–O3 3-STATE Parallel Data Outputs Functional Description The 74F569 counts in the modulo-16 binary sequence. From state 15 it will increment to state 0 in the Up mode; in the Down mode it will decrement from 0 to 15. The clock inputs of all flip-flops are driven in parallel through a clock buffer. All state changes (except due to Master Reset) occurs synchronously with the LOW-to-HIGH transition of the Clock Pulse (CP) input signal. stage counters, the connections between the TC output and the CEP and CET inputs can provide either slow or fast carry propagation. Figure 1 shows the connections for simple ripple carry, in which the clock period must be longer than the CP to TC delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock rates, the carry lookahead connections shown in Figure 2 are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from max to min in the Up mode, or min to max in the Down mode, to start its final cycle. Since this final cycle takes 16 clocks to complete, there is plenty of time for the ripple to progress through the intermediate stages. The critical timing that limits the clock period is the CP to TC delay of the first stage plus the CEP to CP setup time of the last stage. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, registers or counters. For such applications, the Clocked Carry (CC) output is provided. The CC output is normally HIGH. When CEP, CET, and TC are LOW, the CC output will go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again, as shown in the CC Truth Table. When the Output Enable (OE) is LOW, the parallel data outputs O0–O3 are active and follow the flip-flop Q outputs. A HIGH signal on OE forces O0–O3 to the High Z state but does not prevent counting, loading or resetting. The circuits have five fundamental modes of operation, in order of precedence: asynchronous reset, synchronous reset, parallel load, count and hold. Five control inputs— Master Reset (MR), Synchronous Reset (SR), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle CET)—plus the Up/Down (U/D) input, determine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces the flip-flop Q outputs LOW. A LOW signal on SR overrides counting and parallel loading and allows the Q outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With MR, SR and PE HIGH, CEP and CET permit counting when both are LOW. Conversely, a HIGH signal on either CEP or CET inhibits counting. The 74F569 uses edge-triggered flip-flops and changing the SR, PE, CEP, CET or U/D inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. Two types of outputs are provided as overflow/underflow indicators. The Terminal Count (TC) output is normally HIGH and goes LOW providing CET is LOW, when the counter reaches zero in the Down mode, or reaches maximum Logic Equations Count Enable = CEP • CET • PE (15) in the Up mode. TC will then remain LOW until a state change occurs, whether by counting or presetting, or until U/D or CET is changed. To implement synchronous multi- www.fairchildsemi.com Up: TC = Q0 • Q1 • Q2 • Q3 • (Up) • CET Down: TC = Q0 • Q1 • Q2 • Q3 • (Down) • CET 2 Mode Select Table Inputs SR PE CEP CET Output TC (Note 1) CP CC L X X X X X H X L X X X X H X X H X X X H X X X H X X H X X X X H H H L L L H = HIGH Voltage Level L = LOW Voltage Level Inputs X H X = Immaterial = HIGH-to-LOW-to-HIGH Clock Transition Operating MR SR PE L X X X X X Asynchronous Reset H L X X X X Synchronous Reset H H L X X X Parallel Load H H H H X X Hold H H H X H X Hold H H H L L H Count Up H H H L L L Count Down CEP CET U/D Mode H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Note 1: TC is generated internally FIGURE 1. Multistage Counter with Ripple Carry FIGURE 2. Multistage Counter with Lookahead Carry State Diagram 3 www.fairchildsemi.com 74F569 CC Truth Table 74F569 Logic Diagram Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 4 Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +175°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 3) −0.5V to +7.0V Input Current (Note 3) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs. Current Applied to Output in LOW State (Max) twice the rated IOL (mA) DC Electrical Characteristics Symbol Parameter Min Typ Max Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V VOH Output HIGH 10% VCC 2.5 Voltage 10% VCC 2.4 5% VCC 2.7 5% VCC 2.7 VOL IIH 2.0 Units VIH V 10% VCC 0.5 Voltage 10% VCC 0.5 IOD Output Leakage Input LOW Current IOL = 20 mA (TC, CC) Max VIN = 2.7V 7.0 µA Max VIN = 7.0V 50 µA Max VOUT = VCC (TC, CC, On) V 0.0 3.75 µA 0.0 −0.6 mA Max −1.2 mA Max VIN = 0.5V (PE, CET) 50 µA Max VOUT = 2.7V (On) −50 µA Max VOUT = 0.5V (On) −150 mA Max VOUT = 0V (TC, CC, On) 4.75 Circuit Current IIL IOH = −1 mA (TC, CC, On) µA Leakage Current Test IOH = −3 mA (On) 5.0 Breakdown Test Input Leakage Min Min Input HIGH Current VID IIN = −18 mA V Input HIGH Output HIGH Recognized as a LOW Signal Min IOH = −3 mA (On) Output LOW ICEX Conditions Recognized as a HIGH Signal IOH = −1 mA (TC, CC, On) Current IBVI VCC V IOL = 24 mA (On) IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V (Pn, CEP, CP, U/D, OE, MR, SR) IOZH Output Leakage Current IOZL Output Leakage Current IOS Output Short-Circuit Current IZZ Bus Drainage Test 500 µA 0.0V VOUT = 5.25V (On) ICCH Power Supply Current 45 67 mA Max VO = HIGH ICCL Power Supply Current 45 67 mA Max VO = LOW ICCZ Power Supply Current 45 67 mA Max VO = HIGH Z −60 5 www.fairchildsemi.com 74F569 Absolute Maximum Ratings(Note 2) 74F569 AC Electrical Characteristics Symbol Parameter Min TA = +25°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF Typ Max Min Max fMAX Maximum Clock Frequency 90 tPLH Propagation Delay 3.0 tPHL CP to On (PE HIGH or LOW) 4.0 tPLH Propagation Delay 5.5 tPHL CP to TC 4.0 8.5 tPLH Propagation Delay 2.5 4.5 tPHL CET to TC 2.5 6.0 11.0 2.5 12.0 tPLH Propagation Delay 3.5 8.5 11.5 3.5 12.5 tPHL U/D to TC 4.0 8.0 12.0 4.0 13.0 tPLH Propagation Delay 2.5 5.5 7.0 2.0 8.0 tPHL CP to CC 2.0 4.5 6.0 2.0 7.0 tPLH Propagation Delay 2.5 5.0 6.5 2.0 7.5 tPHL CEP, CET to CC 4.0 8.5 11.0 4.0 12.5 tPHL Propagation Delay 5.0 10.0 13.0 5.0 14.5 2.5 5.5 8.0 2.5 8.5 MR to On 70 6.5 MHz 8.5 3.0 9.5 9.0 11.5 4.0 13.0 12.0 15.5 5.5 17.5 12.5 4.0 13.0 6.5 2.5 7.0 tPZH Output Enable Time tPZL OE to On 3.0 6.0 9.0 3.0 10.0 tPHZ Output Disable Time 1.5 5.0 7.0 1.5 8.0 tPLZ OE to On 2.0 4.5 6.0 2.0 7.0 www.fairchildsemi.com 6 Units ns ns ns ns ns ns ns ns 74F569 AC Operating Requirements TA = +25°C Symbol VCC = +5.0V Parameter Min Max TA = 0°C to +70°C VCC = +5.0V Min tS(H) Setup Time, HIGH or LOW 4.0 4.5 tS(L) Pn to CP 4.0 4.5 tH(H) Hold Time, HIGH or LOW 3.0 3.5 tH(L) Pn to CP 3.0 3.5 tS(H) Setup Time, HIGH or LOW 7.0 8.0 tS(L) CEP or CET to CP 5.0 6.5 tH(H) Hold Time, HIGH or LOW 0 0 0.5 tH(L) CEP or CET to CP 0.5 tS(H) Setup Time, HIGH or LOW 8.0 9.0 tS(L) PE to CP 8.0 9.0 tH(H) Hold Time, HIGH or LOW 0.0 1.0 tH(L) PE to CP 0 0 tS(H) Setup Time, HIGH or LOW 11.0 12.5 tS(L) U/D to CP 7.0 8.5 tH(H) Hold Time, HIGH or LOW 0 0 tH(L) U/D to CP 0 0 tS(H) Setup Time, HIGH or LOW 10.5 11.0 tS(L) SR to CP 8.5 9.5 tH(H) Hold Time, HIGH or LOW 0 0 Units Max ns ns ns ns ns ns tH(L) SR to CP 0 0 tW(H) CP Pulse Width, 4.0 4.5 tW(L) HIGH or LOW 7.0 8.0 tW(L) MR Pulse Width, LOW 4.5 6.0 ns tREC MR Recovery Time 6.0 8.0 ns 7 ns www.fairchildsemi.com 74F569 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B www.fairchildsemi.com 8 74F569 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 9 www.fairchildsemi.com 74F569 4-Bit Bidirectional Counter with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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