Revised August 1999 74F299 Octal Universal Shift/Storage Register with Common Parallel I/O Pins General Description Features The 74F299 is an 8-bit universal shift/storage register with 3-STATE outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Additional outputs, Q0– Q7, are provided to allow easy serial cascading. A separate active LOW Master Reset is used to reset the register. ■ Common parallel I/O for reduced pin count ■ Additional serial inputs and outputs for expansion ■ Four operating modes: shift left, shift right, load and store ■ 3-STATE outputs for bus-oriented applications ■ Guaranteed 4000V minimum ESD protection Ordering Code: Order Number Package Number Package Description 74F299SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F299SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F299PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS009515 www.fairchildsemi.com 74F299 Octal Universal Shift/Storage Register April 1988 74F299 Unit Loading/Fan Out Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA DS0 Serial Data Input for Right Shift 1.0/1.0 20 µA/−0.6 mA DS7 Serial Data Input for Left Shift 1.0/1.0 20 µA/−0.6 mA S0 , S1 Mode Select Inputs 1.0/2.0 20 µA/−1.2 mA MR Asynchronous Master Reset Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA OE1, OE2 3-STATE Output Enable Inputs (Active LOW) 1.0/1.0 20 µA/−0.6 mA I/O0–I/O7 Parallel Data Inputs or 3.5/1.083 70 µA/−0.65 mA 150/40(33.3) −3 mA/24 mA (20 mA) 50/33.3 −1 mA/20 mA 3-STATE Parallel Outputs Q0, Q7 Serial Outputs Logic Diagram Functional Description The 74F299 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1, as shown in the Mode Select Table. All flip-flop outputs are brought out through 3-STATE buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A LOW signal on MR overrides the Select and CP inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed. A HIGH signal on either OE1 or OE2 disables the 3-STATE buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The 3-STATE outputs are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation. Mode Select Table Inputs Response MR S1 S0 CP L X X H H H H L H H H L H L L X Asynchronous Reset; Q0–Q7 = LOW Parallel Load; I/On → Qn Shift Right; DS0 → Q0, Q0 → Q1, etc. Shift Left; DS7 → Q7, Q7 → Q6, etc. X Hold H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA ESD Last Passing Voltage (Min) 4000V Voltage Applied to Output in HIGH State (with VCC = 0V) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. −0.5V to VCC Standard Output 3-STATE Output Note 2: Either voltage limit or current limit is sufficient to protect inputs. −0.5V to +5.5V Current Applied to Output twice the rated IOL (mA) in LOW State (Max) DC Electrical Characteristics Symbol Parameter Min Typ Max VCC VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA VOH Output HIGH 10% VCC 2.5 V Min IOH = −1 mA (Q0, Q7, I/On) Voltage 10% VCC 2.4 IOH = −3 mA (I/On) 5% VCC 2.7 IOH = −1 mA (Q0, Q7, I/On) 5% VCC 2.7 IIH V Conditions Input HIGH Voltage VOL 2.0 Units VIH 10% VCC 0.5 Voltage 10% VCC 0.5 Input HIGH Input HIGH Current Breakdown Test IBVIT Input HIGH Current Breakdown Test (I/O) ICEX Output HIGH Leakage Current VID Input Leakage Test IOD Output Leakage Input LOW Current V Min IIH+ Output Leakage Current IIL+ Output Leakage IOZL Current −60 VIN = 2.7V (CP, DS0, DS7, S0, S1, µA Max 7.0 µA Max 0.5 mA Max VIN = 5.5V (I/On) 50 µA Max VOUT = VCC V 0.0 3.75 µA 0.0 −0.6 mA Max MR, OE1, OE 2) VIN = 7.0V (CP, DS0, DS7, S0, S1, MR, OE1, OE 2) IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V (CP, DS0, DS7, MR, OE1, OE2) VIN = 0.5V (S0, S1) −1.2 IOZH IOL = 20 mA (Q0, Q7) IOL = 24 mA (I/On) 5.0 4.75 Circuit Current IIL Recognized as a LOW Signal IOH = −3 mA (I/On) Output LOW Current IBVI Recognized as a HIGH Signal 70 µA Max VI/O = 2.7V (I/On) −650 µA Max VI/O = 0.5V (I/On) −150 mA Max VOUT = 0V 500 µA 0.0V VOUT = 5.25V IOS Output Short-Circuit Current IZZ Bus Drainage Test ICCH Power Supply Current 68 95 mA Max VO = HIGH ICCL Power Supply Current 68 95 mA Max VO = LOW ICCZ Power Supply Current 68 95 mA Max VO = HIGH Z 3 www.fairchildsemi.com 74F299 Absolute Maximum Ratings(Note 1) 74F299 AC Electrical Characteristics Symbol Parameter TA = +25°C TA = −55°C to +125°C TA = 0 to +70°C VCC = 5.0V VCC = 5.0V VCC = 5.0V CL = 50 pF CL = 50 pF CL = 50 pF Min Typ fMAX Maximum Input Frequency 70 100 tPLH Propagation Delay 4.0 7.0 tPHL CP to Q0 or Q7 4.5 6.5 8.0 4.5 9.5 4.5 8.5 tPLH Propagation Delay 3.5 7.0 9.0 3.5 10.0 3.5 10.0 tPHL CP to I/On 4.0 8.5 9.0 4.0 11.0 4.0 10.0 tPHL Propagation Delay 5.5 7.5 9.5 5.5 12.5 5.5 10.5 5.5 11.0 10.0 5.5 12.0 5.5 10.5 MR to Q0 or Q7 tPHL Max Min Max 85 8.0 4.0 Min Max 70 9.0 4.0 Units MHz 8.5 ns ns Propagation Delay MR to I/On tPZH Output Enable Time 3.5 6.0 8.0 3.0 9.5 3.5 9.0 tPZL OE to I/On 4.0 7.0 10.0 4.0 13.0 4.0 11.0 tPHZ Output Disable Time 2.0 4.5 6.0 1.5 7.0 2.0 7.0 tPLZ OE to I/On 1.0 4.0 5.5 1.0 6.5 1.0 6.5 tPZH Output Enable Time 3.5 9.0 3.0 10.5 3.5 10.0 tPZL Sn to I/On 4.0 10.0 4.0 13.0 4.0 11.0 tPHZ Output Disable Time 2.5 6.0 1.5 7.0 2.5 7.0 tPLZ Sn to I/On 1.5 5.5 1.0 6.5 1.5 6.5 ns ns ns AC Operating Requirements Symbol Parameter TA = +25°C TA = −55°C to +125°C VCC = 5.0V VCC = 5.0V Min Max Min Max TA = 0 to +70°C VCC = 5.0V Min tS(H) Setup Time, HIGH or LOW 8.5 10.0 8.5 tS(L) S0 or S1 to CP 8.5 7.5 8.5 tH(H) Hold Time, HIGH or LOW 0 0 0 Units Max ns tH(L) S0 or S1 to CP 0 0 0 tS(H) Setup Time, HIGH or LOW 5.0 5.0 5.0 tS(L) I/On, DS0 or DS7 to CP 5.0 5.0 5.0 tH(H) Hold Time, HIGH or LOW 2.0 2.0 2.0 tH(L) I/On, DS0 or DS7 to CP 2.0 2.0 2.0 tW(H) CP Pulse Width 5.0 5.0 5.0 tW(L) HIGH or LOW 5.0 5.0 5.0 tW(L) MR Pulse Width, LOW 5.0 6.0 5.0 ns tREC Recovery Time, MR to CP 7.0 12.0 7.0 ns www.fairchildsemi.com 4 ns ns 74F299 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number MD20D 5 www.fairchildsemi.com 74F299 Octal Universal Shift/Storage Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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