a Preliminary Technical Data Blackfin® Embedded Processor ADSP-BF522C/ADSP-BF525C/ADSP-BF527C FEATURES PERIPHERALS Up to 600 MHz high-performance Blackfin processor Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register and instruction model for ease of programming and compiler-friendly support Advanced debug, trace, and performance monitoring tbd V to tbd V core VDD with on-chip voltage regulation 1.8V, 2.5V, or 3.3V I/O operation Embedded low power audio CODEC 289-ball MBGA package Refer to the published ADSP-BF522/ADSP-BF525/ADSPBF527 Revision PrB datasheet for additional peripherals CODEC FEATURES MEMORY 132K bytes of on-chip memory: 48K bytes of instruction SRAM 16K bytes of instruction SRAM/cache 32K bytes of data SRAM 32K bytes of data SRAM/cache 4K bytes of scratchpad SRAM External memory controller with glueless support for SDRAM and asynchronous 8-bit and 16-bit memories Nand flash controller Flexible booting options from external flash, SPI and TWI memory or from SPI, TWI, and UART host devices One-time programmable memory for security Two dual-channel memory DMA controllers Memory management unit providing memory protection Stereo 24-bit A/D and D/A converters DAC 100 dB (A-weighted) signal-to-noise ratio at 3.3 V 95 dB (A-weighted) signal-to-noise ratio at 1.8 V ADC 90 dB (A-weighted) signal-to-noise ratio at 3.3 V 85dB (A-weighted) signal-to-noise ratio at 1.8 V Audio sample rates 8 kHz, 44.1 kHz or 88.2 kHz–XTI/MCLK frequency 11.2896 MHz (256 × FS) or 16.9344 MHz (384 × FS) 8 kHz, 32 kHz, 48 kHz or 96 kHz–XTI/MCLK frequency 12.288 MHz (256 × FS) or 18.432 MHz (384 × FS) Highly efficient headphone amplifier Complete stereo/mono or microphone/line interface Normal and USB modes programmed under software control Low power 8 mW stereo playback (1.8 V all power supplies) 20 mW record and playback (1.8 V all power supplies)) Low supply voltages 1.8 V to 3.6 V analog supply range 1.8 V to 3.6 V digital supply range OTP JTAG TEST AND EMULATION VOLTAGE REGULATOR WATCHDOG TIMER PERIPHERAL ACCESS BUS B RTC INTERRUPT CONTROLLER TWI SPORT1-0 CODEC L1 INSTRUCTION MEMORY USB L1 DATA MEMORY 16 NAND DMA CONTROLLER DMA CORE BUS EXTERNAL ACCESS BUS PPI PORTS UART 0-1 DMA EXTERNAL BUS SPI TIMERS 0-7 BOOT ROM EXTERNAL PORT FLASH, SDRAM CONTROL EMAC/HDMA Figure 1. Functional Block Diagram Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. Rev. PrB Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2007 Analog Devices, Inc. All rights reserved. ADSP-BF522C/ADSP-BF525C/ADSP-BF527C REVISION HISTORY 6/07—Revision PrB: Changes from PrA to PrB Corrects SS/PG and VRSEL 289-Ball Mini-BGA Ball Assignment (Alphabetically by Signal) ................................... 7 Corrects SS/PG and VRSEL 289-Ball Mini-BGA Ball Assignment (Numerically by Ball Number) ............................. 8 3/07—Revision PrA: Initial Version Rev. PrB | Page 2 of 12 | June 2007 Preliminary Technical Data ADSP-BF522C/ADSP-BF525C/ADSP-BF527C Preliminary Technical Data GENERAL DESCRIPTION This document describes the differences between the ADSPBF522C/ADSP-BF525C/ADSP-BF527C and the ADSPBF522/ADSP-BF525/ADSP-BF527 standard product. Please refer to the published ADSP-BF522/ADSP-BF525/ADSP-BF527 Revision PrC datasheet for general description and specifications. This document only describes the exceptions to that datasheet. The ADSP-BF522C/ADSP-BF525C/ADSP-BF527C adds a stereo CODEC to the standard product and changes the package labeling. In normal mode, the XMI/MCLK oscillator is set up according to the desired sample rates of the ADC and DAC. For ADC or DAC sampling rates of 8 kHz, 32 kHz, 48 kHz or 96 kHz, MCLK frequencies of either 12.288 MHz (256 × FS) or 18.432 MHz (384 × FS) can be used. For ADC or DAC sampling rates of 8 kHz, 44.1 kHz or 88.2 kHz, MCLK frequencies of either 11.2896 MHz (256 × FS) or 16.9344 MHz (384 × FS) can be used. In USB mode, the XTI/MCLK frequency is only 12MHz allowing for ADC and DAC sampling rates of 8 kHz, 44.1 kHz or 88.2 kHz. STEREO CODEC The CODEC can operate with power supplies as low as 1.8 V for the analog part and 1.8 V for digital port. The maximum voltage is 3.6 V for all power supplies. The CODEC in the ADSP-BF522C/ADSP-BF525C/ADSPBF527C is a low power, high quality stereo audio CODEC for portable digital audio application. It features two 24-bit A/D converter channels and two 24-bit D/A converter channels. The device is controlled by a 2- or 3-wire serial interface which provides access to all features including volume controls, mutes and extensive power management facilities. ATTENUATOR MICBIAS ATTENUATOR RHPOUT RLINEIN MUX ADC MICIN LLINEIN DAC + ROUT DAC + LOUT LHPOUT DIGITAL FILTERS MUX ADC ATTENUATOR ATTENUATOR CLK DIGITAL AUDIO INTERFACE XTI/MCLK XTO CCLKOUT DACDAT ADCDAT BCLK ADCLRC DACLRC CONTROL INTERFACE CMODE CSB CSDA CSCL Figure 2. Audio CODEC Block Diagram Rev. PrB | Page 3 of 12 | June 2007 ADSP-BF522C/ADSP-BF525C/ADSP-BF527C Preliminary Technical Data PIN DESCRIPTIONS The ADSP-BF522C/ADSP-BF525C/ADSP-BF527C processor adds CODEC signals as listed in Table 1. Table 1. Pin Descriptions Pin Name 1 Type Function Pull-Up/Down CCLKOUT O CODEC Clock Output None BCLK I/O CODEC Digital Audio Bit Clock Internal Pull-down1 DACDAT I CODEC DAC Sample Rate Left/Right Clock None DACLRC I/O CODEC I/O DAC Sample Rate Left/Right Clock Internal Pull-down1 ADCDAT O CODEC ADC Digital Audio Data Output None ADCLRC I/O CODEC ADC Sample Rate Left/Right Clock Internal Pull-down1 CMODE I CODEC Control Interface Selection Internal Pull-up1 CSB I CODEC MPU Chip Select/MPU Interface Address Selection Internal Pull-up1 CSDA I/O CODEC MPU Data Input None CSCL I CODEC MPU Clock None XTI/MCLK I CODEC Crystal Input/MPU Clock Input None XTO O CODEC Crystal Output None LHPOUT O CODEC Left Channel Headphone Output (Analog Output) None RHPOUT O CODEC Right Channel Headphone Output (Analog Output) None LOUT O CODEC Left Channel Line Output (Analog Output) None ROUT O CODEC Right Channel Line Output (Analog Output) None VMID O CODEC Mid-rail Reference Decoupling Point (Analog Output) None MICBIAS O CODEC Electret Microphone Bias (Analog Output) None MICIN I CODEC Microphone Input; (Analog Input, AC Coupled) None RLINEIN I CODEC Right Channel Line Input (Analog Input, AC Coupled) None LLINEIN I CODEC Left Channel Line Input (Analog Input, AC Coupled) None GND P CODEC Digital Core Ground N/A AVDD P CODEC Analog VDD N/A AGND P CODEC Analog Ground N/A HPVDD P CODEC Headphone VDD (Analog) N/A HPGND P CODEC Headphone Ground N/A Pull-up/pull-down is only present when the control register interface ACTIVE = 0 to conserve power. Rev. PrB | Page 4 of 12 | June 2007 ADSP-BF522C/ADSP-BF525C/ADSP-BF527C Preliminary Technical Data SPECIFICATIONS Component specifications are subject to change without notice. OPERATING CONDITIONS Parameter Conditions CVDD Digital Core VDD AVDD Analog VDD HPVDD Headphone VDD (Analog) VILC CODEC Low Level Input Voltage1 VIHC CODEC High Level Input Voltage1 VOLC CODEC Low Level Output Voltage1 VOHC CODEC Low Level Output Voltage1 TJ Junction Temperature 289-Ball Chip Scale Ball Grid Array (Mini-BGA) @ TAMBIENT = 0°C to +70°C 1 Min 1.8 1.8 1.8 Typical Max 3.6 3.6 3.6 0.3 × CVDD 0.7 × CVDD 0.1 × CVDD 0.9 × CVDD 0 +105 Unit V V V V V V V °C Parameter value applies to digital signal pins (ADCDAT, ADCLRC, BCLK, CSB, CCLKOUT, CMODE, DACDAT, DACLRC, CSCL, CSDA, XTI/MCLK, XTO). ELECTRICAL CHARACTERISTICS Parameter Conditions Line Input to ADC SNR Signal to Noise Ratio A-weighted, 0 dB Gain @ FS = 48 kHz SNR Signal to Noise Ratio A-weighted, 0 dB Gain @ FS = 96 kHz DR Dynamic Range A-weighted, –60 dB Full Scale Input THD Total Harmonic Distortion –1 dB Input, 0 dB Gain Microphone Input to ADC 0 dB Gain, FS = 48 kHz, 40 kΩ Source Impedance SNR Signal to Noise Ratio A-weighted, 0 dB Gain DR Dynamic Range A-weighted, –60 dB Full Scale Input THD Total Harmonic Distortion 0 dB Input, 0 dB Gain Line Output for DAC Playback Only Load = 10 kΩ, 50 pF SNR Signal to Noise Ratio A-weighted, 0 dB Gain @ FS = 48 kHz SNR Signal to Noise Ratio A-weighted, 0 dB Gain @ FS = 96 kHz DR Dynamic Range A-weighted, –60 dB Full Scale Input THD Total Harmonic Distortion 1 kHz, 0 dB THD Total Harmonic Distortion 1 kHz, –3 dB Analog Line Input to Line Output Load = 10 k Ω, 50 pF, No Gain on Input, Bypass Mode SNR Signal to Noise Ratio THD Total Harmonic Distortion 1 kHz, 0 dB THD Total Harmonic Distortion 1 kHz, –3 dB Stereo Headphone Output PO Maximum Output Power RL = 32 Ω PO Maximum Output Power RL = 16 Ω SNR Signal to Noise Ratio A-weighted THD Total Harmonic Distortion 1 kHz, –5 dB, RL = 32 Ω, Full Scale Input THD Total Harmonic Distortion 1 kHz,–2 dB, RL = 32 Ω, Full Scale Input Microphone Input to Headphone Output Side Tone Mode SNR Signal to Noise Ratio Rev. PrB | Page 5 of 12 | June 2007 Min Typical tbd 85 85 88 –76 tbd tbd tbd tbd tbd tbd Max Unit tbd dB dB dB dB 80 70 –55 dB dB dB 95 93 90 –80 –90 dB dB dB dB dB 90 –83 –92 9 18 95 –62 90 tbd tbd tbd tbd dB dB dB mW mW dB dB dB dB ADSP-BF522C/ADSP-BF525C/ADSP-BF527C Preliminary Technical Data DIGITAL FILTER CHARACTERISTICS Parameter ADC Filter Passband Passband Passband Ripple Stopband Stopband Attenuation High Pass Filter Corner Frequency High Pass Filter Corner Frequency High Pass Filter Corner Frequency DAC Filter Passband Passband Passband Ripple Stopband Stopband Attenuation Conditions Min ±0.05 dB –6 dB tbd × FS Typical Max tbd × FS 0.5 × FS tbd tbd × FS tbd F > 0.5465 × FS –3 dB –0.5 dB –0.1 dB tbd × FS tbd × FS 0.5 × FS tbd tbd × FS tbd F > 0.5465 × FS PACKAGE INFORMATION The information presented in Figure 3 and Table 2 provides details about the package branding for the ADSPBF522C/ADSP-BF525C/ADSP-BF527C processor. For a complete listing of product availability, see Ordering Guide on Page 12. a ADSP-BF525C tppZccc vvvvvv.x n.n yyww country_of_origin B Figure 3. Product Information on Package Table 2. Package Brand Information Field Description t Temperature Range pp Package Type Z Lead Free Option ccc See Ordering Guide vvvvvv.x Assembly Lot Code n.n Silicon Revision yyww Date Code dB dB Hz Hz Hz 3.7 10.4 21.6 ±0.03 dB –6 dB Brand Key Unit Rev. PrB | Page 6 of 12 | June 2007 dB dB ADSP-BF522C/ADSP-BF525C/ADSP-BF527C Preliminary Technical Data 289-BALL MINI-BGA PINOUT Table 3 lists the mini-BGA pinout by signal mnemonic. Table 4 on Page 8 lists the mini-BGA pinout by ball number. Table 3. 289-Ball Mini-BGA Ball Assignment (Alphabetically by Signal) Signal Ball No. ABE0/SDQM0 AB9 ABE1/SDQM1 AC9 ADCDAT A16 ADCLRC A15 ADDR1 AB8 ADDR2 AC8 ADDR3 AB7 ADDR4 AC7 ADDR5 AC6 ADDR6 AB6 ADDR7 AB4 ADDR8 AB5 ADDR9 AC5 ADDR10 AC4 ADDR11 AB3 ADDR12 AC3 ADDR13 AB2 ADDR14 AC2 ADDR15 AA2 ADDR16 W2 ADDR17 Y2 ADDR18 AA1 ADDR19 AB1 AGND G17 AGND H22 AMS0 AC17 AMS1 AB16 AMS2 AC16 AMS3 AB15 AOE AC15 ARDY AC14 ARE AB17 AVDD G16 AVDD J22 AWE AB14 BCLK A19 BMODE0 G2 BMODE1 F2 BMODE2 E1 BMODE3 E2 CCLKOUT D22 CLKBUF AB19 CLKIN R23 CLKOUT AB18 CMODE E22 Signal Ball No. CSB D23 CSCL B23 CSDA C23 DACDAT A18 DACLRC A17 DATA0 Y1 DATA1 V2 DATA2 W1 DATA3 U2 DATA4 V1 DATA5 U1 DATA6 T2 DATA7 T1 DATA8 R1 DATA9 P1 DATA10 P2 DATA11 R2 DATA12 N1 DATA13 N2 DATA14 M2 DATA15 M1 EMU J2 EXT_WAKE AC19 GND A1 GND A23 GND B6 GND J9 GND J10 GND J11 GND J12 GND J13 GND J14 GND J15 GND K9 GND K10 GND K11 GND K12 GND K13 GND K14 GND K15 GND L9 GND L10 GND L11 GND L12 GND L13 Signal GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND LHPOUT LLINEIN LOUT MICBIAS MICIN NMI OTPVPP PF0 PF1 PF2 PF3 PF4 Ball No. L14 L15 M9 M10 M11 M12 M13 M14 M15 N9 N10 N11 N12 N13 N14 N15 P9 P10 P11 P12 P13 P14 P15 R9 R10 R11 R12 R13 R14 R15 T22 AC1 AC23 B20 E23 F22 H23 J23 U22 AB11 A7 B8 A8 B9 B11 Signal PF5 PF6 PF7 PF8 PF9 PF10 PF11 PF12 PF13 PF14 PF15 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 PG10 PG11 PG12 PG13 PG14 PG15 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PH8 PH9 PH10 PH11 PH12 PH13 PH14 PH15 PPICLK/TMRCLK PPIFS1/TMR0 Rev. PrB Ball No. B10 B12 B13 B16 A20 B15 B17 B18 B19 A9 A10 H2 G1 H1 F1 D1 D2 C2 B1 C1 B2 B4 B3 A2 A3 A4 A5 A11 A12 A13 B14 A14 K23 K22 L23 L22 T23 M22 R22 M23 N22 N23 P22 A6 B7 Signal RESET RHPOUT RLINEIN ROUT RTXI RTXO SA10 SCAS SCKE SCL SDA SMS SRAS SS/PG SWE TCK TDI TDO TMS TRST USB_DM USB_DP USB_ID USB_RSET USB_VBUS USB_VREF USB_XTALIN USB_XTALOUT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT | Page 7 of 12 | June 2007 Ball No. V22 B21 F23 G22 U23 V23 AC10 AC11 AB13 B22 C22 AC13 AB12 AC20 AB10 L1 J1 K1 L2 K2 AB21 AA22 Y22 AC21 AB20 AC22 AB23 AA23 G7 G8 G9 G10 G11 G12 G13 G14 G15 H7 H17 J17 K17 L17 M17 N17 P17 Signal VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDMEM VDDMEM VDDMEM VDDMEM VDDMEM VDDMEM VDDMEM VDDMEM VDDMEM Ball No. R17 T17 U17 B5 H8 H9 H10 H11 H12 H13 H14 H15 H16 J8 J16 K8 K16 L8 L16 M8 M16 N8 N16 P8 P16 R8 R16 T8 T9 T10 T11 T12 T13 T14 T15 T16 J7 K7 L7 M7 N7 P7 R7 T7 U7 Signal VDDMEM VDDMEM VDDMEM VDDMEM VDDMEM VDDMEM VDDMEM VDDMEM VDDMEM VDDOTP VDDRTC VDDUSB VDDUSB VMID VROUT VRSEL XTAL XTI/MCLK XTO Ball No. U8 U9 U10 U11 U12 U13 U14 U15 U16 AC12 W23 W22 Y23 G23 AC18 AB22 P23 A22 A21 ADSP-BF522C/ADSP-BF525C/ADSP-BF527C Preliminary Technical Data Table 4. 289-Ball Mini-BGA Ball Assignment (Numerically by Ball Number) Ball No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 Signal GND PG12 PG13 PG14 PG15 PPICLK/TMRCLK PF0 PF2 PF14 PF15 PH0 PH1 PH2 PH4 ADCLRC ADCDAT DACLRC DACDAT BCLK PF9 XTO XTI/MCLK GND PG7 PG9 PG11 PG10 VDDINT GND PPIFS1/TMR0 PF1 PF3 PF5 PF4 PF6 PF7 PH3 PF10 PF8 PF11 PF12 PF13 LHPOUT RHPOUT SCL Ball No. B23 C1 C2 C22 C23 D1 D2 D22 D23 E1 E2 E22 E23 F1 F2 F22 F23 G1 G2 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G22 G23 H1 H2 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 Signal Ball No. CSCL H22 PG8 H23 PG6 J1 SDA J2 CSDA J7 PG4 J8 PG5 J9 CCLKOUT J10 CSB J11 BMODE2 J12 BMODE3 J13 CMODE J14 LLINEIN J15 PG3 J16 BMODE1 J17 LOUT J22 RLINEIN J23 PG1 K1 BMODE0 K2 VDDEXT K7 VDDEXT K8 VDDEXT K9 VDDEXT K10 VDDEXT K11 VDDEXT K12 VDDEXT K13 VDDEXT K14 VDDEXT K15 AVDD K16 AGND K17 ROUT K22 VMID K23 PG2 L1 PG0 L2 VDDEXT L7 VDDINT L8 VDDINT L9 VDDINT L10 VDDINT L11 VDDINT L12 VDDINT L13 VDDINT L14 VDDINT L15 VDDINT L16 VDDEXT L17 Signal Ball No. AGND L22 MICBIAS L23 TDI M1 EMU M2 VDDMEM M7 VDDINT M8 GND M9 GND M10 GND M11 GND M12 GND M13 GND M14 GND M15 VDDINT M16 VDDEXT M17 AVDD M22 MICIN M23 TDO N1 TRST N2 VDDMEM N7 VDDINT N8 GND N9 GND N10 GND N11 GND N12 GND N13 GND N14 GND N15 VDDINT N16 VDDEXT N17 PH6 N22 PH5 N23 TCK P1 TMS P2 VDDMEM P7 VDDINT P8 GND P9 GND P10 GND P11 GND P12 GND P13 GND P14 GND P15 VDDINT P16 VDDEXT P17 Rev. PrB Signal Ball No. PH8 P22 PH7 P23 DATA15 R1 DATA14 R2 VDDMEM R7 VDDINT R8 GND R9 GND R10 GND R11 GND R12 GND R13 GND R14 GND R15 VDDINT R16 VDDEXT R17 PH10 R22 PH12 R23 DATA12 T1 DATA13 T2 VDDMEM T7 VDDINT T8 GND T9 GND T10 GND T11 GND T12 GND T13 GND T14 GND T15 VDDINT T16 VDDEXT T17 PH13 T22 PH14 T23 DATA9 U1 DATA10 U2 VDDMEM U7 VDDINT U8 GND U9 GND U10 GND U11 GND U12 GND U13 GND U14 GND U15 VDDINT U16 VDDEXT U17 Signal PH15 XTAL DATA8 DATA11 VDDMEM VDDINT GND GND GND GND GND GND GND VDDINT VDDEXT PH11 CLKIN DATA7 DATA6 VDDMEM VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDEXT GND PH9 DATA5 DATA3 VDDMEM VDDMEM VDDMEM VDDMEM VDDMEM VDDMEM VDDMEM VDDMEM VDDMEM VDDMEM VDDEXT | Page 8 of 12 | June 2007 Ball No. U22 U23 V1 V2 V22 V23 W1 W2 W22 W23 Y1 Y2 Y22 Y23 AA1 AA2 AA22 AA23 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AC1 AC2 AC3 AC4 Signal NMI RTXI DATA4 DATA1 RESET RTXO DATA2 ADDR16 VDDUSB VDDRTC DATA0 ADDR17 USB_ID VDDUSB ADDR18 ADDR15 USB_DP USB_XTALOUT ADDR19 ADDR13 ADDR11 ADDR7 ADDR8 ADDR6 ADDR3 ADDR1 ABE0/SDQM0 SWE OTPVPP SRAS SCKE AWE AMS3 AMS1 ARE CLKOUT CLKBUF USB_VBUS USB_DM VRSEL USB_XTALIN GND ADDR14 ADDR12 ADDR10 Ball No. AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 Signal ADDR9 ADDR5 ADDR4 ADDR2 ABE1/SDQM1 SA10 SCAS VDDOTP SMS ARDY AOE AMS2 AMS0 VROUT EXT_WAKE SS/PG USB_RSET USB_VREF GND ADSP-BF522C/ADSP-BF525C/ADSP-BF527C Preliminary Technical Data Figure 5 shows the top view of the mini-BGA ball configuration. Figure 4 shows the bottom view of the mini-BGA ball configuration. Table 5. Thermal Characteristics (BC-289) Parameter θJA θJMA θJMA θJB θJC Condition 0 linear m/s air flow 1 linear m/s air flow 2 linear m/s air flow Typical tbd tbd tbd tbd tbd Unit ⴗC/W ⴗC/W ⴗC/W ⴗC/W ⴗC/W A1 BALL PAD CORNER A B C D E F G H J K L M N P KEY: R V DDINT GND V DDEXT I/O T AGND U V V W DDMEM Y AVDD AA AB AC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 TOP VIEW Figure 4. 289-Ball Mini-BGA Ball Configuration (Top View) Rev. PrB | Page 9 of 12 | June 2007 ADSP-BF522C/ADSP-BF525C/ADSP-BF527C Preliminary Technical Data A1 BALL PAD CORNER A B C D E F G H J K L M N P R T KEY: U V W Y AA AB AC V DDINT GND V DDEXT I/O AVDD 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BOTTOM VIEW Figure 5. 289-Ball Mini-BGA Ball Configuration (Bottom View) Rev. PrB | Page 10 of 12 | June 2007 AGND V DDMEM ADSP-BF522C/ADSP-BF525C/ADSP-BF527C Preliminary Technical Data OUTLINE DIMENSIONS Dimensions in the outline dimension figures are shown in millimeters. 289-BALL MINI BGA (BC-289-2) 0.5 BSC BALL PITCH 12.00 BSC SQ A1 BALL PAD CORNER 11.00 BSC SQ A1 BALL PAD CORNER CL A B C D E F G H J K L M N P R T U V W Y AA AB AC CL 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 TOP VIEW BOTTOM VIEW 1.40 1.26 1.11 0.20 MIN DETAIL A SIDE VIEW NOTES 1. DIMENSIONS ARE IN MILLIMETERS. 2. COMPLIES WITH JEDEC REGISTERED OUTLINE MO-195, VARIATION AJ AND EXCEPTION TO PACKAGE HEIGHT AND BALL HEIGHT. 3. MINIMUM BALL HEIGHT 0.20 0.08 MAX COPLANARITY 0.35 BALL DIAMETER 0.30 0.25 SEATING PLANE DETAIL A Figure 6. 289-Ball Chip Scale Package Ball Grid Array (Mini-BGA) SURFACE MOUNT DESIGN Table 6 is provided as an aid to PCB design. For industrystandard design recommendations, refer to IPC-7351, Generic Requirements for Surface Mount Design and Land Pattern Standard. Table 6. BGA Data for Use with Surface Mount Design Package 289-Ball Chip Scale Package Ball Grid Array (Mini-BGA) Rev. PrB Ball Attach Type Solder Mask Defined | Page 11 of 12 | June 2007 Solder Mask Opening 0.26 mm diameter Ball Pad Size 0.35 mm diameter ADSP-BF522C/ADSP-BF525C/ADSP-BF527C Preliminary Technical Data ORDERING GUIDE Temperature Package Instruction Operating Voltage Model Range1 Package Description Option Rate (Max) (Nom) ADSPBF527KBCZENGC1 0ºC to +70ºC 289-Ball Chip Scale Package Ball Grid Array BC-289 600 MHz tbd V internal, 1.8 V or 3.3 V I/O (Mini-BGA) 1 Referenced temperature is ambient temperature. ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06876-0-6/07(PrB) Rev. PrB | Page 12 of 12 | June 2007