AD ADSP-21160NKB-95

PRELIMINARY TECHNICAL DATA
a
DSP Microcomputer
ADSP-21160N
Preliminary Technical Data
SUMMARY
High-Performance 32-Bit DSP—Applications in Audio,
Medical, Military, Graphics, Imaging, and
Communication
Super Harvard Architecture—Four Independent Buses
for Dual Data Fetch, Instruction Fetch, and
Nonintrusive, Zero-Overhead I/O
Backwards-Compatible—Assembly Source Level
Compatible with Code for ADSP-2106x DSPs
Single-Instruction-Multiple-Data (SIMD) Computational
Architecture—Two 32-Bit IEEE Floating-Point
Computation Units, Each with a Multiplier, ALU,
Shifter, and Register File
Integrated Peripherals—Integrated I/O Processor,
4 M Bits On-Chip Dual-Ported SRAM, Glueless
Multiprocessing Features, and Ports (Serial, Link,
External Bus, and JTAG)
KEY FEATURES
95 MHz (10.5 ns) Core Instruction Rate
Single-Cycle Instruction Execution, Including SIMD
Operations in Both Computational Units
570 MFLOPS Peak and 380 MFLOPS Sustained
Performance (Based on FIR)
Dual Data Address Generators (DAGs) with Modulo and
Bit-Reverse Addressing
Zero-Overhead Looping and Single-Cycle Loop Setup,
Providing Efficient Program Sequencing
IEEE 1149.1 JTAG Standard Test Access Port and
On-Chip Emulation
400-Ball 27 ⴛ 27 mm Metric PBGA Package
FUNCTIONAL BLOCK DIAGRAM
CORE PROCESSOR
DAG1
8X4X32
DAG2
8X4X32
PROCESSOR PORT
ADDR
DATA
ADDR
DATA
I/O PORT
DATA
ADDR
DATA
ADDR
JTAG
BLOCK 1
TWO INDEPENDENT
DUAL-PORTED BLOCKS
6
TEST AND
EMULATION
PROGRAM
SEQUENCER
PM ADDRESS BUS
32
DM ADDRESS BUS
32
PM DATA BUS
BUS
CONNECT
(PX)
INSTRUCTION
CACHE
32 X 48-BIT
BLOCK 0
TIMER
DUAL-PORTED SRAM
DM DATA BUS
IOD
64
EXTERNAL
PORT
IOA
18
ADDR BUS
MUX
32
MULTIPROCESSOR
INTERFACE
16/32/40/48/64
DATA BUS
MUX
32/40/64
64
HOST PORT
MULT
DATA
REGISTER
FILE
(PEX)
16 X 40-BIT
BARREL
SHIFTER
ALU
BARREL
SHIFTER
DATA
REGISTER
FILE
(PEY)
16 X 40-BIT
ALU
MULT
DMA
CONTROLLER
IOP
REGISTERS
(MEMORY
MAPPED)
4
6
SERIAL PORTS
(2)
CONTROL,
STATUS, AND
DATA BUFFERS
LINK PORTS
(6)
6
60
I/O PROCESSOR
REV. PrB
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices
assumes no obligation regarding future manufacturing unless otherwise agreed to in
writing.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700
www.analog.com
Fax:781/326-8703
©Analog Devices,Inc., 2002
PRELIMINARY TECHNICAL DATA
April 2002
For current information contact Analog Devices at 800/262-5643
FEATURES (CONTINUED)
Single Instruction Multiple Data (SIMD)
Architecture Provides:
Two Computational Processing Elements
Concurrent Execution—Each Processing Element
Executes the Same Instruction, but Operates on
Different Data
Code Compatibility—at Assembly Level, Uses the
Same Instruction Set as the ADSP-2106x
SHARC DSPs
Parallelism in Buses and Computational Units Allows:
Single-cycle Execution (with or without SIMD) of: A
Multiply Operation, An ALU Operation, A Dual
Memory Read or Write, and An Instruction Fetch
Transfers Between Memory and Core at up to Four
32-Bit Floating- or Fixed-Point Words per Cycle
Accelerated FFT Butterfly Computation Through a
Multiply with Add and Subtract
4M Bits On-Chip Dual-Ported SRAM for Independent
Access by Core Processor, Host, and DMA
DMA Controller supports:
14 Zero-Overhead DMA Channels for Transfers Between
ADSP-21160N Internal Memory and External Memory,
External Peripherals, Host Processor, Serial Ports, or
Link Ports
64-Bit Background DMA Transfers at Core Clock Speed,
in Parallel with Full-Speed Processor Execution
665M Bytes/s Transfer Rate Over IOP Bus
Host Processor Interface to 16- and 32-Bit
Microprocessors
4G Word Address Range for Off-Chip Memory
Memory Interface Supports Programmable Wait State
Generation and Page-Mode for Off-Chip Memory
Multiprocessing Support Provides:
Glueless Connection for Scalable DSP Multiprocessing
Architecture
Distributed On-Chip Bus Arbitration for Parallel Bus
Connect of up to Six ADSP-21160Ns plus Host
Six Link Ports for Point-To-Point Connectivity and Array
Multiprocessing
Serial Ports Provide:
Two 47.5M Bits/s Synchronous Serial Ports with
Companding Hardware
Independent Transmit and Receive Functions
TDM Support for T1 and E1 Interfaces
64-Bit Wide Synchronous External Port Provides:
Glueless Connection to Asynchronous and SBSRAM
External Memories
Up to 47.5 MHz Operation
ADSP-21160N
GENERAL DESCRIPTION
The ADSP-21160N SHARC DSP is the second iteration
of the ADSP-21160. Built in a 0.18 micron CMOS process,
it offers higher performance and lower power consumption
than its predecessor, the ADSP-21160M. Easing portability, the ADSP-21160N is application source code
compatible with first generation ADSP-2106x SHARC
DSPs in SISD (Single Instruction, Single Data) mode. To
take advantage of the processor’s SIMD (Single Instruction,
Multiple Data) capability, some code changes are needed.
Like other SHARCs, the ADSP-21160N is a 32-bit
processor that is optimized for high performance DSP applications. The ADSP-21160N includes an 95 MHz core, a
dual-ported on-chip SRAM, an integrated I/O processor
with multiprocessing support, and multiple internal buses
to eliminate I/O bottlenecks.
The ADSP-21160N introduces Single-Instruction,
Multiple-Data (SIMD) processing. Using two computational units (ADSP-2106x SHARC DSPs have one), the
ADSP-21160N can double performance versus the
ADSP-2106x on a range of DSP algorithms.
Fabricated in a state of the art, high speed, low power
CMOS process, the ADSP-21160N has a 10.5 ns instruction cycle time. With its SIMD computational hardware
running at 95 MHz, the ADSP-21160N can perform 570
million math operations per second.
Table 1 shows performance benchmarks for the
ADSP-21160N.
Table 1. ADSP-21160N Benchmarks
Benchmark Algorithm
Speed
1024 Point Complex FFT (Radix 4, with
reversal)
FIR Filter (per tap)
IIR Filter (per biquad)
Matrix Multiply (pipelined)
[3ⴛ3] ⴛ [3ⴛ1]
Matrix Multiply (pipelined)
[4ⴛ4] ⴛ [4ⴛ1]
Divide (y/x)
Inverse Square Root
DMA Transfer Rate
96 µs
5.25 ns
21 ns
47.25 ns
84 ns
31.5 ns
47.25 ns
665M Bytes/s
These benchmarks provide single-channel extrapolations of
measured dual-channel processing performance. For more
information on benchmarking and optimizing DSP code for
single- and dual-channel processing, see Analog Devices’s
website.
The ADSP-21160N continues SHARC’s industry-leading
standards of integration for DSPs, combining a
high-performance 32-bit DSP core with integrated, on-chip
system features. These features include a 4M-bit dual
ported SRAM memory, host processor interface, I/O
REV. PrB
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
2
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
April 2002
processor that supports 14 DMA channels, two serial ports,
six link ports, external parallel bus, and glueless
multiprocessing.
The functional block diagram on page 1 shows a block
diagram of the ADSP-21160N, illustrating the following
architectural features:
• Two processing elements, each made up of an ALU, Multiplier, Shifter, and Data Register File
• Data Address Generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core every core
processor cycle
• Interval timer
• On-Chip SRAM (4M bits)
• Interfacing to off-chip memory peripherals
• Glueless multiprocessing support for six
ADSP-21160N SHARCs
• Host port
• DMA controller
• Serial ports and link ports
• JTAG test access port
Figure 1 shows a typical single-processor system. A multiprocessing system appears in Figure 4.
ADSP-21160
CLKIN
FLAG3–0
TIMEXP
LINK
DEVICES
(6 MAX)
(OPTIONAL)
LXCLK
LXACK
LXDAT7–0
SERIAL
DEVICE
(OPTIONAL)
TCLK0
RCLK0
TFS0
RSF0
DT0
DR0
SERIAL
DEVICE
(OPTIONAL)
TCLK1
RCLK1
TFS1
RSF1
DT1
DR1
RPBA
ID2–0
RESET
DATA
BRST
ADDR31–0
ADDR
DATA63–0
DATA
RDx
OE
WRx
ACK
WE
ACK
PAGE
SBTS
CLKOUT
DMAR1–2
BOOT
EPROM
(OPTIONAL)
MEMORY/
MAPPED
DEVICES
(OPTIONAL)
SIMD Computational Engine
The ADSP-21160N contains two computational processing elements that operate as a Single Instruction Multiple
Data (SIMD) engine. The processing elements are referred
to as PEX and PEY, and each contains an ALU, multiplier,
shifter, and register file. PEX is always active, and PEY may
be enabled by setting the PEYEN mode bit in the MODE1
register. When this mode is enabled, the same instruction
is executed in both processing elements, but each processing
element operates on different data. This architecture is
efficient at executing math-intensive DSP algorithms.
Independent, Parallel Computation Units
Within each processing element is a set of computational
units. The computational units consist of an arithmetic/logic unit (ALU), multiplier, and shifter. These units
perform single-cycle instructions. The three units within
each processing element are arranged in parallel, maximizing computational throughput. Single multifunction
instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier
operations occur in both processing elements. These computation units support IEEE 32-bit single-precision
floating-point, 40-bit extended precision floating-point,
and 32-bit fixed-point data formats.
Data Register File
DMA DEVICE
(OPTIONAL)
DATA
DMAG1–2
CS
HBR
HBG
REDY
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
BR1–6
ADDR
PA
DATA
JTAG
6
Figure 1. Single-Processor System
REV. PrB
The ADSP-21160N includes the following architectural features of the ADSP-2116x family core. The
ADSP-21160N is code compatible at the assembly level
with the ADSP-2106x and ADSP-21161.
CS
MS3–0
DATA
4
EBOOT
LBOOT
IRQ2–0
ADDR
CIF
ADDRESS
3
CS
BMS
CLK_CFG3–0
CONTROL
4
ADSP-21160N Family Core Architecture
Entering SIMD mode also has an effect on the way data is
transferred between memory and the processing elements.
When in SIMD mode, twice the data bandwidth is required
to sustain computational operation in the processing
elements. Because of this requirement, entering SIMD
mode also doubles the bandwidth between memory and the
processing elements. When using the DAGs to transfer data
in SIMD mode, two data values are transferred with each
access of memory or the register file.
• External port that supports:
CLOCK
ADSP-21160N
A general-purpose data register file is contained in each
processing element. The register files transfer data between
the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16
secondary) register files, combined with the ADSP-2116x
enhanced Harvard architecture, allow unconstrained data
flow between computation units and internal memory. The
registers in PEX are referred to as R0–R15 and in PEY
as S0–S15.
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-21160N features an enhanced Harvard architecture in which the data memory (DM) bus transfers data,
and the program memory (PM) bus transfers both instructions and data (see the functional block diagram on page 1).
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
3
PRELIMINARY TECHNICAL DATA
April 2002
For current information contact Analog Devices at 800/262-5643
With the ADSP-21160N’s separate program and data
memory buses and on-chip instruction cache, the processor
can simultaneously fetch four operands and an instruction
(from the cache), all in a single cycle.
Instruction Cache
The ADSP-21160N includes an on-chip instruction cache
that enables three-bus operation for fetching an instruction
and four data values. The cache is selective—only the
instructions whose fetches conflict with PM bus data
accesses are cached. This cache allows full-speed execution
of core, providing looped operations such as digital filter
multiply- accumulates and FFT butterfly processing.
Data Address Generators with Hardware
Circular Buffers
The ADSP-21160N’s two data address generators (DAGs)
are used for indirect addressing and provide for implementing circular data buffers in hardware. Circular buffers allow
efficient programming of delay lines and other data structures required in digital signal processing, and are
commonly used in digital filters and Fourier transforms.
The two DAGs of the ADSP-21160N contain sufficient
registers to allow the creation of up to 32 circular buffers
(16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reducing
overhead, increasing performance, and simplifying implementation. Circular buffers can start and end at any
memory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of
parallel operations, for concise programming. For example,
the ADSP-21160N can conditionally execute a multiply, an
add, and subtract, in both processing elements, while
branching, all in a single instruction.
ADSP-21160N Memory and I/O Interface Features
Augmenting the ADSP-2116x family core, the
ADSP-21160N adds the following architectural features:
Dual-Ported On-Chip Memory
The ADSP-21160N contains four megabits of on-chip
SRAM, organized as two blocks of 2M bits each, which can
be configured for different combinations of code and data
storage. Each memory block is dual-ported for single-cycle,
independent accesses by the core processor and I/O processor. The dual-ported memory in combination with three
separate on-chip buses allows two data transfers from the
core and one from I/O processor, in a single cycle. On the
ADSP-21160N, the memory can be configured as a
maximum of 128K words of 32-bit data, 256K words of
16-bit data, 85K words of 48-bit instructions (or 40-bit
data), or combinations of different word sizes up to four
megabits. All of the memory can be accessed as 16-bit,
32-bit, 48-bit, or 64-bit words. A 16-bit floating-point
storage format is supported that effectively doubles the
amount of data that may be stored on-chip. Conversion
REV. PrB
ADSP-21160N
between the 32-bit floating-point and 16-bit floating-point
formats is done in a single instruction. While each memory
block can store combinations of code and data, accesses are
most efficient when one block stores data, using the DM
bus for transfers, and the other block stores instructions and
data, using the PM bus for transfers. Using the DM bus and
PM bus in this way, with one dedicated to each memory
block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in
the cache.
Off-Chip Memory and Peripherals Interface
The ADSP-21160N’s external port provides the processor’s
interface to off-chip memory and peripherals. The 4G word
off-chip address space is included in the ADSP-21160N’s
unified address space. The separate on-chip buses—for PM
addresses, PM data, DM addresses, DM data, I/O
addresses, and I/O data—are multiplexed at the external
port to create an external system bus with a single 32-bit
address bus and a single 64-bit data bus. The lower 32 bits
of the external data bus connect to even addresses and the
upper 32 bits of the 64 connect to odd addresses. Every
access to external memory is based on an address that
fetches a 32-bit word, and with the 64-bit bus, two address
locations can be accessed at once. When fetching an instruction from external memory, two 32-bit data locations are
being accessed (16 bits are unused). Figure 3 shows the
alignment of various accesses to external memory.
The external port supports asynchronous, synchronous,
and synchronous burst accesses. ZBT synchronous burst
SRAM can be interfaced gluelessly. Addressing of external
memory devices is facilitated by on-chip decoding of
high-order address lines to generate memory bank select
signals. Separate control lines are also generated for simplified addressing of page-mode DRAM. The ADSP-21160N
provides programmable memory wait states and external
memory acknowledge controls to allow interfacing to
DRAM and peripherals with variable access, hold, and
disable time requirements.
DMA Controller
The ADSP-21160N’s on-chip DMA controller allows
zero-overhead data transfers without processor intervention. The DMA controller operates independently and
invisibly to the processor core, allowing DMA operations to
occur while the core is simultaneously executing its program
instructions. DMA transfers can occur between the
ADSP-21160N’s internal memory and external memory,
external peripherals, or a host processor. DMA transfers can
also occur between the ADSP-21160N’s internal memory
and its serial ports or link ports. External bus packing to
16-, 32-, 48-, or 64-bit words is performed during DMA
transfers. Fourteen channels of DMA are available on the
ADSP-21160N—six via the link ports, four via the serial
ports, and four via the processor’s external port (for either
host processor, other ADSP-21160Ns, memory or I/O
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
4
PRELIMINARY TECHNICAL DATA
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April 2002
Internal
Memory
Space
IOP Reg’s
0x00 0000
Long Word
0x02 0000
0x04 0000
Normal Word
Short Word
Internal
ADSP-21160N
0x80 0000
Bank 0
MS0
DATA63–0
63
55
47
39
31
23
15
BYTE 7
0x08 0000
7
0
BYTE 0
RDL/WRL
RDH/WRH
0x10 0000
64-BIT LONG WORD, SIMD, DMA, IOP REGISTER TRANSFERS
Memory
Space
Bank 1
MS1
64-BIT TRANSFER FOR 48-BIT INSTRUCTION FETCH
(ID = 001)
64-BIT TRANSFER FOR 40-BIT EXTENDED PRECISION
Internal
0x20 0000
32-BIT NORMAL WORD (EVEN ADDRESS)
Memory
Space
Bank 2
MS2
32-BIT NORMAL WORD (ODD ADDRESS)
(ID = 010)
RESTRICTED DMA, HOST, EPROM DATA ALIGNMENTS:
Internal
0x30 0000
32-BIT PACKED
Memory
Bank 3
Space
MS3
16-BIT PACKED
(ID = 011)
EPROM
0x40 0000
Multiprocessor
Memory
Space
Internal
Memory
External
Memory
Space
Space
(ID = 100)
Internal
0x50 0000
ify-write sequences for semaphores. A vector interrupt is
provided for interprocessor commands. Maximum
throughput for interprocessor data transfer is 380M bytes/s
over the external port. Broadcast writes allow simultaneous
transmission of data to all ADSP-21160Ns and can be used
to implement reflective semaphores.
Memory
Space
(ID = 101)
Internal
0x60 0000
Nonbanked
Memory
Space
(ID = 110)
Broadcast
Figure 3. ADSP-21160N External Data Alignment
Options
0x70 0000
Write to
All DSPs
(ID = 111)
0x7F FFFF
0xFFFF FFFF
Six link ports provide for a second method of multiprocessing communications. Each link port can support
communications to another ADSP-21160N. Using the
links, a large multiprocessor system can be constructed in a
2D or 3D fashion. Systems can use the link ports and cluster
multiprocessing concurrently or independently.
Figure 2. ADSP-21160N Memory Map
Link Ports
transfers). Programs can be downloaded to the
ADSP-21160N using DMA transfers. Asynchronous
off-chip peripherals can control two DMA channels using
DMA Request/Grant lines (DMAR1–2, DMAG1–2).
Other DMA features include interrupt generation upon
completion of DMA transfers, two-dimensional DMA, and
DMA chaining for automatic linked DMA transfers.
Multiprocessing
The ADSP-21160N offers powerful features tailored to
multiprocessing DSP systems as shown in Figure 4. The
external port and link ports provide integrated glueless multiprocessing support.
The external port supports a unified address space (see
Figure 2) that allows direct interprocessor accesses of each
ADSP-21160N’s internal memory. Distributed bus arbitration logic is included on-chip for simple, glueless connection
of systems containing up to six ADSP-21160Ns and a host
processor. Master processor changeover incurs only one
cycle of overhead. Bus arbitration is selectable as either fixed
or rotating priority. Bus lock allows indivisible read-modREV. PrB
The ADSP-21160N features six 8-bit link ports that provide
additional I/O capabilities. With the capability of running
at 95 MHz rates, each link port can support 95M bytes/s.
Link port I/O is especially useful for point-to-point interprocessor communication in multiprocessing systems. The
link ports can operate independently and simultaneously.
Link port data is packed into 48- or 32-bit words, and can
be directly read by the core processor or DMA-transferred
to on-chip memory. Each link port has its own double-buffered input and output registers. Clock/acknowledge
handshaking controls link port transfers. Transfers are programmable as either transmit or receive.
Serial Ports
The ADSP-21160N features two synchronous serial ports
that provide an inexpensive interface to a wide variety of
digital and mixed-signal peripheral devices. The serial ports
can operate up to half the clock rate of the core, providing
each with a maximum data rate of 47.5M bit/s. Independent
transmit and receive functions provide greater flexibility for
serial communications. Serial port data can be automati-
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
5
PRELIMINARY TECHNICAL DATA
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ADSP-21160#3
CLKIN
RESET
Host Processor Interface
ADDR31–0
The ADSP-21160N host interface allows easy connection
to standard microprocessor buses, both 16-bit and 32-bit,
with little additional hardware required. The host interface
is accessed through the ADSP-21160N’s external port and
is memory-mapped into the unified address space. Four
channels of DMA are available for the host interface; code
and data transfers are accomplished with low software
overhead. The host processor communicates with the
ADSP-21160M’s external bus with host bus request
(HBR), host but grant (HBG), ready (REDY), acknowledge
(ACK), and chip select (CS) signals. The host can directly
read and write the internal memory of the ADSP-21160N,
and can access the DMA channel setup and mailbox registers. Vector interrupt support provides efficient execution
of host commands.
DATA63–0
RPBA
3
ID2–0
CONTROL
011
PA
BR1–2, BR4–6
5
BR3
ADSP-21160#2
CLKIN
ADDR31–0
RESET
DATA63–0
Program Booting
RPBA
The internal memory of the ADSP-21160N can be booted
at system power-up from an 8-bit EPROM, a host processor, or through one of the link ports. Selection of the boot
source is controlled by the BMS (Boot Memory Select),
EBOOT (EPROM Boot), and LBOOT (Link/Host Boot)
pins. 32-bit and 16-bit host processors can be used
for booting.
3
ID2–0
CONTROL
010
5
CLKIN
ADDR31–0
ADDR
DATA63–0
DATA
RDx
ID2–0
WRx
ACK
MS3–0
001
CONTROL
RPBA
3
DATA
ADSP-21160#1
ADDRESS
Phased Locked Loop
CONTROL
PA
BR1, BR3–6
BR2
RESET
OE
WE
GLOBALMEMORY
AND
PERIPHERAL(OPTIONAL)
ACK
CS
BMS
PAGE
CS
ADDR
SBTS
CLOCK
BOOTEPROM(OPTIONAL)
DATA
CS
HBR
HBG
REDY
PA
BR2–6
BR1
HOSTPROCESSOR
INTERFACE(OPTIONAL)
ADDR
5
DATA
Figure 4. Shared Memory Multiprocessing System
cally transferred to and from on-chip memory via a
dedicated DMA. Each of the serial ports offers a TDM
multichannel mode. The serial ports can operate with little-endian or big-endian transmission formats, with word
lengths selectable from 3 bits to 32 bits. They offer selectable
REV. PrB
The ADSP-21160N uses an on-chip PLL to generate the
internal clock for the core. Ratios of 2:1, 3:1, and 4:1
between the core and CLKIN are supported. The
CLK_CFG pins are used to select the ratio. The CLKIN
rate is the rate at which the synchronous external
port operates.
Power Supplies
CLKOUT
RESET
ADSP-21160N
synchronization and transmit modes as well as optional
µ-law or A-law companding. Serial port clocks and frame
syncs can be internally or externally generated.
DATA
CONTROL
ADSP-21160#6
ADSP-21160#5
ADSP-21160#4
ADDRESS
April 2002
The ADSP-21160N has separate power supply connections
for the internal (VDDINT), external (VDDEXT), and analog
(AVDD /AGND) power supplies. The internal and analog
supplies must meet the 1.9 V requirement. The external
supply must meet the 3.3 V requirement. All external supply
pins must be connected to the same supply.
The PLL Filter Figure 5 on page 7 must be added for each
ADSP-21160N in the system. VDDint is the digital core
supply. It is recommended that the capacitors be connected
directly to AGND using short thick trace. It is recommended that the capacitors be placed as close to AVDD and
AGND as possible. The connection from AGND to the
(digital) ground plane should be made after the capacitors.
The use of a thick trace for AGND is reasonable only
because the PLL is a relatively low power circuit - it does
not apply to any other ADSP-21160N GND connection.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
6
PRELIMINARY TECHNICAL DATA
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April 2002
10⍀
VDDINT
AVDD
0.1␮F
0.01␮F
AGND
Figure 5. Analog Power (AVDD) Filter Circuit
Development Tools
The ADSP-21160N is supported with a complete set of
software and hardware development tools, including Analog
Devices’ emulators and VisualDSP++1 development environment. The same emulator hardware that supports other
ADSP-2116x DSPs, also fully emulates the
ADSP-21160N.
The VisualDSP++ project management environment lets
programmers develop and debug an application. This environment includes an easy-to-use assembler that is based on
an algebraic syntax; an archiver (librarian/library builder),
a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ run-time library that
includes DSP and mathematical functions. Two key points
for these tools are:
• Compiled ADSP-2116x C/C++ code efficiency—the
compiler has been developed for efficient translation of
C/C++ code to ADSP-2116x assembly. The DSP has
architectural features that improve the efficiency of
compiled C/C++ code.
• ADSP-2106x family code compatibility—The assembler
has legacy features to ease the conversion of existing
ADSP-2106x applications to the ADSP-2116x.
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:
• View mixed C/C++ and assembly code (interleaved
source and object information)
• Insert break points
• Set conditional breakpoints on registers, memory, and
stacks
ADSP-21160N
of the ADSP-2116x development tools, including the syntax
highlighting in the VisualDSP++ editor. This capability
permits:
• Control how the development tools process inputs and
generate outputs.
• Maintain a one-to-one correspondence with the tool’s
command line switches.
Analog Devices’ DSP emulators use the IEEE 1149.1 JTAG
test access port of the ADSP-21160N processor to monitor
and control the target board processor during emulation.
The emulator provides full-speed emulation, allowing
inspection and modification of memory, registers, and
processor stacks. Nonintrusive in-circuit emulation is
assured by the use of the processor’s JTAG interface—the
emulator does not affect target system loading or timing.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the ADSP-2116x processor
family. Hardware tools include ADSP-2116x PC plug-in
cards. Third Party software tools include DSP libraries,
real-time operating systems, and block diagram
design tools.
Designing an Emulator-Compatible DSP Board
(Target)
The White Mountain DSP (Product Line of Analog
Devices, Inc.) family of emulators are tools that every DSP
developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1
JTAG Test Access Port (TAP) on each JTAG DSP. The
emulator uses the TAP to access the internal features of the
DSP, allowing the developer to load code, set breakpoints,
observe variables, observe memory, and examine registers.
The DSP must be halted to send data and commands, but
once an operation has been completed by the emulator, the
DSP system is set running at full speed with no impact on
system timing.
• Trace instruction execution
To use these emulators, the target’s design must include the
interface between an Analog Devices’ JTAG DSP and the
emulation header on a custom DSP target board.
• Perform linear or statistical profiling of program
execution
Target Board Header
• Fill, dump, and graphically plot the contents of memory
• Source level debugging
• Create custom debugger windows
The VisualDSP++ IDE lets programmers define and
manage DSP software development. Its dialog boxes and
property pages let programmers configure and manage all
1
The emulator interface to an Analog Devices’ JTAG DSP
is a 14-pin header, as shown in Figure 6. The customer must
supply this header on the target board in order to communicate with the emulator. The interface consists of a
standard dual row 0.025" square post header, set on
0.1" ⴛ 0.1" spacing, with a minimum post length of 0.235".
Pin 3 is the key position used to prevent the pod from being
inserted backwards. This pin must be clipped on the
target board.
VisualDSP++ is a registered trademark of Analog Devices, Inc.
REV. PrB
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
7
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
April 2002
Also, the clearance (length, width, and height) around the
header must be considered. Leave a clearance of at least
0.15" and 0.10" around the length and width of the header,
and reserve a height clearance to attach and detach the pod
connector.
ADSP-21160N
GND
1
2
3
4
GND
KEY (NO PIN)
5
6
BTMS
1
EMU
3
GND
5
7
BTRST
9
9
10
9
11
TMS
BTDI
TCK
GND
TRST
12
TDI
8
BTCK
8
TCK
6
BTMS
7
BTCK
4
KEY (NO PIN)
BTRST
TMS
2
GND
EMU
13
14
TDO
10
TRST
9
11
TDI
BTDI
13
TOP VIEW
12
14
Figure 7. JTAG Target Board Connector with No Local
Boundary Scan
TDO
GND
TOP VIEW
Figure 6. JTAG Target Board Connector for JTAG
Equipped Analog Devices DSP (Jumpers in
Place)
As can be seen in Figure 6, there are two sets of signals on
the header. There are the standard JTAG signals TMS,
TCK, TDI, TDO, TRST, and EMU used for emulation
purposes (via an emulator). There are also secondary JTAG
signals BTMS, BTCK, BTDI, and BTRST that are optionally used for board-level (boundary scan) testing.
0.64"
0.24"
0.88"
Figure 8. JTAG Pod Connector Dimensions
When the emulator is not connected to this header, place
jumpers across BTMS, BTCK, BTRST, and BTDI as
shown in Figure 7. This holds the JTAG signals in the
correct state to allow the DSP to run free. Remove all the
jumpers when connecting the emulator to the JTAG header.
JTAG Emulator Pod Connector
Figure 8 details the dimensions of the JTAG pod connector
at the 14-pin target end. Figure 9 displays the keep-out area
for a target board header. The keep-out area allows the pod
connector to properly seat onto the target board header.
This board area should contain no components (chips,
resistors, capacitors, etc.). The dimensions are referenced
to the center of the 0.25" square post pin.
Design-for-Emulation Circuit Information
For details on target board design issues including: single
processor connections, multiprocessor scan chains, signal
buffering, signal termination, and emulator pod logic, see
the EE-68: Analog Devices JTAG Emulation Technical
Reference on the Analog Devices website—use site search on
REV. PrB
0.10"
0.15"
Figure 9. JTAG Pod Connector Keep-Out Area
“EE-68” (www.analog.com). This document is updated
regularly to keep pace with improvements to emulator
support.
Additional Information
This data sheet provides a general overview of the
ADSP-21160N architecture and functionality. For detailed
information on the ADSP-2116x Family core architecture
and instruction set, refer to the ADSP-2116x SHARC DSP
Hardware Reference.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
8
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
April 2002
PIN FUNCTION DESCRIPTIONS
ADSP-21160N pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements
with respect to CLKIN (or with respect to TCK for TMS,
TDI). Inputs identified as asynchronous (A) can be asserted
asynchronously to CLKIN (or to TCK for TRST).
Tie or pull unused inputs to VDD or GND, except for the
following:
• ADDR31–0, DATA63–0, PAGE, BRST, CLKOUT
(ID2–0 = 00x) (NOTE: These pins have a logic-level hold
circuit enabled on the ADSP-21160N DSP with ID2–0
= 00x)
ADSP-21160N
• LxCLK, LxACK, LxDAT7–0 (LxPDRDE = 0) (NOTE:
See Link Port Buffer Control Register Bit definitions in
the ADSP-21160 DSP Hardware Reference).
• DTx, DRx, TCLKx, RCLKx, EMU, TMS, TRST, TDI
(NOTE: These pins have a pull-up.)
The following symbols appear in the Type column of
Table 2: A = Asynchronous, G = Ground, I = Input,
O = Output, P = Power Supply, S = Synchronous,
(A/D) = Active Drive, (O/D) = Open Drain, and
T = Three-State (when SBTS is asserted, or when the
ADSP-21160N is a bus slave).
• PA, ACK, MS3–0, RDx, WRx, CIF, DMARx, DMAGx
(ID2–0 = 00x) (NOTE: These pins have a pull-up
enabled on the ADSP-21160N DSP with ID2–0 = 00x)
Table 2. Pin Function Descriptions
Pin
Type
Function
ADDR31–0
I/O/T
DATA63–0
I/O/T
MS3–0
O/T
RDL
I/O/T
RDH
I/O/T
WRL
I/O/T
External Bus Address. The ADSP-21160N outputs addresses for external memory and
peripherals on these pins. In a multiprocessor system, the bus master outputs addresses
for read/writes of the internal memory or IOP registers of other ADSP-21160Ns. The
ADSP-21160N inputs addresses when a host processor or multiprocessing bus master
is reading or writing its internal memory or IOP registers. A keeper latch on the DSP’s
ADDR31–0 pins maintains the input at the level it was last driven (only enabled on the
ADSP-21160N with ID2–0 = 00x).
External Bus Data. The ADSP-21160N inputs and outputs data and instructions on
these pins. Pull-up resistors on unused DATA pins are not necessary. A keeper latch on
the DSP’s DATA63-0 pins maintains the input at the level it was last driven (only enabled
on the ADSP-21160N with ID2–0 = 00x).
Memory Select Lines. These outputs are asserted (low) as chip selects for the corresponding banks of external memory. Memory bank size must be defined in the SYSCON
control register. The MS3–0 outputs are decoded memory address lines. In asynchronous access mode, the MS3–0 outputs transition with the other address outputs.
In synchronous access modes, the MS3–0 outputs assert with the other address lines;
however, they de-assert after the first CLKIN cycle in which ACK is sampled asserted.
MS3–0 has a 20kΩ internal pull-up resistor that is enabled on the ADSP-21160N with
ID2–0 = 00x.
Memory Read Low Strobe. RDL is asserted whenever ADSP-21160N reads from the
low word of external memory or from the internal memory of other ADSP-21160Ns.
External devices, including other ADSP-21160Ns, must assert RDL for reading from
the low word of ADSP-21160N internal memory. In a multiprocessing system, RDL is
driven by the bus master. RDL has a 20kΩ internal pull-up resistor that is enabled on
the ADSP-21160N with ID2–0 = 00x.
Memory Read High Strobe. RDH is asserted whenever ADSP-21160N reads from the
high word of external memory or from the internal memory of other ADSP-21160Ns.
External devices, including other ADSP-21160Ns, must assert RDH for reading from
the high word of ADSP-21160N internal memory. In a multiprocessing system, RDH
is driven by the bus master. RDH has a 20kΩ internal pull-up resistor that is enabled
on the ADSP-21160N with ID2–0 = 00x.
Memory Write Low Strobe. WRL is asserted when ADSP-21160N writes to the low
word of external memory or internal memory of other ADSP-21160Ns. External devices
must assert WRL for writing to ADSP-21160N’s low word of internal memory. In a
multiprocessing system, WRL is driven by the bus master. WRL has a 20kΩ internal
pull-up resistor that is enabled on the ADSP-21160N with ID2–0 = 00x.
REV. PrB
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
9
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
April 2002
ADSP-21160N
Table 2. Pin Function Descriptions (Continued)
Pin
Type
Function
WRH
I/O/T
PAGE
O/T
BRST
I/O/T
ACK
I/O/S
SBTS
I/S
IRQ2–0
I/A
FLAG3–0
I/O/A
TIMEXP
O
HBR
I/A
HBG
I/O
CS
I/A
Memory Write High Strobe. WRH is asserted when ADSP-21160N writes to the high
word of external memory or internal memory of other ADSP-21160Ns. External devices
must assert WRH for writing to ADSP-21160N’s high word of internal memory. In a
multiprocessing system, WRH is driven by the bus master. WRH has a 20kΩ internal
pull-up resistor that is enabled on the ADSP-21160N with ID2–0 = 00x.
DRAM Page Boundary. The ADSP-21160N asserts this pin to signal that an external
DRAM page boundary has been crossed. DRAM page size must be defined in the
ADSP-21160N’s memory control register (WAIT). DRAM can only be implemented
in external memory Bank 0; the PAGE signal can only be activated for Bank 0 accesses.
In a multiprocessing system PAGE is output by the bus master. A keeper latch on the
DSP’s PAGE pin maintains the output at the level it was last driven (only enabled on
the ADSP-21160N with ID2–0 = 00x).
Sequential Burst Access. BRST is asserted by ADSP-21160N or a host to indicate that
data associated with consecutive addresses is being read or written. A slave device
samples the initial address and increments an internal address counter after each
transfer. The incremented address is not pipelined on the bus. If the burst access is a
read from host to ADSP-21160N, ADSP-21160N automatically increments the address
as long as BRST is asserted. BRST is asserted after the initial access of a burst transfer.
It is asserted for every cycle after that, except for the last data request cycle (denoted by
RDx or WRx asserted and BRST negated). A keeper latch on the DSP’s BRST pin
maintains the input at the level it was last driven (only enabled on the ADSP-21160N
with ID2–0 = 00x).
Memory Acknowledge. External devices can de-assert ACK (low) to add wait states to
an external memory access. ACK is used by I/O devices, memory controllers, or other
peripherals to hold off completion of an external memory access. The ADSP-21160N
deasserts ACK as an output to add wait states to a synchronous access of its internal
memory. ACK has a 2kΩ internal pull-up resistor that is enabled on the ADSP-21160N
with ID2–0 = 00x.
Suspend Bus and Three-State. External devices can assert SBTS (low) to place the
external bus address, data, selects, and strobes in a high impedance state for the following
cycle. If the ADSP-21160N attempts to access external memory while SBTS is asserted,
the processor will halt and the memory access will not be completed until SBTS is
deasserted. SBTS should only be used to recover from host processor and/or
ADSP-21160N deadlock or used with a DRAM controller.
Interrupt Request Lines. These are sampled on the rising edge of CLKIN and may be
either edge-triggered or level-sensitive.
Flag Pins. Each is configured via control bits as either an input or output. As an input,
it can be tested as a condition. As an output, it can be used to signal external peripherals.
Timer Expired. Asserted for four Core Clock cycles when the timer is enabled and
TCOUNT decrements to zero.
Host Bus Request. Must be asserted by a host processor to request control of the
ADSP-21160N’s external bus. When HBR is asserted in a multiprocessing system, the
ADSP-21160N that is bus master will relinquish the bus and assert HBG. To relinquish
the bus, the ADSP-21160N places the address, data, select, and strobe lines in a high
impedance state. HBR has priority over all ADSP-21160N bus requests (BR6–1) in a
multiprocessing system.
Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor
may take control of the external bus. HBG is asserted (held low) by the ADSP-21160N
until HBR is released. In a multiprocessing system, HBG is output by the
ADSP-21160N bus master and is monitored by all others. After HBR is asserted, and
before HBG is given, HBG will float for 1 tCLK (1 CLKIN cycle). To avoid erroneous
grants, HBG should be pulled up with a 20k to 50k ohm external resistor.
Chip Select. Asserted by host processor to select the ADSP-21160N.
REV. PrB
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
10
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
April 2002
ADSP-21160N
Table 2. Pin Function Descriptions (Continued)
Pin
Type
Function
REDY
O (O/D)
DMAR1
I/A
DMAR2
I/A
ID2–0
I
DMAG1
O/T
DMAG2
O/T
BR6–1
I/O/S
RPBA
I/S
PA
I/O/T
DTx
DRx
TCLKx
RCLKx
TFSx
RFSx
LxDAT7–0
O
I
I/O
I/O
I/O
I/O
I/O
LxCLK
I/O
LxACK
I/O
EBOOT
I
LBOOT
I
BMS
I/O/T
Host Bus Acknowledge. The ADSP-21160N deasserts REDY (low) to add waitstates
to a host access when CS and HBR inputs are asserted.
DMA Request 1 (DMA Channel 11). Asserted by external port devices to request DMA
services. DMAR1 has a 20kΩ internal pull-up resistor that is enabled on the
ADSP-21160N with ID2–0 = 00x.
DMA Request 2 (DMA Channel 12). Asserted by external port devices to request DMA
services. DMAR2 has a 20kΩ internal pull-up resistor that is enabled on the
ADSP-21160N with ID2–0 = 00x.
Multiprocessing ID. Determines which multiprocessing bus request (BR1–BR6) is used
by ADSP-21160N. ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, and
so on. Use ID = 000 or ID = 001 in single-processor systems. These lines are a system
configuration selection which should be hardwired or only changed at reset.
DMA Grant 1 (DMA Channel 11). Asserted by ADSP-21160N to indicate that the
requested DMA starts on the next cycle. Driven by bus master only. DMAG1 has a
20kΩ internal pull-up resistor that is enabled on the ADSP-21160N with ID2–0 = 00x.
DMA Grant 2 (DMA Channel 12). Asserted by ADSP-21160N to indicate that the
requested DMA starts on the next cycle. Driven by bus master only. DMAG2 has a
20kΩ internal pull-up resistor that is enabled on the ADSP-21160N with ID2–0 = 00x.
Multiprocessing Bus Requests. Used by multiprocessing ADSP-21160Ns to arbitrate
for bus mastership. An ADSP-21160N only drives its own BRx line (corresponding to
the value of its ID2–0 inputs) and monitors all others. In a multiprocessor system with
less than six ADSP-21160Ns, the unused BRx pins should be pulled high; the processor’s
own BRx line must not be pulled high or low because it is an output.
Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for
multiprocessor bus arbitration is selected. When RPBA is low, fixed priority is selected.
This signal is a system configuration selection which must be set to the same value on
every ADSP-21160N. If the value of RPBA is changed during system operation, it must
be changed in the same CLKIN cycle on every ADSP-21160N.
Priority Access. Asserting its PA pin allows an ADSP-21160N bus slave to interrupt
background DMA transfers and gain access to the external bus. PA is connected to all
ADSP-21160Ns in the system. If access priority is not required in a system, the PA pin
should be left unconnected. PA has a 20kΩ internal pull-up resistor that is enabled on
the ADSP-21160N with ID2–0 = 00x.
Data Transmit (Serial Ports 0, 1). Each DT pin has a 50 kΩ internal pull-up resistor.
Data Receive (Serial Ports 0, 1). Each DR pin has a 50 kΩ internal pull-up resistor.
Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 kΩ internal pull-up resistor.
Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 kΩ internal pull-up resistor.
Transmit Frame Sync (Serial Ports 0, 1).
Receive Frame Sync (Serial Ports 0, 1).
Link Port Data (Link Ports 0–5). Each LxDAT pin has a 50 kΩ internal pull-down
resistor that is enabled or disabled by the LPDRD bit of the LCTL0–1 register.
Link Port Clock (Link Ports 0–5). Each LxCLK pin has a 50 kΩ internal pull-down
resistor that is enabled or disabled by the LPDRD bit of the LCTL0–1 register.
Link Port Acknowledge (Link Ports 0–5). Each LxACK pin has a 50 kΩ internal
pull-down resistor that is enabled or disabled by the LPDRD bit of the LCOM register.
EPROM Boot Select. For a description of how this pin operates, see Table 3. This signal
is a system configuration selection that should be hardwired.
Link Boot. For a description of how this pin operates, see Table 3. This signal is a system
configuration selection that should be hardwired.
Boot Memory Select. Serves as an output or input as selected with the EBOOT and
LBOOT pins; see Table 3. This input is a system configuration selection that should be
hardwired.
REV. PrB
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
11
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
April 2002
ADSP-21160N
Table 2. Pin Function Descriptions (Continued)
Pin
Type
Function
CLKIN
I
CLK_CFG3–0
I
CLKOUT
O/T
RESET
I/A
TCK
TMS
I
I/S
TDI
I/S
TDO
TRST
O
I/A
EMU
O (O/D)
CIF
O/T
VDDINT
P
VDDEXT
AVDD
P
P
AGND
GND
NC
G
G
Local Clock In. CLKIN is the ADSP-21160N clock input. The ADSP-21160N external
port cycles at the frequency of CLKIN. The instruction cycle rate is a multiple of the
CLKIN frequency; it is programmable at power-up. CLKIN may not be halted,
changed, or operated below the specified frequency.
Core/CLKIN Ratio Control. ADSP-21160N core clock (instruction cycle) rate is equal
to n ⴛ CLKIN where n is user-selectable to 2, 3, or 4, using the CLK_CFG3–0 inputs.
For clock configuration definitions, see the RESET & CLKIN section of the System
Design chapter of the ADSP-21160 SHARC DSP Hardware Reference manual.
CLKOUT is driven at the CLKIN frequency by the ADSP-21160N. This output can
be three-stated by setting the COD bit in the SYSCON register. A keeper latch on the
DSP’s CLKOUT pin maintains the output at the level it was last driven (only enabled
on the ADSP-21160N with ID2-0 = 00x).
Processor Reset. Resets the ADSP-21160N to a known state and begins execution at
the program memory location specified by the hardware reset vector address. The
RESET input must be asserted (low) at power-up.
Test Clock (JTAG). Provides a clock for JTAG boundary scan.
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kΩ
internal pull-up resistor.
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a
20 kΩ internal pull-up resistor.
Test Data Output (JTAG). Serial scan output of the boundary scan path.
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)
after power-up or held low for proper operation of the ADSP-21160N. TRST has a
20 kΩ internal pull-up resistor.
Emulation Status. Must be connected to the ADSP-21160N emulator target board
connector only. EMU has a 50 kΩ internal pull-up resistor.
Core Instruction Fetch. Signal is active low when an external instruction fetch is
performed. Driven by bus master only. Three-state when host is bus master. CIF has a
20kΩ internal pull-up resistor that is enabled on the ADSP-21160N with ID2–0 = 00x.
Core Power Supply. Nominally 1.9 V dc and supplies the DSP’s core processor
(40 pins).
I/O Power Supply. Nominally 3.3 V dc (43 pins).
Analog Power Supply. Nominally 1.9 V dc and supplies the DSP’s internal PLL (clock
generator). This pin has the same specifications as VDDINT, except that added filtering
circuitry is required. For more information, see Power Supplies on page 6.
Analog Power Supply Return.
Power Supply Return. (82 pins)
Do Not Connect. Reserved pins that must be left open and unconnected (9 pins).
Table 3. Boot Mode Selection
EBOOT
LBOOT
BMS
Booting Mode
1
0
0
0
0
1
0
0
1
0
1
1
Output
1 (Input)
1 (Input)
0 (Input)
0 (Input)
x (Input)
EPROM (Connect BMS to EPROM chip select.)
Host Processor
Link Port
No Booting. Processor executes from external memory.
Reserved
Reserved
REV. PrB
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
12
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
April 2002
ADSP-21160N
ADSP-21160N SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
C Grade
K Grade
Signal
Parameter1
Min
Max
Min
Max
Unit
VDDINT
AVDD
VDDEXT
TCASE
VIH1
VIH2
VIL
Internal (Core) Supply Voltage
Analog (PLL) Supply Voltage
External (I/O) Supply Voltage
Case Operating Temperature2
High Level Input Voltage3, @ VDDEXT =Max
High Level Input Voltage4, @ VDDEXT =Max
Low Level Input Voltage3,4, @ VDDEXT =Min
1.8
1.8
3.13
–40
2.2
2.3
–0.5
2.0
2.0
3.47
+100
VDDEXT +0.5
VDDEXT +0.5
0.8
1.8
1.8
3.13
0
2.2
2.3
–0.5
2.0
2.0
3.47
85
VDDEXT +0.5
VDDEXT +0.5
0.8
V
V
V
ºC
V
V
V
1
Specifications subject to change without notice.
See Environmental Conditions on page 48 for information on thermal specifications.
3
Applies to input and bidirectional pins: DATA63–0, ADDR31–0, RDx, WRx, ACK, SBTS, IRQ2–0, FLAG3–0, HBG, CS, DMAR1, DMAR2, BR6–1,
ID2–0, RPBA, PA, BRST, TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1,
TCLK0, TCLK1, RCLK0, RCLK1.
4
Applies to input pins: CLKIN, RESET, TRST.
2
ELECTRICAL CHARACTERISTICS
C and K Grades
Parameter1
VOH
VOL
IIH
IIL
IILPU1
IILPU2
IOZH
IOZL
IOZHPD
IOZLPU1
IOZLPU2
IOZHA
IOZLA
IDD-INPEAK
IDD-INHIGH
IDD-INLOW
IDD-IDLE
AIDD
CIN
1
Test Conditions
2
High Level Output Voltage
Low Level Output Voltage2
High Level Input Current4,5,6
Low Level Input Current4
Low Level Input Current Pull-Up15
Low Level Input Current Pull-Up26
Three-State Leakage Current7,8,9,10
Three-State Leakage Current7
Three-State Leakage Current
Pull-Down10
Three-State Leakage Current
Pull-Up18
Three-State Leakage Current
Pull-Up29
Three-State Leakage Current11
Three-State Leakage Current11
Supply Current (Internal)12
Supply Current (Internal)13
Supply Current (Internal)14
Supply Current (Idle)15
Supply Current (Analog)16
Input Capacitance17,18
Min
Max
Unit
0.4
10
10
250
500
10
10
250
V
V
µA
µA
µA
µA
µA
µA
µA
@ VDDEXT =Max, VIN =0 V
250
µA
@ VDDEXT =Max, VIN =0 V
500
µA
@ VDDEXT =Max, VIN =VDD Max
@ VDDEXT =Max, VIN =0 V
tCCLK =10.5 ns, VDDINT =Max
tCCLK =10.5 ns, VDDINT =Max
tCCLK =10.5 ns, VDDINT =Max
tCCLK =10.5 ns, VDDINT =Max
@AVDD =Max
fIN =1 MHz, TCASE =25°C,
VIN =2.5 V
25
4
1400
875
625
400
10
4.7
µA
mA
mA
mA
mA
mA
mA
pF
3
@ VDDEXT =Min, IOH =–2.0 mA
@ VDDEXT =Min, IOL =4.0 mA3
@ VDDEXT =Max, VIN =VDD Max
@ VDDEXT =Max, VIN =0 V
@ VDDEXT =Max, VIN =0 V
@ VDDEXT =Max, VIN =0 V
@ VDDEXT =Max, VIN =VDD Max
@ VDDEXT =Max, VIN =0 V
@ VDDEXT =Max, VIN =VDD Max
2.4
Specifications subject to change without notice.
REV. PrB
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ADSP-21160N
Applies to output and bidirectional pins: DATA63–0, ADDR31–0, MS3–0, RDx, WRx, PAGE, CLKOUT, ACK, FLAG3–0, TIMEXP, HBG, REDY,
DMAG1, DMAG2, BR6–1, PA, BRST, CIF, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK,
LxACK, BMS, TDO, EMU.
3
See Output Drive Currents on page 46 for typical drive current capabilities.
4
Applies to input pins: SBTS, IRQ2–0, HBR, CS, ID2–0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK, CLK_CFG3-0.
5
Applies to input pins with internal pull-ups: DR0, DR1.
6
Applies to input pins with internal pull-ups: DMARx, TMS, TDI, TRST.
7
Applies to three-statable pins: DATA63–0, ADDR31–0, PAGE, CLKOUT, ACK, FLAG3–0, REDY, HBG, BMS, BR6–1, TFSx, RFSx, TDO.
8
Applies to three-statable pins with internal pull-ups: DTx, TCLKx, RCLKx, EMU.
9
Applies to three-statable pins with internal pull-ups: MS3–0, RDx, WRx, DMAGx, PA, CIF.
10
Applies to three-statable pins with internal pull-downs: LxDAT7–0, LxCLK, LxACK.
11
Applies to ACK pulled up internally with 2 kΩ during reset or ID2–0 = 00x.
12
The test program used to measure IDD-INPEAK represents worst case processor operation and is not sustainable under normal application conditions. Actual
internal power measurements made using typical applications are less than specified. For more information, see Power Dissipation on page 46.
13
IDDINHIGH is a composite average based on a range of high activity code. For more information, see Power Dissipation on page 46.
14
IDDINLOW is a composite average based on a range of low activity code. For more information, see Power Dissipation on page 46.
15
Idle denotes ADSP-21160N state during execution of IDLE instruction. For more information, see Power Dissipation on page 46.
16
Characterized, but not tested.
17
Applies to all signal pins.
18
Guaranteed, but not tested.
2
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ADSP-21160N
ABSOLUTE MAXIMUM RATINGS
Internal (Core) Supply Voltage (VDDINT)1 . . –0.3 V to +2.3 V
Analog (PLL) Supply Voltage (AVDD) . . . . . –0.3 V to +2.3 V
External (I/O) Supply Voltage (VDDEXT) . . . . –0.3 V to +4.6 V
Input Voltage . . . . . . . . . . . . . . . . . –0.5 V to VDDEXT +0.5 V
Output Voltage Swing . . . . . . . . . . . –0.5 V to VDDEXT +0.5 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF
Junction Temperature under Bias . . . . . . . . . . . . . . . 130ºC
Storage Temperature Range. . . . . . . . . . . –65ºC to +150ºC
1
Stresses greater than those listed above may cause permanent damage to the device.
These are stress ratings only. Functional operation of the device at these or any
other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ESD SENSITIVITY
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V
readily accumulate on the human body and test equipment and can discharge without
detection. Although the ADSP-21160N features proprietary ESD protection circuitry,
permanent damage may occur on devices subjected to high-energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. PrB
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Timing Specifications
The ADSP-21160N’s internal clock switches at higher frequencies than the system input clock (CLKIN). To generate
the internal clock, the DSP uses an internal phase-locked
loop (PLL). This PLL-based clocking minimizes the skew
between the system clock (CLKIN) signal and the DSP’s
internal clock (the clock source for the external port logic
and I/O pads).
The ADSP-21160N’s internal clock (a multiple of CLKIN)
provides the clock signal for timing internal memory,
processor core, link ports, serial ports, and external port (as
required for read/write strobes in asynchronous access
mode). During reset, program the ratio between the DSP’s
internal clock frequency and external (CLKIN) clock
frequency with the CLK_CFG3–0 pins. Even though the
internal clock is the clock source for the external port, the
external port clock always switches at the CLKIN frequency. To determine switching frequencies for the serial
and link ports, divide down the internal clock, using the
programmable divider control of each port (TDIVx/RDIVx
for the serial ports and LxCLKD1–0 for the link ports).
Note the following definitions of various clock periods that
are a function of CLKIN and the appropriate ratio control:
• tCCLK = (tCK) / CR
• tLCLK = (tCCLK) ⴛ LR
• tSCLK = (tCCLK) ⴛ SR
ADSP-21160N
Switching Characteristics specify how the processor
changes its signals. Circuitry external to the processor must
be designed for compatibility with these signal characteristics. Switching characteristics describe what the processor
will do in a given circumstance. Use switching characteristics to ensure that any timing requirement of a device
connected to the processor (such as memory) is satisfied.
Timing Requirements apply to signals that are controlled
by circuitry external to the processor, such as the data input
for a read operation. Timing requirements guarantee that
the processor operates correctly with other devices.
During processor reset (RESET pin low) or software reset
(SRST bit in SYSCON register = 1), de-assertion (MS3-0,
HBG, DMAGx, RDx, WRx, CIF, PAGE, BRST) and
three-state (FLAG3-0, LxCLK, LxACK, LxDAT7-0,
ACK, REDY, PA, TFSx, RFSx, TCLKx, RCLKx, DTx,
BMS, TDO, EMU, DATA) timings differ. These occur
asynchronously to CLKIN, and may not meet the specifications published in the Timing Requirements and
Switching Characteristics tables. The maximum delay for
de-assertion and three-state is one tCK from RESET pin
assertion low or setting the SRST bit in SYSCON. During
reset the DSP will not respond to SBTS, HBR and MMS
accesses. HBR asserted before reset will be recognized, but
a HBG will not be returned by the DSP until after reset is
de-asserted and the DSP has completed bus
synchronization.
Where:
• LCLK = Link Port Clock
• SCLK = Serial Port Clock
• tCK = CLKIN Clock Period
• tCCLK = (Processor) Core Clock Period
• tLCLK = Link Port Clock Period
• tSCLK = Serial Port Clock Period
• CR = Core/CLKIN Ratio (2, 3, or 4:1,
determined by CLK_CFG3–0 at reset)
• LR = Link Port/Core Clock Ratio (1, 2, 3, or 4:1,
determined by LxCLKD)
• SR = Serial Port/Core Clock Ratio (wide range,
determined by ⴛCLKDIV)
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of
others. While addition or subtraction would yield meaningful results for an individual device, the values given in this
data sheet reflect statistical variations and worst cases. Consequently, it is not meaningful to add parameters to derive
longer times.
See Figure 34 under Test Conditions for voltage reference
levels.
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April 2002
Power-up Sequencing
During the power up sequence of the DSP, differences in
the ramp up rates and activation time between the two power
supplies can cause current to flow in the I/O ESD protection
circuitry. To prevent this damage to the ESD diode protection circuitry, Analog Devices, Inc. recommends including
a bootstrap Schottky diode (see Figure 11 on page 18. The
bootstrap Schottky diode connected between the 1.9V and
ADSP-21160N
3.3V power supplies protects the ADSP-21160N from
partially powering the 3.3V supply. Including a Schottky
diode will shorten the delay between the supply ramps and
thus prevent damage to the ESD diode protection circuitry.
With this technique, if the 1.9V rail rises ahead of the 3.3V
rail, the Schottky diode pulls the 3.3V rail along with the
1.9V rail.
Table 4. Power-up Sequencing
Parameter
Min
Timing Requirements:
tRSTVDD
RESET low before VDDINT/VDDEXT on
tIVDDEVDD
VDDINT on before VDDEXT
tCLKVDD
CLKIN running after valid VDDINT/VDDEXT1
tCLKRST
CLKIN valid before RESET de-asserted
tPLLRST
PLL control setup before RESET de-asserted
Switching Characteristics:
DSP core reset de-asserted after RESET de-asserted
tCORERST
0
-50
0
103
TBD4
Max
200
2002
4096*tCK4,5
Unit
ns
ms
ms
µs
ms
ms
1
Valid VDDINT/VDDEXT assumes that the supplies are fully ramped to their 1.9 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds
of milliseconds, depending on the design of the power supply subsystem.
2
CLKIN should be driven coincident with power-up to avoid an undefined state in internal gates, which may cause excess current flow.
3
Assumes a stable CLKIN signal after meeting worst case start up timing of oscillators. Refer to your oscillator manufacturer’s data sheet for start up time.
4
Based on CLKIN cycles.
5
CORERST is an internal signal only. The 4096 cycle count is dependent on tSRST specification. If setup time is not met, one additional CLKIN cycle may
be added to the core reset time, resulting in 4097 cycles maximum.
RESET
tRSTVDD
VDDINT
tIVDDEVDD
VDDEXT
tCLKVDD
CLKIN
tCLKRST
CLK_CFG3-0
tPLLRST
tCORERST
CORERST
Figure 10. Power-up Sequencing
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3.3V I/O
VOLTAGE REGULATOR
ADSP-21160N
VDDEXT
ADSP-21160
1.9V CORE
VOLTAGE REGULATOR
VDDINT
Figure 11. Dual Voltage Schottky Diode
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ADSP-21160N
Clock Input
Table 5. Clock Input
95 MHz
Parameter
Min
Max
Unit
Timing Requirements:
tCK
CLKIN Period
tCKL
CLKIN Width Low
CLKIN Width High
tCKH
tCKRF
CLKIN Rise/Fall (0.4 V–2.0 V)
21
9.5
9.5
80
40
40
3
ns
ns
ns
ns
tCK
CLKIN
tCKH
tCKL
Figure 12. Clock Input
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ADSP-21160N
Reset
Table 6. Reset
Parameter
Min
Timing Requirements:
tWRST
RESET Pulsewidth Low1
RESET Setup Before CLKIN High2
tSRST
4tCK
8
Max
Unit
ns
ns
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 µs while RESET is
low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator).
2
Only required if multiple ADSP-21160Ns must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple
ADSP-21160Ns communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself
after reset.
1
CLKIN
tWRST
tSRST
RESET
Figure 13. Reset
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ADSP-21160N
Interrupts
Table 7. Interrupts
1
2
Parameter
Min
Timing Requirements:
tSIR
IRQ2–0 Setup Before CLKIN High1
IRQ2–0 Hold After CLKIN High1
tHIR
tIPW
IRQ2–0 Pulsewidth2
6
0
2+tCK
Max
Unit
ns
ns
ns
Only required for IRQx recognition in the following cycle.
Applies only if tSIR and tHIR requirements are not met.
CLKIN
tSIR
tHIR
IRQ2–0
tIPW
Figure 14. Interrupts
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ADSP-21160N
Timer
Table 8. Timer
Parameter
Min
Max
Unit
Switching Characteristic:
tDTEX
CLKIN High to TIMEXP
1
9
ns
CLKIN
tDTEX
tDTEX
TIMEXP
Figure 15. Timer
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ADSP-21160N
Flags
Table 9. Flags
Parameter
Min
Timing Requirements:
tSFI
FLAG3–0 IN Setup Before CLKIN High1
FLAG3–0 IN Hold After CLKIN High1
tHFI
tDWRFI
FLAG3–0 IN Delay After RDx/WRx Low1
tHFIWR
FLAG3–0 IN Hold After RDx/WRx Deasserted1
Switching Characteristics:
FLAG3–0 OUT Delay After CLKIN High
tDFO
FLAG3–0 OUT Hold After CLKIN High
tHFO
tDFOE
CLKIN High to FLAG3–0 OUT Enable
tDFOD
CLKIN High to FLAG3–0 OUT Disable
1
Max
4
1
Unit
ns
ns
ns
ns
12
0
9
1
1
tCK– tCCLK +5
ns
ns
ns
ns
Flag inputs meeting these setup and hold times for instruction cycle N will affect conditional instructions in instruction cycle N+2.
CLKIN
tDFOE
tDFO
tDFO
tDFOD
tHFO
FLAG3–0 OUT
FLAG OUTPUT
CLKIN
tSFI
tHFI
FLAG3–0 IN
tDWRFI
tHFIWR
RDX
WRX
FLAG INPUT
Figure 16. Flags
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ADSP-21160N
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-21160N is the bus master accessing external memory space in asynchronous access mode. Note that timing for ACK, DATA, RDx, WRx, and DMAG strobe timing parameters only applies
to asynchronous access mode.
Table 10. Memory Read—Bus Master
Parameter
Min
Max
Timing Requirements:
tDAD
Address, CIF, Selects Delay to Data
tCK – 0.25tCCLK – 11+W
Valid1,2
tDRLD
RDx Low to Data Valid1,3
tCK – 0.5tCCLK +W
tHDA
Data Hold from Address, Selects4
0
Data Setup to RDx High1
8
tSDS
tHDRH
Data Hold from RDx High3,4
1
tDAAK
ACK Delay from Address, Selects2,5
tCK – 0.5tCCLK – 12+W
tDSAK
ACK Delay from RDx Low3,5
tCK – 0.75tCCLK – 11+W
tSAKC
ACK Setup to CLKIN3,5
0.5tCCLK +3
tHAKC
ACK Hold After CLKIN3
1
Switching Characteristics:
Address, CIF, Selects Hold After RDx
0.25tCCLK – 1+H
tDRHA
High3
Address, CIF, Selects to RDx Low2
0.25tCCLK – 3
tDARL
tRW
RDx Pulse width3
tCK – 0.5tCCLK – 1+W
tRWR
RDx High to WRx, RDx, DMAGx Low3
0.5tCCLK – 1+HI
W = (number of wait states specified in WAIT register) ⴛ tCK.
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = tCK (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
Data Delay/Setup: User must meet tDAD, tDRLD, or tSDS.
The falling edge of MSx, BMS is referenced.
3
Note that timing for ACK, DATA, RDx, WRx, and DMAG strobe timing parameters only applies to asynchronous access mode.
4
Data Hold: User must meet tHDA or tHDRH in asynchronous access mode. See Example System Hold Time Calculation on page 47 for the calculation of
hold times given capacitive and dc loads.
5
ACK Delay/Setup: User must meet tDAAK, tDSAK, or tSAKC for deassertion of ACK (Low), all three specifications must be met for assertion of ACK (High).
2
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ADSP-21160N
tDARL
tDRHA
ADDRESS
MSx, CIF
BMS
tRW
RDX
tDRLD
tSDS
tDAD
tHDA
tHDRH
DATA
tDSAK
tRWR
tDAAK
ACK
tSAKC
tHAKC
CLKIN
WRx
DMAG
Figure 17. Memory Read—Bus Master
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ADSP-21160N
Memory Write—Bus Master
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-21160N is the bus master accessing external memory space in asynchronous access mode. Note that timing for ACK, DATA, RDx, WRx, and DMAG strobe timing parameters only applies
to asynchronous access mode.
Table 11. Memory Write—Bus Master
Parameter
Min
Max
Unit
Timing Requirements:
tDAAK
ACK Delay from Address, Selects1,2
tCK – 0.5tCCLK –12+W
tDSAK
ACK Delay from WRx Low1,3
tCK – 0.75tCCLK – 11+W
tSAKC
ACK Setup to CLKIN1,3
0.5tCCLK +3
tHAKC
ACK Hold After CLKIN1,3
1
Switching Characteristics:
Address, CIF, Selects to WRx
tCK – 0.25tCCLK – 3+W
tDAWH
Deasserted2,3
Address, CIF, Selects to WRx Low2
0.25tCCLK – 3
tDAWL
tWW
WRx Pulse width3
tCK – 0.5tCCLK – 1+W
tDDWH
Data Setup before WRx High3
tCK – 0.5tCCLK – 1+W
tDWHA
Address Hold after WRx Deasserted3
0.25tCCLK – 1+H
tDWHD
Data Hold after WRx Deasserted3
0.25tCCLK – 1+H
tDATRWH
Data Disable after WRx Deasserted3,4
0.25tCCLK – 2+H
0.25tCCLK +2+H
WRx High to WRx, RDx, DMAGx Low3 0.5tCCLK – 1+HI
tWWR
tDDWR
Data Disable before WRx or RDx Low 0.25tCCLK – 1+I
tWDE
WRx Low to Data Enabled
–0.25tCCLK – 1
W = (number of wait states specified in WAIT register) × tCK.
H = tCK (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
I = tCK (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
ACK Delay/Setup: User must meet tDAAK or tDSAK or tSAKC for deassertion of ACK (Low), all three specifications must be met for assertion of ACK (High).
The falling edge of MSx, BMS is referenced.
3
Note that timing for ACK, DATA, RDx, WRx, and DMAG strobe timing parameters only applies to asynchronous access mode.
4
See Example System Hold Time Calculation on page 47 for calculation of hold times given capacitive and dc loads.
2
ADDRESS
MSx , BMS ,
CIF
tDAWH
tDAWL
tDWHA
tWW
WRx
tWDE
tDATRWH
tDDWH
tWWR
tDDWR
DATA
tDSAK
tDWHD
tDAAK
ACK
tSAKC
tHAKC
CLKIN
RDx
DMAG
Figure 18. Memory Write—Bus Master
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ADSP-21160N
Synchronous Read/Write—Bus Master
Use these specifications for interfacing to external memory systems that require CLKIN—relative timing or for accessing
a slave ADSP-21160N (in multiprocessor memory space). These synchronous switching characteristics are also valid during
asynchronous memory reads and writes except where noted (see Memory Read—Bus Master on page 24 and Memory
Write—Bus Master on page 26). When accessing a slave ADSP-21160N, these switching characteristics must meet the
slave’s timing requirements for synchronous read/writes (see Synchronous Read/Write—Bus Slave on page 29). The slave
ADSP-21160N must also meet these (bus master) timing requirements for data and acknowledge setup and hold times.
Table 12. Synchronous Read/Write—Bus Master
Parameter
Min
Timing Requirements:
tSSDATI
Data Setup Before CLKIN1
Data Hold After CLKIN1
tHSDATI
tSACKC
ACK Setup Before CLKIN1
tHACKC
ACK Hold After CLKIN1
Switching Characteristics:
Address, MSx, BMS, BRST, CIF Delay After CLKIN
tDADDO
tHADDO
Address, MSx, BMS, BRST, CIF Hold After CLKIN
tDPGO
PAGE Delay After CLKIN
tDRDO
RDx High Delay After CLKIN1
tDWRO
WRx High Delay After CLKIN1
RDx/WRx Low Delay After CLKIN
tDRWL
tDDATO
Data Delay After CLKIN
tHDATO
Data Hold After CLKIN
tDACKMO
ACK Delay After CLKIN2
tACKMTR
ACK Disable Before CLKIN2
tDCKOO
CLKOUT Delay After CLKIN
CLKOUT Period
tCKOP
tCKWH
CLKOUT Width High
tCKWL
CLKOUT Width Low
Max
5.5
1
0.5tCCLK +3
1
ns
ns
ns
ns
10
1.5
1.5
0.25tCCLK – 1
0.25tCCLK – 1
0.25tCCLK – 1
1.5
3
–3
1
tCK – 1
tCK/2 – 2
tCK/2 – 2
Unit
11
0.25tCCLK +9
0.25tCCLK +9
0.25tCCLK +9
0.25tCCLK +9
9
5
tCK3 +1
tCK/2+23
tCK/2+23
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note that timing for ACK, DATA, RDx, WRx, and DMAG strobe timing parameters only applies to synchronous access mode.
Applies to broadcast write, master precharge of ACK.
3
Applies only when the DSP drives a bus operation; CLKOUT held inactive or three-state otherwise, For more information, see the System Design chapter
in the ADSP-2116x SHARC DSP Hardware Reference.
1
2
REV. PrB
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ADSP-21160N
CLKIN
tCKOP
tCKWH
tDCKOO
tCKWL
CLKOUT
tDADDO
tHADDO
ADDRESS
MSX, BRST,
CIF
tDPGO
PAGE
tHACKC
tSACKC
ACK
(IN)
tDACKMO
tACKMTR
ACK
(OUT)
READ CYCLE
tDRWL
tDRDO
⌹⌬␹
tSSDATI
tHSDATI
DATA
(IN)
WRITE CYCLE
tDRWL
tDWRO
⑁ ⌹␹
tDDATO
tHDATO
DATA
(OUT)
Figure 19. Synchronous Read/Write—Bus Master
REV. PrB
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ADSP-21160N
Synchronous Read/Write—Bus Slave
Use these specifications for ADSP-21160N bus master accesses of a slave’s IOP registers or internal memory (in multiprocessor memory space). The bus master must meet these (bus slave) timing requirements.
Table 13. Synchronous Read/Write—Bus Slave
Parameter
Min
Timing Requirements:
tSADDI
Address, BRST Setup Before CLKIN
tHADDI
Address, BRST Hold After CLKIN
tSRWI
RDx/WRx Setup Before CLKIN
tHRWI
RDx/WRx Hold After CLKIN
tSSDATI
Data Setup Before CLKIN
Data Hold After CLKIN
tHSDATI
Switching Characteristics:
Data Delay After CLKIN
tDDATO
tHDATO
Data Hold After CLKIN
tDACKC
ACK Delay After CLKIN
tHACKO
ACK Hold After CLKIN
REV. PrB
Max
5
1
5
1
5.5
1
Unit
ns
ns
ns
ns
ns
ns
0.25 tCCLK + 9
1.5
10
1.5
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
ns
ns
ns
ns
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ADSP-21160N
CLKIN
tSADDI
tHADDI
ADDRESS
tHACKO
tDACKC
ACK
tSRWI
READ ACCESS
tHRWI
RDx
tHDATO
tDDATO
DATA
(OUT)
WRITE ACCESS
tHRWI
tSRWI
WRx
tSSDATI
tHSDATI
DATA
(IN)
Figure 20. Synchronous Read/Write—Bus Slave
REV. PrB
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ADSP-21160N
Multiprocessor Bus Request and Host Bus Request
Use these specifications for passing of bus mastership between multiprocessing ADSP-21160Ns (BRx) or a host processor
(HBR, HBG).
Table 14. Multiprocessor Bus Request and Host Bus Request
Parameter
Min
Timing Requirements:
tHBGRCSV
HBG Low to RDx/WRx/CS Valid
HBR Setup Before CLKIN1
tSHBRI
tHHBRI
HBR Hold After CLKIN1
HBG Setup Before CLKIN
tSHBGI
tHHBGI
HBG Hold After CLKIN High
tSBRI
BRx, PA Setup Before CLKIN
tHBRI
BRx, PA Hold After CLKIN High
tSRPBAI
RPBA Setup Before CLKIN
tHRPBAI
RPBA Hold After CLKIN
Switching Characteristics:
HBG Delay After CLKIN
tDHBGO
tHHBGO
HBG Hold After CLKIN
BRx Delay After CLKIN
tDBRO
tHBRO
BRx Hold After CLKIN
tDPASO
PA Delay After CLKIN, Slave
tTRPAS
PA Disable After CLKIN, Slave
tDPAMO
PA Delay After CLKIN, Master
tPATR
PA Disable Before CLKIN, Master
REDY (O/D) or (A/D) Low from CS and HBR Low2
tDRDYCS
tTRDYHG
REDY (O/D) Disable or REDY (A/D) High from HBG2
tARDYTR
REDY (A/D) Disable from CS or HBR High2
1
2
Max
Unit
6.5 + tCK + tCCLK 12.5CR
ns
6
1
6
1
9
1
6
2
ns
ns
ns
ns
ns
ns
ns
ns
7
2
8
1.5
8
1.5
0.25tCCLK +9
0.25tCCLK – 5
0.5tCK
tCK +20
11
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Only required for recognition in the current cycle.
(O/D) = open drain, (A/D) = active drive.
REV. PrB
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ADSP-21160N
CLKIN
tS HB R I
tH H BR I
HBR
t DH B GO
tH HB G O
HBG (OUT)
tD B R O
tH B RO
BRx (OUT)
tTRP A S
tD PA S O
PA (OUT)
(SLAVE)
tP A TR
tD PA M O
PA (OUT)
(MAS TER)
t SH B GI
tH H B GI
HBG (IN)
tSB R I
tH B R I
BRx (IN)
tS PA I
tH PA I
PA (IN)
(O/D)
tS RP B A I
tH R PB A I
RPBA
HBR
CS
tTR D YH G
t DR D YC S
REDY
(O /D)
tA R DY TR
REDY
(A/D)
tH B GRC S V
HBG (OUT)
RDx
WRx
CS
O/D = OPEN DRAIN, A/ D = ACTIVE
DRIVE
Figure 21. Multiprocessor Bus Request and Host Bus Request
REV. PrB
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ADSP-21160N
Asynchronous Read/Write—Host to ADSP-21160N
Use these specifications (Table 15 and Table 16) for asynchronous host processor accesses of an ADSP-21160N, after the
host has asserted CS and HBR (low). After HBG is returned by the ADSP-21160N, the host can drive the RDx and WRx
pins to access the ADSP-21160N’s internal memory or IOP registers. HBR and HBG are assumed low for this timing
Table 15. Read Cycle
Parameter
Min
Timing Requirements:
tSADRDL
Address Setup/CS Low Before RDx Low
Address Hold/CS Hold Low After RDx
tHADRDH
tWRWH
RDx/WRx High Width
tDRDHRDY
RDx High Delay After REDY (O/D) Disable
tDRDHRDY
RDx High Delay After REDY (A/D) Disable
Switching Characteristics:
Data Valid Before REDY Disable from Low
tSDATRDY
tDRDYRDL
REDY (O/D) or (A/D) Low Delay After RDx Low
tRDYPRD
REDY (O/D) or (A/D) Low Pulsewidth for Read
Data Disable After RDx High
tHDARWH
Max
0
2
5
0
0
Unit
ns
ns
ns
ns
ns
2
11
tCK - 3
2
6
ns
ns
ns
ns
READ CYCLE
ADDRESS/ CS
tH AD R D H
tS AD R D L
tWR WH
RDx
tH D A R WH
D ATA (OUT)
tSD A TR DY
tD RD YRD L
tD R D HR D Y
t RD Y PR D
REDY (O/ D)
REDY (A/D)
Figure 22. Read Cycle (Asynchronous Read—Host to ADSP-21160N)
REV. PrB
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Table 16. Write Cycle
Parameter
Min
Timing Requirements:
tSCSWRL
CS Low Setup Before WRx Low
CS Low Hold After WRx High
tHCSWRH
tSADWRH
Address Setup Before WRx High
tHADWRH
Address Hold After WRx High
tWWRL
WRx Low Width
tWRWH
RDx/WRx High Width
tDWRHRDY
WRx High Delay After REDY (O/D) or (A/D) Disable
Data Setup Before WRx High
tSDATWH
tHDATWH
Data Hold After WRx High
Switching Characteristics:
REDY (O/D) or (A/D) Low Delay After WRx/CS Low
tDRDYWRL
tRDYPWR
REDY (O/D) or (A/D) Low Pulsewidth for Write
Max
0
0
6
2
7
5
0
5
4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
5.75 + 0.5tCCLK
ns
ns
WRITE CY CLE
ADDRESS
tSA D WR H
tS C SWR L
tH AD W RH
T HC S WR H
CS
tWWR L
tWR WH
WRx
tH D A TWH
tSD A TWH
DATA (I N)
tD R D YW RL
tR D YP WR
tD WR H R DY
REDY (O /D)
REDY (A/D)
O/D = O PEN DRAIN, A/D = ACT IVE
DRI VE
Figure 23. Write Cycle (Asynchronous Write—Host to ADSP-21160N)
REV. PrB
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ADSP-21160N
Three-State Timing—Bus Master and Bus Slave
These specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to
CLKIN and the SBTS pin. This timing is applicable to bus master transition cycles (BTC) and host transition cycles (HTC)
as well as the SBTS pin.
Table 17. Three-State Timing—Bus Slave, HBR, SBTS
Parameter
Min
Timing Requirements:
tSTSCK
SBTS Setup Before CLKIN
tHTSCK
SBTS Hold After CLKIN
Switching Characteristics:
Address/Select Enable After CLKIN
tMIENA
tMIENS
Strobes Enable After CLKIN1
HBG Enable After CLKIN
tMIENHG
tMITRA
Address/Select Disable After CLKIN
tMITRS
Strobes Disable After CLKIN1,2
tMITRHG
HBG Disable After CLKIN
tDATEN
Data Enable After CLKIN3
tDATTR
Data Disable After CLKIN3
tACKEN
ACK Enable After CLKIN3
ACK Disable After CLKIN3
tACKTR
tCDCEN
CLKOUT Enable After CLKIN
tCDCTR
CLKOUT Disable After CLKIN
tATRHBG
Address, MSx Disable Before HBG Low
tSTRHBG
RDx, WRx, DMAGx Disable Before HBG Low
tPTRHBG
Page Disable Before HBG Low
BMS Disable Before HBG Low
tBTRHBG
tMENHBG
Memory Interface Enable After HBG High4
Max
6
2
1.5
1.5
1.5
1.5
0.25tCCLK – 4
3.5
0.25tCCLK +1
1.5
1.5
1.5
1.5
tCCLK – 3
1.5tCK + 1.5
tCK + 0.25tCCLK + 1.5
tCK + 1.5
0.5tCK + 1.5
tCK – 5
Unit
ns
ns
9
9
9
9
0.25tCCLK
8
0.25tCCLK + 7
5
9
5
9
tCCLK +1
1.5tCK + 5
tCK + 0.25tCCLK + 5
tCK + 5
0.5tCK + 1.5
tCK +5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Strobes = RDx, WRx, DMAGx.
If access aborted by SBTS, then strobes disable before CLKIN [0.25tCCLK + 1.5 (min.), 0.25tCCLK + 5 (max.)]
3
In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.
4
Memory Interface = Address, RDx, WRx, MSx, PAGE, DMAGx, and BMS (in EPROM boot mode).
1
2
REV. PrB
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ADSP-21160N
CLKIN
tSTSCK
tHTSCK
SBTS
tMIENA, tMIENS, tMIENHG
tMITRA, tMITRS, tMITRHG
MEMORY
INTERFACE
tDATTR
tDATEN
DATA
tACKTR
tACKEN
ACK
tCDCEN
tCDCTR
CLKOUT
HBG
tMENHBG
tATRHBG
tSTRHBG
tPTRHBG
tBTRHBG
MEMORY
INTERFACE
MEMORY INTERFACE = ADDRESS, RDx, WRx, MSx, PAGE, DMAGx. BMS (IN EPROM BOOT MODE)
Figure 24. Three-State Timing—Bus Slave, HBR, SBTS
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ADSP-21160N
DMA Handshake
These specifications describe the three DMA handshake modes. In all three modes DMAR is used to initiate transfers. For
handshake mode, DMAG controls the latching or enabling of data externally. For external handshake mode, the data transfer
is controlled by the ADDR31–0, RDx, WRx, PAGE, MS3–0, ACK, and DMAG signals. For Paced Master mode, the data
transfer is controlled by ADDR31–0, RDx, WRx, MS3–0, and ACK (not DMAG). For Paced Master mode, the Memory
Read-Bus Master, Memory Write-Bus Master, and Synchronous Read/Write-Bus Master timing specifications for
ADDR31–0, RDx, WRx, MS3–0, PAGE, DATA63–0, and ACK also apply.
Table 18. DMA Handshake
Parameter
Min
Max
Timing Requirements:
tSDRC
DMARx Setup Before CLKIN1
3
DMARx Width Low (Nonsynchronous)2 0.5tCCLK +1
tWDR
tSDATDGL
Data Setup After DMAGx Low3
tCK – 0.5tCCLK –7
tHDATIDG
Data Hold After DMAGx High
2
tDATDRH
Data Valid After DMARx High3
tCK +3
tDMARLL
DMARx Low Edge to Low Edge4
tCK
tDMARH
DMARx Width High2
0.5tCCLK +1
Switching Characteristics:
DMAGx Low Delay After CLKIN
0.25tCCLK +1
0.25tCCLK +9
tDDGL
tWDGH
DMAGx High Width
0.5tCCLK – 1+HI
DMAGx Low Width
tCK – 0.5tCCLK – 1
tWDGL
tHDGC
DMAGx High Delay After CLKIN
tCK – 0.25tCCLK +1.5
tCK – 0.25tCCLK +9
tVDATDGH
Data Valid Before DMAGx High5
tCK – 0.25tCCLK – 8
tCK – 0.25tCCLK +5
tDATRDGH
Data Disable After DMAGx High6
0.25tCCLK – 3
0.25tCCLK +1.5
tDGWRL
WRx Low Before DMAGx Low
–1.5
2
tDGWRH
DMAGx Low Before WRx High
tCK – 0.5tCCLK – 2 +W
WRx High Before DMAGx High7
–1.5
2
tDGWRR
tDGRDL
RDx Low Before DMAGx Low
–1.5
2
tDRDGH
RDx Low Before DMAGx High
tCK – 0.5tCCLK –2+W
tDGRDR
RDx High Before DMAGx High7
–1.5
2
tDGWR
DMAGx High to WRx, RDx, DMAGx
0.5tCCLK – 2+HI
Low
Address/Select Valid to DMAGx High
18
tDADGH
tDDGHA
Address/Select Hold after DMAGx High
1
W = (number of wait states specified in WAIT register) ⴛ tCK.
HI = tCK (if data bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
Only required for recognition in the current cycle.
Maximum throughput using DMARx/DMAGx handshaking equals tWDR + tDMARH = (0.5tCCLK +1) + (0.5tCCLK +1)=12.5 ns (80 MHz). This throughput
limit applies to non-synchronous access mode only.
3
tSDATDGL is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of
the write, the data can be driven tDATDRH after DMARx is brought high.
4
Use tDMARLL if DMARx transitions synchronous with CLKIN. Otherwise, use tWDR and tDMARH.
5
tVDATDGH is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then
tVDATDGH = tCK – .25tCCLK – 8 + (n × tCK) where n equals the number of extra cycles that the access is prolonged.
6
See Example System Hold Time Calculation on page 47 for calculation of hold times given capacitive and dc loads.
7
This parameter applies for synchronous access mode only.
2
REV. PrB
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CLKIN
tSDRC
tDMARLL
tSDRC
tWDR
tDMARH
DMARx
tHDGC
tDDGL
tWDGL
tWDGH
DMAGx
TRANSFERS BETWEEN ADSP-2116X
INTERNAL MEMORY AND EXTERNAL DEVICE
tDATRDGH
tVDATDGH
DATA
(FROM ADSP-2116X TO EXTERNAL DRIVE)
tDATDRH
tSDATDGL
tHDATIDG
DATA
(FROM EXTERNAL DRIVE TO ADSP-2116X)
TRANSFERS BETWEEN EXTERNAL DEVICE AND
EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE)
tDGWRL
tDGWRH
tDGWRR
WRx
(EXTERNAL DEVICE TO EXTERNAL MEMORY)
tDGRDR
tDGRDL
RDx
(EXTERNAL MEMORY TO EXTERNAL DEVICE)
tDRDGH
tDADGH
tDDGHA
ADDR
MSX
* MEMORY READ BUS MASTER, MEMORY WRITE BUS MASTER, OR SYNCHRONOUS READ/WRITE BUS MASTER
TIMING SPECIFICATIONS FOR ADDR31–0, RDX, WRX, MS3–0 AND ACK ALSO APPLY HERE.
Figure 25. DMA Handshake Timing
REV. PrB
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ADSP-21160N
Link Ports
Calculation of link receiver data setup and hold, relative to link clock, is required to determine the maximin allowable skew
that can be introduced in the transmission path, between LDATA and LCLK. Setup skew is the maximum delay that can
be introduced in LDATA, relative to LCLK (setup skew = tLCLKTWH minimum – tDLDCH – tSLDCL). Hold skew is the maximum
delay that can be introduced in LCLK, relative to LDATA (hold skew = tLCLKTWL minimum + tHLDCH – tHLDCL).Calculations
made directly from speed specifications result in unrealistically small skew times, because they include multiple tester
guardbands.
Note that there is a two-cycle effect latency between the link port enable instruction and the DSP enabling the link port.
Table 19. Link Ports—Receive
Parameter
Min
Timing Requirements:
tSLDCL
Data Setup Before LCLK Low
tHLDCL
Data Hold After LCLK Low
tLCLKIW
LCLK Period
LCLK Width Low
tLCLKRWL
tLCLKRWH
LCLK Width High
Switching Characteristics:
LACK Low Delay After LCLK High1
tDLALC
1
Max
2.5
2.5
tLCLK
4
4
Unit
ns
ns
ns
ns
ns
12
17
ns
LACK goes low with tDLALC relative to rise of LCLK after first nibble, but doesn’t go low if the receiver’s link buffer is not about to fill.
RECEIVE
tLCLKIW
tLCLKRWH
tLCLKRWL
LCLK
tSLDCL
LDAT(7:0)
tHLDCL
IN
tDLALC
LACK (OUT)
Figure 26. Link Ports—Receive
REV. PrB
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Table 20. Link Ports—Transmit
Parameter
Min
Timing Requirements:
tSLACH
LACK Setup Before LCLK High
LACK Hold After LCLK High
tHLACH
Switching Characteristics:
Data Delay After LCLK High
tDLDCH
tHLDCH
Data Hold After LCLK High
tLCLKTWL
LCLK Width Low
tLCLKTWH
LCLK Width High
tDLACLK
LCLK Low Delay After LACK High
Max
Unit
14
–2
ns
ns
6.0
–2
0.5tLCLK – .5
0.5tLCLK – .5
0.5tLCLK +5
ns
ns
ns
ns
ns
0.5tLCLK +.5
0.5tLCLK +.5
3/ tLCLK +11
2
TRANSMIT
tLCLKTWH
tLCLKTWL
LAST NIBBLE/BYTE
TRANSMITTED
FIRST NIBBLE/BYTE
TRANSMITTED
LCLK INACTIVE
(HIGH)
LCLK
tDLDCH
tHLDCH
LDAT(7:0)
OUT
tSLACH
tHLACH
tDLACLK
LACK (IN)
THE tSLACH REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED.
Figure 27. Link Ports—Transmit
REV. PrB
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Serial Ports
To determine whether communication is possible between two devices at clock speed n, the following specifications must
be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width.
Table 21. Serial Ports—External Clock
1
2
Parameter
Min
Timing Requirements:
tSFSE
TFS/RFS Setup Before TCLK/RCLK1
tHFSE
TFS/RFS Hold After TCLK/RCLK1,2
tSDRE
Receive Data Setup Before RCLK1
tHDRE
Receive Data Hold After RCLK1
tSCLKW
TCLK/RCLK Width
TCLK/RCLK Period
tSCLK
3.5
4
1.5
4
8
2tCCLK
Max
Unit
ns
ns
ns
ns
ns
ns
Referenced to sample edge.
RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.
Table 22. Serial Ports—Internal Clock
1
2
Parameter
Min
Timing Requirements:
tSFSI
TFS Setup Before TCLK1; RFS Setup Before RCLK1
tHFSI
TFS/RFS Hold After TCLK/RCLK1,2
Receive Data Setup Before RCLK1
tSDRI
tHDRI
Receive Data Hold After RCLK1
8
tCCLK/2 + 1
6.5
3
Max
Unit
ns
ns
ns
ns
Referenced to sample edge.
RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.
Table 23. Serial Ports—External or Internal Clock
1
Parameter
Min
Switching Characteristics:
RFS Delay After RCLK (Internally Generated RFS)1
tDFSE
tHOFSE
RFS Hold After RCLK (Internally Generated RFS)1
3
Max
Unit
13
ns
ns
Max
Unit
13
ns
ns
ns
ns
Referenced to drive edge.
Table 24. Serial Ports—External Clock
1
Parameter
Min
Switching Characteristics:
tDFSE
TFS Delay After TCLK (Internally Generated TFS)1
tHOFSE
TFS Hold After TCLK (Internally Generated TFS)1
tDDTE
Transmit Data Delay After TCLK1
tHDTE
Transmit Data Hold After TCLK1
3
16
0
Referenced to drive edge.
Table 25. Serial Ports—Internal Clock
Parameter
Min
Switching Characteristics:
tDFSI
TFS Delay After TCLK (Internally Generated TFS)1
TFS Hold After TCLK (Internally Generated TFS)1
tHOFSI
–1.5
REV. PrB
Max
Unit
4.5
ns
ns
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ADSP-21160N
Table 25. Serial Ports—Internal Clock (Continued)
Parameter
tDDTI
tHDTI
tSCLKIW
1
Min
1
Transmit Data Delay After TCLK
Transmit Data Hold After TCLK1
TCLK/RCLK Width
Max
Unit
7.5
0
0.5tSCLK –1.5
0.5tSCLK +1.5
ns
ns
ns
Min
Max
Unit
Referenced to drive edge.
Table 26. Serial Ports—Enable and Three-State
Parameter
Switching Characteristics:
tDDTEN
Data Enable from External TCLK1
tDDTTE
Data Disable from External TCLK1
tDDTIN
Data Enable from Internal TCLK1
Data Disable from Internal TCLK1
tDDTTI
1
4
10
0
3
ns
ns
ns
ns
Referenced to drive edge.
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DATA RECEIVE— INTERNAL CLOCK
DRIVE
EDGE
DATA RECEIVE— EXTERNAL CLOCK
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
ADSP-21160N
RCLK
SAMPLE
EDGE
tSCLKW
RCLK
tDFSE
tDFSE
tSFSI
tHOFSE
tHOFSE
tHFSI
RFS
tSFSE
tHFSE
tSDRE
tHDRE
RFS
tSDRI
tHDRI
DR
DR
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT— INTERNAL CLOCK
DRIVE
EDGE
DATA TRANSMIT— EXTERNAL CLOCK
SAMPLE
EDGE
tSCLKIW
DRIVE
EDGE
SAMPLE
EDGE
tSCLKW
TCLK
TCLK
tDFSE
tDFSI
tHOFSI
tSFSI
TFS
tHFSI
tHOFSE
tSFSE
tHFSE
TFS
tDDTI
tDDTE
tHDTE
tHDTI
DT
DT
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE EDGE
DRIVE EDGE
TCLK /
RCLK
TCLK
(EXT)
tDDTTE
tDDTEN
DT
DRIVE
EDGE
TCLK
(INT)
DRIVE
EDGE
tDDTIN
TCLK /
RCLK
tDDTTI
DT
Figure 28. Serial Ports
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ADSP-21160N
Table 27. Serial Ports—External Late Frame Sync
Parameter
Min
Switching Characteristics:
tDDTLFSE
Data Delay from Late External TFS or External RFS with
MCE = 1, MFD = 01
Data Enable from late FS or MCE = 1, MFD = 01
tDDTENFS
1
Max
Unit
13
ns
1.0
ns
MCE = 1, TFS enable and TFS valid follow tDDTLFSE and tDDTENFS.
EXTERNAL RFS WITH MCE = 1, MFD = 0
DRIVE
SAMPLE
DRIVE
RCLK
tSFSE/I
tHOFSE/I
(SEE NOTE 2)
RFS
tDDTENFS
DT
tDDTE/I
tHDTE/I
1ST BIT
2ND BIT
tDDTLFSE
LATE EXTERNAL TFS
DRIVE
SAMPLE
DRIVE
TCLK
tHOFSE/I
tSFSE/I
(SEE NOTE 2)
TFS
tDDTE/I
TDDTENFS
DT
tHDTE/I
1ST BIT
2ND BIT
tDDTLFSE
Figure 29. External Late Frame Sync
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ADSP-21160N
JTAG Test Access Port and Emulation
Table 28. JTAG Test Access Port and Emulation
Parameter
Min
Timing Requirements:
tTCK
TCK Period
TDI, TMS Setup Before TCK High
tSTAP
tHTAP
TDI, TMS Hold After TCK High
tSSYS
System Inputs Setup Before TCK Low1
tHSYS
System Inputs Hold After TCK Low1
tTRSTW
TRST Pulsewidth
Switching Characteristics:
TDO Delay from TCK Low
tDTDO
tDSYS
System Outputs Delay After TCK Low2
Max
tCK
5
6
7
18
4tCK
Unit
ns
ns
ns
ns
ns
ns
13
30
ns
ns
System Inputs = DATA63–0, ADDR31–0, RDx, WRx, ACK, SBTS, HBR, HBG, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, IRQ2–0, FLAG3–0,
PA, BRST, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, EBOOT, LBOOT, BMS,
CLKIN, RESET.
2
System Outputs = DATA63–0, ADDR31–0, MS3–0, RDx, WRx, ACK, PAGE, CLKOUT, HBG, REDY, DMAG1, DMAG2, BR6–1, PA, BRST, CIF,
FLAG3–0, TIMEXP, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, BMS.
1
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 30. IEEE 11499.1 JTAG Test Access Port
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Output Drive Currents
Figure 31 shows typical I–V characteristics for the output
drivers of the ADSP-21160N. The curves represent the
current drive capability of the output drivers as a function
of output voltage.
ADSP-21160N
from Electrical Characteristics on page 13 and the current-versus-operation information in Table 29, engineers
can estimate the ADSP-21160N’s internal power supply
(VDDINT) input current for a specific application, according
to the following formula:
% Peak × I DDINPEAK
% High × I DDINHIGH
120
SOURCE (VDDEXT) CURRENT –MA
100
% Low × I DDINLOW
VDDEXT =3.47V, –40°C
80
VDDEXT =3.3V, 25°C
60
+ % Idle × I DDIDLE
------------------------------------------------I DDINT
VDDEXT = 3.13V, 100°C
40
20
The external component of total power dissipation is caused
by the switching of output pins. Its magnitude depends on:
0
–20
• the number of output pins that switch during each
cycle (O)
–40
VDDEXT =3.47V, –40°C
–60
• the maximum frequency at which they can switch (f)
VDDEXT =3.3V, 25°C
–80
VDDEXT =3.13V, 100°C
–100
• their load capacitance (C)
–120
0
0.5
1
1.5
2
2.5
SOURCE(VDDEXT) VOLTAGE–V
3
3.5
• their voltage swing (VDD)
and is calculated by:
Figure 31. ADSP-21160N Typical Drive Currents
Power Dissipation
Total power dissipation has two components, one due to
internal circuitry and one due to the switching of external
output drivers.
Internal power dissipation is dependent on the instruction
execution sequence and the data operands involved. Using
the current specifications (IDDINPEAK, IDDINHIGH, IDDINLOW, IDDIDLE)
PEXT = O × C × VDD2 × f
The load capacitance should include the processor’s
package capacitance (CIN). The switching frequency
includes driving the load high and then back low. Address
and data pins can drive high and low at a maximum rate of
1/(2tCK). The write strobe can switch every cycle at a
frequency of 1/tCK. Select pins switch at 1/(2tCK), but selects
can switch on each cycle.
Table 29. ADSP-21160N Operation Types vs. Input Current
Operation
Peak Activity1
High Activity1
Low Activity1
Instruction Type
Instruction Fetch
Core Memory Access2
Multifunction
Cache
2 per tCK cycle
(DMⴛ64 and PMⴛ64)
1 per 2 tCCLK cycles
1 per external port cycle (ⴛ64)
Worst case
Multifunction
Internal Memory
1 per tCK cycle
(DMⴛ64)
1 per 2 tCCLK cycles
1 per external port cycle (ⴛ64)
Random
Single Function
Internal Memory
None
Internal Memory DMA
External Memory DMA
Data bit pattern for core
memory access and DMA
None
None
N/A
1
Peak Activity=IDDINPEAK, High Activity=IDDINHIGH, and Low Activity=IDDINLOW. The state of the PEYEN bit (SIMD versus SISD mode) does not influence
these calculations.
2
These assume a 2:1 core clock ratio. For more information on ratios and clocks (tCK and tCCLK), see the timing ratio definitions on page 16.
REV. PrB
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Example: Estimate PEXT with the following assumptions:
ADSP-21160N
• External data memory writes occur every other cycle, a
rate of 1/(2 tCK), with 50% of the pins switching
• A system with one bank of external data memory—asynchronous RAM (64-bit)
• The bus cycle time is 47.5 MHz (tCK = 21 ns).
• Four 64K × 16 RAM chips are used, each with a load of
10 pF
The PEXT equation is calculated for each class of pins that
can drive:
Table 30. External Power Calculations (3.3 V Device)
Pin Type
# of Pins
% Switching
×C
×f
× VDD2
= PEXT
Address
MS0
WRx
Data
CLKOUT
15
1
2
64
1
50
0
–
50
–
× 44.7 pF
× 44.7 pF
× 44.7 pF
× 14.7 pF
× 4.7 pF
× 24 MHz
× 24 MHz
× 24 MHz
× 24 MHz
× 48 MHz
× 10.9 V
× 10.9 V
× 10.9 V
× 10.9 V
× 10.9 V
= 0.088 W
= 0.000 W
= 0.023 W
= 0.123 W
= 0.003 W
PEXT = 0.237 W
A typical power consumption can now be calculated for
these conditions by adding a typical internal power
dissipation:
PTOTAL = PEXT + PINT + PPLL
Where:
• PEXT is from Table 30
• PINT is IDDINT × 1.9 V, using the calculation IDDINT listed in
Power Dissipation on page 46
• PPLL is AIDD × 1.9 V, using the value for AIDD listed in
ABSOLUTE MAXIMUM RATINGS on page 15
Note that the conditions causing a worst-case PEXT are
different from those causing a worst-case PINT. Maximum
PINT cannot occur while 100% of the output pins are
switching from all ones to all zeros. Note also that it is not
common for an application to have 100% or even 50% of
the outputs switching simultaneously.
Test Conditions
The test conditions for timing parameters appearing in
ADSP-21160N specifications on page 13 include output
disable time, output enable time, and capacitive loading.
Output Enable Time
Output pins are considered to be enabled when they have
made a transition from a high impedance state to when they
start driving. The output enable time tENA is the interval from
when a reference signal reaches a high or low voltage level
to when the output has reached a specified high or low trip
point, as shown in the Output Enable/Disable diagram
(Figure 32). If multiple pins (such as the data bus) are
enabled, the measurement value is that of the first pin to
start driving.
Example System Hold Time Calculation
To determine the data output hold time in a particular
system, first calculate tDECAY using the equation given above.
Choose ⌬V to be the difference between the
ADSP-21160N’s output voltage and the input threshold for
the device requiring the hold time. A typical ⌬V will be
0.4 V. CL is the total bus capacitance (per data line), and IL
is the total leakage or three-state current (per data line). The
hold time will be tDECAY plus the minimum disable time (i.e.,
tDATRWH for the write cycle).
Output Disable Time
Output pins are considered to be disabled when they stop
driving, go into a high impedance state, and start to decay
from their output high or low voltage. The time for the
voltage on the bus to decay by ∆V is dependent on the
capacitive load, CL and the load current, IL. This decay time
can be approximated by the following equation:
tDECAY = (CL∆V)/IL
The output disable time tDIS is the difference between
tMEASURED and tDECAY as shown in Figure 32. The time tMEASURED
is the interval from when the reference signal switches to
when the output voltage decays ∆V from the measured
output high or output low voltage. tDECAY is calculated with
test loads CL and IL, and with ∆V equal to 0.5 V.
REFERENCE
SIGNAL
⌻DIS
tMEASURED
tENA
VOH (MEASURED)
VOH (MEASURED) – ⌬V 2.0V
VOL (MEASURED)
VOL (MEASURED) + ⌬V 1.0V
tDECAY
OUTPUT STOPS
DRIVING
OUTPUT STARTS
DRIVING
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS VOLTAGE
TO BE APPROXIMATELY 1.5V
Figure 32. Output Enable/Disable
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ADSP-21160N
50 ⍀
TO
OUTPUT
PIN
1.5V
RISE TIME
12PF
Y = 0.086192X + 2.34
TBD
FALL TIME
Figure 33. Equivalent Device Loading for AC
Measurements (Includes All Fixtures)
Y = 0.076014X +
2.15
INPUT
OR
OUTPUT
1.5V
1.5V
50
Capacitive Loading
Output delays and holds are based on standard capacitive
loads: 12 pF on all pins (see Figure 33). Figure 35 and
Figure 36 show how output rise time varies with capacitance. Figure 37 graphically shows how output delays and
holds vary with load capacitance. (Note that this graph or
derating does not apply to output disable delays; see Output
Disable Time on page 47.) The graphs of Figure 35,
Figure 36, and Figure 37 may not be linear outside the
ranges shown.
30.00
200
250
Figure 36. Typical Output Rise Time (10%–90%,
VDDEXT = Min) vs. Load Capacitance
20.00
OUTPUT DELAY OR HOLD – ns
Figure 34. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
100
150
LOAD CAPACITANCE – pF
15.00
10.0
0
Y = 0.085526X – 3.87
5.00
0.0
0
RISE AND FALL TIMES – ns
25.00
–5.00
0
RISE TIME
20.00
Y = 0.086687X + 2.18
TBD
15.00
50
100
150
LOAD CAPACITANCE – pF
200
250
Figure 37. Typical Output Delay or Hold vs. Load
Capacitance (at Max Case Temperature)
FALL TIME
10.00
Thermal Characteristics
Y = 0.072781X + 1.99
5.00
0.0
0 0
50
100
150
200
250
LOAD CAPACITANCE – pF
Figure 35. Typical Output Rise Time (10%–90%,
VDDEXT = Max) vs. Load Capacitance
The ADSP-21160N is specified for a case temperature
(TCASE). To ensure that the TCASE data sheet specification is
not exceeded, a heatsink and/or an air flow source may be
used. Use the center block of ground pins (PBGA balls:
F7-14, G7-14, H7-14, J7-14, K7-14, L7-14, M-14, N7-14,
P7-14, R7-15) to provide thermal pathways to the printed
circuit board’s ground plane. A heatsink should be attached
to the ground plane (as close as possible to the thermal
pathways) with a thermal adhesive.
Environmental Conditions
The ADSP-21160NKB-95 and ADSP-21160NCB-TBD
are provided in a 400-Ball Metric PBGA (Plastic Ball Grid
Array) package.
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ADSP-21160N
T CASE = T AMB + ( PD × θ CA )
• TCASE = Case temperature (measured on top surface
of package)
• PD = Power dissipation in W (this value depends upon
the specific application; a method for calculating PD is
shown under Power Dissipation).
• θCA = Value from Table 31.
• θ JB= 6.46°C/W
Table 31. Airflow Over Package Versus θCA
Airflow (Linear Ft./Min.)
θCA (°C/W)1
1
θJC = 3.6 °C/W.
0
12.13
200
9.86
400
8.7
400-BALL METRIC PBGA PIN CONFIGURATIONS
Table 32 lists the pin assignments for the PBGA package,
and the pin configurations diagram on page 53 shows the
pin assignment summary.
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Table 32. 400-ball Metric PBGA Pin Assignments
Pin Name PBGA Pin# Pin Name
PBGA Pin# Pin Name
PBGA Pin# Pin Name
PBGA Pin#
DATA[14]
DATA[13]
DATA[10]
DATA[8]
DATA[4]
DATA[2]
TDI
TRST
RESET
RPBA
IRQ0
FLAG1
TIMEXP
NC
NC
TFS1
RFS1
RCLK0
DT0
L0DAT[4]
DATA[30]
DATA[29]
DATA[23]
DATA[21]
VDDEXT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
GND
VDDINT
VDDINT
VDDINT
VDDINT
VDDEXT
L1DAT[6]
L1DAT[5]
L1ACK
L1DAT[1]
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
E01
E02
E03
E04
E05
E06
E07
E08
E09
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
DATA[22]
DATA[16]
DATA[15]
DATA[9]
DATA[6]
DATA[3]
DATA[0]
TCK
EMU
IRQ2
FLAG3
FLAG0
NC
NC
DT1
RCLK1
RFS0
TCLK0
L0DAT[5]
L0DAT[2]
DATA[34]
DATA[33]
DATA[27]
DATA[26]
VDDEXT
VDDINT
GND
GND
GND
GND
GND
GND
GND
GND
VDDINT
VDDEXT
L1DAT[4]
L1DAT[3]
L1DAT[0]
L2DAT[7]
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
F01
F02
F03
F04
F05
F06
F07
F08
F09
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
DATA[24]
DATA[18]
DATA[17]
DATA[11]
DATA[7]
DATA[5]
DATA[1]
TMS
TD0
IRQ1
FLAG2
NC
NC
TCLK1
DR1
DR0
L0DAT[7]
L0DAT[6]
L0ACK
L0DAT[0]
DATA[38]
DATA[35]
DATA[32]
DATA[31]
VDDEXT
VDDINT
GND
GND
GND
GND
GND
GND
GND
GND
VDDINT
VDDEXT
L1DAT[2]
L2DAT[6]
L2DAT[4]
L2CLK
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
G01
G02
G03
G04
G05
G06
G07
G08
G09
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
DATA[28]
DATA[25]
DATA[20]
DATA[19]
DATA[12]
VDDEXT
VDDINT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDEXT
TFS0
L1DAT[7]
L0CLK
L0DAT[3]
L0DAT[1]
L1CLK
DATA[40]
DATA[39]
DATA[37]
DATA[36]
VDDEXT
VDDINT
GND
GND
GND
GND
GND
GND
GND
GND
VDDINT
VDDEXT
L2DAT[5]
L2ACK
L2DAT[3]
L2DAT[1]
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
H01
H02
H03
H04
H05
H06
H07
H08
H09
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
DATA[44]
DATA[43]
DATA[42]
DATA[41]
VDDEXT
VDDINT
GND
GND
J01
J02
J03
J04
J05
J06
J07
J08
CLK_CFG_0
DATA[46]
DATA[45]
DATA[47]
VDDEXT
VDDINT
GND
GND
K01
K02
K03
K04
K05
K06
K07
K08
CLKIN
CLK_CFG_1
AGND
CLK_CFG_2
VDDEXT
VDDINT
GND
GND
L01
L02
L03
L04
L05
L06
L07
L08
AVDD
CLK_CFG_3
CLKOUT
NC
VDDEXT
VDDINT
GND
GND
M01
M02
M03
M04
M05
M06
M07
M08
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ADSP-21160N
Table 32. 400-ball Metric PBGA Pin Assignments (Continued)
Pin Name PBGA Pin# Pin Name
PBGA Pin# Pin Name
PBGA Pin# Pin Name
PBGA Pin#
GND
GND
GND
GND
GND
GND
VDDINT
VDDEXT
L2DAT[2]
L2DAT[0]
HBG
HBR
NC
NC
DATA[48]
DATA[51]
VDDEXT
VDDINT
GND
GND
GND
GND
GND
GND
GND
GND
VDDINT
VDDEXT
L3DAT[5]
L3DAT[6]
L3DAT[4]
L3CLK
J09
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
N01
N02
N03
N04
N05
N06
N07
N08
N09
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
GND
GND
GND
GND
GND
GND
VDDINT
VDDEXT
BR6
BR5
BR4
BR3
DATA[49]
DATA[50]
DATA[52]
DATA[55]
VDDEXT
VDDINT
GND
GND
GND
GND
GND
GND
GND
GND
VDDINT
VDDEXT
L3DAT[2]
L3DAT[1]
L3DAT[3]
L3ACK
K09
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
P01
P02
P03
P04
P05
P06
P07
P08
P09
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
GND
GND
GND
GND
GND
GND
VDDINT
VDDEXT
BR2
BR1
ACK
REDY
DATA[53]
DATA[54]
DATA[57]
DATA[60]
VDDEXT
VDDINT
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDEXT
L4DAT[5]
L4DAT[6]
L4DAT[7]
L3DAT[0]
L09
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
R01
R02
R03
R04
R05
R06
R07
R08
R09
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
GND
GND
GND
GND
GND
GND
VDDINT
VDDEXT
PAGE
SBTS
PA
L3DAT[7]
DATA[56]
DATA[58]
DATA[59]
DATA[63]
VDDEXT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDEXT
L4DAT[3]
L4ACK
L4CLK
L4DAT[4]
M09
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
T01
T02
T03
T04
T05
T06
T07
T08
T09
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
DATA[61]
DATA[62]
ADDR[3]
ADDR[2]
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
L5DAT[7]
U01
U02
U03
U04
U05
U06
U07
U08
U09
U10
U11
U12
U13
U14
U15
U16
U17
ADDR[4]
ADDR[6]
ADDR[7]
ADDR[10]
ADDR[14]
ADDR[18]
ADDR[22]
ADDR[25]
ADDR[28]
ID0
ADDR[1]
MS1
CS
RDL
DMAR2
L5DAT[0]
L5DAT[2]
V01
V02
V03
V04
V05
V06
V07
V08
V09
V10
V11
V12
V13
V14
V15
V16
V17
ADDR[5]
ADDR[9]
ADDR[12]
ADDR[15]
ADDR[17]
ADDR[20]
ADDR[23]
ADDR[26]
ADDR[29]
ID1
ADDR[0]
BMS
MS2
CIF
RDH
DMAG2
LBOOT
W01
W02
W03
W04
W05
W06
W07
W08
W09
W10
W11
W12
W13
W14
W15
W16
W17
ADDR[8]
ADDR[11]
ADDR[13]
ADDR[16]
ADDR[19]
ADDR[21]
ADDR[24]
ADDR[27]
ADDR[30]
ADDR[31]
ID2
BRST
MS0
MS3
WRH
WRL
DMAG1
Y01
Y02
Y03
Y04
Y05
Y06
Y07
Y08
Y09
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
REV. PrB
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
51
PRELIMINARY TECHNICAL DATA
April 2002
For current information contact Analog Devices at 800/262-5643
ADSP-21160N
Table 32. 400-ball Metric PBGA Pin Assignments (Continued)
Pin Name PBGA Pin# Pin Name
PBGA Pin# Pin Name
PBGA Pin# Pin Name
L4DAT[0] U18
L4DAT[1] U19
L4DAT[2] U20
V18
V19
V20
W18
W19
W20
L5ACK
L5DAT[4]
L5DAT[6]
L5DAT[1]
L5DAT[3]
L5DAT[5]
PBGA Pin#
DMAR1
EBOOT
L5CLK
Y18
Y19
Y20
400-BALL METRIC PBGA PIN CONFIGURATIONS (BOTTOM VIEW, SUMMARY)
20
18
19
16
17
14
15
12
13
10
11
8
9
6
7
4
5
2
3
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
K EY :
VDDINT
GND*
AVDD
VDDEXT
AGND
I/O SIGNALS
NO CONNECTION
* USE THE CENTER BLOCK OF GROUND PINS (PBGA BALLS: F7-14, G7-14, H7-14, J7-14,
K7-14, L7-14, M7-14, N7-14, P7-14, R7-15) TO PROVIDE THERMAL PATHWAYS TO YOUR
PRINTED CIRCUIT BOARD’S GROUND PLANE.
REV. PrB
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
52
PRELIMINARY TECHNICAL DATA
April 2002
For current information contact Analog Devices at 800/262-5643
ADSP-21160N
OUTLINE DIMENSIONS
The ADSP-21160N comes in a 27mm ⴛ 27mm, 400-ball
Metric PBGA package with 20 rows of balls.
400-BALL METRIC PBGA (B-400)
27.20
27.00 SQ
26.80
20 18 16 14 12 10 8 6 4 2
19 17 15 13 11 9 7 5 3 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
24.13
BSC
SQ
24.10
24.00 SQ
23.90
1.27 (0.050)
BSC
BALL PITCH
BOTTOM VIEW
TOP VIEW
2.49
2.32
2.15
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS, EXCEPT (0.050) DIMENSION AT
BALL
PITCH IS IN INCHES.
2. CENTER FIGURES ARE NOMINAL DIMENSIONS.
3. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.30 OF ITS IDEAL
POSITION RELATIVE TO THE PACKAGE EDGES.
4. THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.15 OF ITS IDEAL
POSITION RELATIVE TO THE BALL GRID.
1.19
1.17
1.15
0.60
0.55
0.50
DETAIL A
SEATING
PLANE
0.70
0.60
0.50
0.90
0.75
0.60
BALL DIAMETER
0.20 MAX
DETAIL A
ORDERING GUIDE
1
Part Number1
Case Temperature
Range
Instruction Rate
On-Chip
SRAM
Operating Voltage
ADSP-21160NCB-TBD
ADSP-21160NKB-95
–40°C to 100°C
0°C to 85°C
TBD MHz
95 MHz
4M bits
4M bits
1.9 INT/3.3 EXT V
1.9 INT/3.3 EXT V
B = Plastic Ball Grid Array (PBGA) package.
REV. PrB
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
53