Data Sheet, V0.3, Sep. 2003 ar y TC1130 P re li m in 32-Bit Single-Chip Microcontroller Microcontrollers N e v e r s t o p t h i n k i n g . Edition 2003-09 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2003. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Data Sheet, V0.3, Sep. 2003 TC1130 32-Bit Single-Chip Microcontroller Microcontrollers N e v e r s t o p t h i n k i n g . TC1130 Advance Information Revision History: 2003-09 V0.3 Previous Version: Page Subjects (major changes since last revision) We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] 32-Bit Single-Chip Microcontroller TriCore Family TC1130 Advance Information • High Performance 32-bit TriCore V1.3 CPU with 4-Stage Pipeline • Floating Point Unit (FPU) • Dual Issue super-scalar implementation – MAC Instruction maximum triple issue • Circular Buffer and bit-reverse addressing modes for DSP algorithms • Flexible multi-master interrupt system • Very fast interrupt response time • Hardware controlled context switch for task switch and interrupts • Memory Management Unit (MMU) • On-chip Memory – 32 KByte Data Memory (SPRAM) – 32 KByte Code Memory (SPRAM) – 16 KByte Instruction Cache (ICACHE). – 64KByte SRAM Data Memory Unit (DMU) – 16 KByte Boot ROM • On-chip Bus Systems – 64-Bit High Performance Local Memory Bus (LMB) for fast access between caches and on-local memories and FPI Interface – On-chip Flexible Peripheral Interconnect Buses (FPI) for interconnections of functional units • DMA Controller with 8 channels for data transfer operations between peripheral units and memory locations – Two high speed Micro Link Interfaces (MLI0/1) for controller communication and emulation • Flexible External Bus Interface Unit (EBU) to access external data memories • One Multifunctional General Purpose Timer Units (GPTU) with three 32-bit timer/ counters • Two Capture and Compare units (CCU60/1) for PWM signal generation, each with – 3-channel, 16 bit Capture and Compare unit – 1-channel, 16 bit Compare unit • Three Asynchronous/Synchronous Serial Channels (ASC0/1/2) with baudrate generator, parity, framing and overrun error detection, support FIFO and IrDA data transmission • Two High Speed Synchronous Serial Channels (SSC0/1) with programmable data length, FIFO support and shift direction • One MultiCAN Module with four CAN nodes and 64 message buffers for high efficiency data handling • Fast Ethernet Controller with 10/100 Mbps MII-Based physical devices support Data Sheet 1 V0.3, 2003-09 TC1130 • USB module with compliance to USB Specification Revision 1.1, with support for 1.5MBaud to 12MBaud devices • Inter-IC (IIC) module with two physical IIC buses • Digital I/O ports with 3.3V IO capabilities • Level 2 On-chip Debug Support • Power Management System • Clock Generation Unit with PLL • Maximum CPU and Bus clock frequency at 150MHz without MMU and 120MHz with MMU • Ambient temperature under bias: -40° to +85°C • P-LBGA-208 package Data Sheet 2 V0.3, 2003-09 Figure 1 Data Sheet 3 Cedar_BLK Mem Checker 8 8 8 PORT4 MLI0 8 Boot-ROM 16 Kbytes LBCU LMB BUS MLI 1 SMIF DMA 8 channels DMU 64 KB SRAM 7 15 Ethernet MDIO D+ RxCLK TxCLK D- USB LFI Bridge 128 8 PORT3 16 4 13 GPTU 3 Timers 11 2 1 16 PORT2 8 DMA Bus, 32 Bi t MultiCAN CCU6 4nodes CCU61 CCU60 4 II C 2 Channels SBCU FPI BUS SSC0 SSC1 16 PORT1 2 ASC0 FIFO, IrDA Cerberus 16 PORT0 2 24 23 8 2 5 A[23:0] JTAGI/ O BRKIN XTAL1 XTAL2 Control EBU_Control External I nterrupts JTAG 7 VSS VDD AD[31: 0] 1.5-3.3 V TC1130 Bl ockDiagram 32 PLL ASC2 FIFO, IrDA EBU 2 2 3 ASC1 FIFO, IrDA SCU (PWR) Power Management, WatchdogTimer, Reset PMI (Program MemoryInterface) 32KB Scratch Pad RAM 16 KB Inst ruction Cache BRKOUT STM 64 16 1 3 3 3 1 6 3 2 1 1 OCDS2 TriCore 1M CPU CPS OCDS FPU MMU FPI Bus(Flexible Peripheral Interface), 32Bit DMI (Data MemoryInterface) 32 KBScratchPad RAM LMB (Local Memory Bus) 64Bit TC1130 Block Diagram TC1130 Block Diagram V0.3, 2003-09 TC1130 Logic Symbol General Control EBU Control PORST HDRST NMI HWCFG[0:2] RD RD/WR WAIT MR/W BFCLKI BFCLKO ALE BAA ADV CS[0:3] CSCOMB CKE Port 0 16-Bit 3 Port 1 16-Bit Port 2 16-Bit Port 3 16-Bit Port 4 8-Bit TRST TCK TDI TDO TMS BRKIN 4 TC1130 TRCLK MII_TxCLK MII_RxCLK MII_MDIO RAS CAS SDCLKI SDCLKO BC[0:3] D+ 4 USB, MLI0, SCU OCDS / JTAG Control Ethernet Clock USB DXTAL1 XTAL2 VDDOSC3 VSSOSC3 A[0:23] AD[0:31] Digital Circuitry Power Supply Alternate Functions GPTU, MultiCAN, SSC0/1, ASC1/2, CCU60, MLI0, EBU, SCU, External Interrupts SSC0/1, MultiCAN, Ethernet, EBU, SCU, OCDS ASC0/1/2, SSC0/1, IIC, CCU60, EBU, SCU SSC0/1, CCU61, MLI1, OCDS 9 VDD 6 VDDP 14 VSS Oscillator VDDOSC VSSOSC MCB04945mod Figure 2 Data Sheet TC1130 Logic Symbol 4 V0.3, 2003-09 TC1130 Pin Configuration A B C D E F G H J K Reser ved P3.10 P3.11 P3.12 P2.15 P2.14 P2.11 P2.9 P2.8 P2.7 15 P3.0 P3.1 P3.8 P3.2 P3.3 P3.6 P3.5 P3.9 P3.15 P2.12 VSS P0.3 P2.4 P0.1 P0.9 D- 15 14 P1.9 P1.10 P1.11 P1.14 P1.13 P1.15 P3.4 P3.7 P3.14 P2.13 HW CFG1 HW CFG0 P2.5 P2.3 P0.10 D+ 14 13 P1.8 P1.7 P1.5 V DDP VSS P1.12 VDD V SS V DDP P3.13 P2.10 VSS VDDP P2.2 P0.8 TDI 13 12 P1.6 P1.3 P1.1 P1.2 P2.6 P2.0 P0.5 TCK 12 11 BAA ADV P1.4 P1.0 P0.4 TRST 11 10 A17 A18 A19 A20 9 A16 WAIT CS2 CS0 8 A15 CS3 AD0 CS1 7 BC3 BC2 AD1 AD16 6 BC1 AD2 AD3 RAS 5 BC0 AD17 AD4 CAS 4 AD18 AD19 AD20 V DDP V SS AD28 AD29 V DDP V SS A14 CKE V DDP 3 AD5 AD21 AD7 AD25 AD11 AD12 AD15 AD30 A10 A11 A12 A13 2 AD6 AD22 AD8 AD9 AD26 AD27 AD31 AD14 A5 A6 A7 A8 A9 RD MII_ MII_ 2 RXCLK TXCLK 1 Reser ved AD23 AD24 BFCLKI BFCLKO AD10 A0 A1 A2 A3 A4 MII_ MDIO Reser ved A B K L M N P R T 16 C D L M V DDOSC XTAL1 208-Pin P-LBGA Package Pin Configuration (top view) for TC1130 N XTAL2 P R VDD VSS OSC3 P0.0 F Reser 16 ved V DD V SS V SS VDD P0.7 P0.2 P0.5 TDO 10 V DD V SS V SS VDD P0.11 P0.12 P4.1 TMS 9 V DD V SS V SS VDD P0.14 P0.13 P4.0 V DD V SS V SS VDD P4.2 P0.15 P4.5 NMI 7 P4.3 P4.4 P4.6 HW CFG2 6 PORST BRKIN 5 HDRST P4.7 E T AD13 SDCLKO SDCLKI G H J VSS A23 CS MR/W COMB A22 ALE TRCLK 8 A21 4 RD/WR 3 1 MCP04950mod Figure 3 Data Sheet TC1130 Pinning: P-BGA-208 Package (top view) 5 V0.3, 2003-09 TC1130 Table 1 Symbol Pin Definitions and Functions Pin P0 P0.0 N11 P0.1 P15 P0.2 P19 P0.3 M15 P0.4 R11 P0.5 R12 P0.6 R10 P0.7 N10 P0.8 R13 P0.9 R15 P0.10 R14 P0.11 N9 Data Sheet In PU/ Out PD1) Functions I/O Port 0 Port 0 is a 16-bit bidirectional general purpose I/O port which can be alternatively used for GPTU, MultiCAN, ASC1/2, SSC0/1, MLI0, EBU and SCU. GPTU_0 GPTU input/output line 0 RXD1B ASC1 receiver input/output B GPTU_1 GPTU input/output line 1 TXD1B ASC1 transmitter output B GPTU_2 GPTU input/output line 2 RXD2B ASC2 receiver input/output B GPTU_3 GPTU input/output line 3 TXD2B ASC2 transmitter output B GPTU_4 GPTU input/output line 4 SLSI1 SSC1 Slave Select input BREQ EBU Bus Request Output GPTU_5 GPTU input/output line 5 HOLD EBU Hold Request Input CC60_T12HR CCU0 Timer 12 hardware run BRKOUT#_B OCDS Break Out B GPTU_6 GPTU input/output line 6 HLDA EBU Hold Acknowledge Input/Output CC60_T13HR CCU0 Timer 13 hardware run SLSO0_0 SSC0 Slave Select output 0 GPTU_7 GPTU input/output line 7 SLSO1_0 SSC1 Slave Select output 0 RXDCAN0_A CAN node 0 receiver input A REQ0 External Trigger Input 0 TCLK0A MLI0 transmit channel clock output A TXDCAN0_A CAN node 0 transmitter output A TREADY0A MLI0 transmit channel ready input A REQ1 External Trigger Input 1 RXDCAN1_A CAN node 1 receiver input A REQ2 External Trigger Input 2 TVALID0A MLI0 transmit channel valid output A TXDCAN1_A CAN node 1 transmitter output A REQ3 External Trigger Input 3 TDATA0A MLI0 transmit channel data output A I/O I/O I/O O I/O I/O I/O O I/O I O I/O I I O I/O I/O I O I/O O I I O O I I I I O O I O PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC 6 V0.3, 2003-09 TC1130 Table 1 Pin Definitions and Functions(cont’d) Symbol Pin In PU/ Out PD1) P0.12 P9 P0.13 P8 P0.14 N8 P0.15 P7 I I I O I O I I I O I I Data Sheet PUC PUC PUC PUC Functions RXDCAN2 RCLK0A REQ4 TXDCAN2 REQ5 RREADY0A RXDCAN3 REQ6 RVALID0A TXDCAN3 REQ7 RDATA0A 7 CAN node 2 receiver input MLI0 receive channel clock input A External Trigger Input 4 CAN node 2 transmitter output External Trigger Input 5 MLI0 receive channel ready output A CAN node 3 receiver input External Trigger Input 6 MLI0 receive channel valid input A CAN node 3 transmitter output External Trigger Input 7 MLI0 receive channel data input A V0.3, 2003-09 TC1130 Table 1 Symbol Pin Definitions and Functions(cont’d) Pin P1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 In PU/ Out PD1) Functions I/O Port 1 Port 1 serves as 16-bit bidirectional general purpose I/ O port which can be used for input/output for Ethernet controller, MultiCAN, CAN, OCDS L2, SSC0/1, EBU and SCU MII_TXD0 Ethernet controller transmit data output line 0 RXDCAN0_B CAN node 0 receiver input B SWCFG0 Software configuration 0 OCDSA_0 OCDS L2 Debug Line A0 MII_TXD1 Ethernet controller transmit data output line 1 SWCFG1 Software configuration 1 TXDCAN0_B CAN node 0 transmitter output B OCDSA_1 OCDS L2 Debug Line A1 MII_TXD2 Ethernet controller transmit data output line 2 RXDCAN1_B CAN node 1 receiver input B SWCFG2 Software configuration 2 OCDSA_2 OCDS L2 Debug Line A2 MII_TXD3 Ethernet controller transmit data output line 3 TXDCAN1_B CAN node 1 transmitter output B SWCFG3 Software configuration 3 OCDSA_3 OCDS L2 Debug Line A3 MII_TXER Ethernet controller transmit error output line SWCFG4 Software configuration 4 OCDSA_4 OCDS L2 Debug Line A4 MII_TXEN Ethernet controller transmit enable output line SWCFG5 Software configuration 5 OCDSA_5 OCDS L2 Debug Line A5 MII_MDC Ethernet controller management data clock output line SWCFG6 Software configuration 6 OCDSA_6 OCDS L2 Debug Line A6 D11 O PUC C12 I I O O PUC D12 I O O O PUC B12 I I O O PUC C11 O I O O PUC C13 I O O PUC A12 I O O PUC I O Data Sheet 8 V0.3, 2003-09 TC1130 Table 1 Pin Definitions and Functions(cont’d) Symbol Pin In PU/ Out PD1) Functions P1.7 B13 I PUC MII_RXDV P1.8 A13 P1.9 A14 P1.10 B14 I O I I O I I O I C14 I O I F13 I O O I E14 I O O O D14 I O O I P1.11 P1.12 P1.13 P1.14 P1.15 Data Sheet F14 O I O I O I O PUC SWCFG7 OCDSA_7 MII_CRS SWCFG8 OCDSA_8 MII_COL SWCFG9 OCDSA_9 MII_RXD0 PUC SWCFG10 OCDSA_10 MII_RXD1 PUC SWCFG11 OCDSA_11 SLSO0_1 MII_RXD2 PUC SWCFG12 OCDSA_12 SLSO1_1 MII_RXD3 PUC SWCFG13 OCDSA_13 SLSO0_2 MII_RXER PUC PUC PUC SLSO1_2 SWCFG14 OCDSA_14 SLSI0 RMW SWCFG15 OCDSA_15 9 Ethernet Controller receive data valid input line Software configuration 7 OCDS L2 Debug Line A7 Ethernet Controller carrier input line Software configuration 8 OCDS L2 Debug Line A8 Ethernet Controller collision input line Software configuration 9 OCDS L2 Debug Line A9 Ethernet Controller receive data input line 0 Software configuration 10 OCDS L2 Debug Line A10 Ethernet Controller receive data input line 1 Software configuration 11 OCDS L2 Debug Line A1 SSC0 Slave Select output 1 Ethernet Controller receive data input line 2 Software configuration 12 OCDS L2 Debug Line A12 SSC1 Slave Select output 1 Ethernet Controller receive data input line 3 Software configuration 13 OCDS L2 Debug Line A13 SSC0 Slave Select output 2 Ethernet Controller receive error input line SSC1 Slave Select output 2 Software configuration 14 OCDS L2 Debug Line A14 SSC0 Slave Select Input EBU Read Modify Write Software configuration 15 OCDS L2 Debug Line A15 V0.3, 2003-09 TC1130 Table 1 Symbol Pin Definitions and Functions(cont’d) Pin P2 In PU/ Out PD1) Functions I/O Port 2 Port 2 is a 16-bit bidirectional general purpose I/O port which can be alternatively used for ASC0/1/2, SSC0/1, CCU0, IIC, EBU and SCU. RXD0 ASC0 receiver input/output line CSEMU EBU Chip Select Output for Emulator Region TXD0 ASC0 transmitter output line TESTMODE Test Mode Select Input MRST0 SSC0 master receive / slave transmit input/output MTSR0 SSC0 master transmit / slave receive input/output SCLK0 SSC0 clock input/output line COUT60_3 CCU0 compare channel 3 output MRST1A SSC1 master receive / slave transmit input/output A CC60_0 CCU0 input/output of capture/compare channel 0 MTSR1A SSC1 master transmit / slave receive input/output A COUT60_0 CCU0 output of capture/compare channel 0 SCLK1A SSC1 clock input/output line A CC60_1 CCU0 input/output of capture/ compare channel 1 RXD1A ASC1 receiver input/output line A COUT60_1 CCU0 output of capture/compare channel 1 TXD1A ASC1 transmitter output line A CC60_2 CCU0 input/output of capture/ compare channel 2 RXD2A ASC2 receiver input/output line A COUT60_2 CCU0 output of capture/compare channel 2 TXD2A ASC2 transmitter output line A SDA0 IIC Serial Data line 0 CTRAP0 CCU0 trap input SLSO0_3 SSC0 Slave Select output 3 P2.0 P12 I/O O PUC P2.1 P11 PUC P2.2 P13 O I I/O P2.3 P14 I/O PUC P2.4 P2.5 N15 N14 I/O O I/O PUC PUC P2.6 N12 I/O PUC PUC I/O P2.7 K16 O PUC P2.8 J16 I/O I/O PUC H16 I/O O PUC L13 O I/O PUC G16 I/O O PUC P2.9 P2.10 P2.11 P2.12 Data Sheet K15 O I/O I O 10 V0.3, 2003-09 TC1130 Table 1 Pin Definitions and Functions(cont’d) Symbol Pin In PU/ Out PD1) P2.13 K14 P2.14 F16 P2.15 E16 I/O I O I I/O O I I/O O Data Sheet Functions SCL0 CCPOS0_0 SLSO1_3 CCPOS0_1 SDA1 SLSO0_4 CCPOS0_2 SCL1 SLSO1_4 11 IIC clock line 0 CCU0 Hall input signal 0 SSC1 Slave Select output 3 CCU0 Hall input signal 1 IIC Serial Data line 1 SSC0 Slave Select output 4 CCU0 Hall input signal 2 IIC clock line 1 SSC1 Slave Select output 4 V0.3, 2003-09 TC1130 Table 1 Symbol Pin Definitions and Functions(cont’d) Pin P3 P3.0 A15 P3.1 B15 P3.2 In PU/ Out PD1) Functions I/O Port 3 Port 3 is a 16-bit bidirectional general purpose I/O port which can be alternatively used for MLI1, CCU1, SSC0/1 and OCDS Level 2 debug lines. OCDSB_0 OCDS L2 Debug Line B0 COUT61_3 CCU1 compare channel 3 output OCDSB_1 OCDS L2 Debug Line B1 CC61_0 CCU1 input/output of capture/ compare channel 0 OCDSB_2 OCDS L2 Debug Line B2 COUT61_0 CCU1 output of capture/compare channel 0 OCDSB_3 OCDS L2 Debug Line B3 CC61_1 CCU1 input/output of capture/ compare channel 1 OCDSB_4 OCDS L2 Debug Line B4 COUT61_1 CCU1 output of capture/compare channel 1 OCDSB_5 OCDS L2 Debug Line B5 CC61_2 CCU1 input/output of capture/ compare channel 2 OCDSB_6 OCDS L2 Debug Line B6 COUT61_2 CCU1 output of capture/compare channel 2 OCDSB_7 OCDS L2 Debug Line B7 CTRAP1 CCU1 trap input SLSO0_5 SSC0 Slave Select output 5 OCDSB_8 OCDS L2 Debug Line B8 CCPOS1_0 CCU1 Hall input signal 0 TCLK1 MLI1 transmit channel clock output SLSO1_5 SSC1 Slave Select output 5 OCDSB_9 OCDS L2 Debug Line B9 CCPOS1_1 CCU1 Hall input signal 1 TREADY1 MLI1 transmit channel ready input SLSO0_6 SSC0 Slave Select output 6 OCDSB_10 OCDS L2 Debug Line B10 CCPOS1_2 CCU1 Hall input signal 2 TVALID1 MLI1 transmit channel valid output SLSO1_6 SSC1 Slave Select output 6 O O O I/O PUC D15 O O PUC P3.3 E15 O I/O PUC P3.4 G14 O O PUC P3.5 G15 O I/O PUC P3.6 F15 O O PUC P3.7 H14 PUC P3.8 C15 P3.9 H15 P3.10 B16 O I O O I O O O I I O O I O O Data Sheet PUC PUC PUC PUC 12 V0.3, 2003-09 TC1130 Table 1 Pin Definitions and Functions(cont’d) Symbol Pin In PU/ Out PD1) P3.11 C16 PUC P3.12 D16 P3.13 K13 O O O I O I O I O O I/O P3.14 J14 O I I/O PUC OCDSB_14 RVALID1 MTSR1B P3.15 J15 O I I/O PUC OCDSB_15 RDATA1 SCLK1B Data Sheet PUC PUC Functions OCDSB_11 TDATA1 SLSO0_7 CC61_T12HR OCDSB_12 RCLK1 SLSO1_7 CC61_T13HR OCDSB_13 RREADY1 MRST1B 13 OCDS L2 Debug Line B11 MLI1 transmit channel data output SSC0 Slave Select output 7 CCU1 Timer 12 hardware run OCDS L2 Debug Line B12 MLI1 receive channel clock input SSC1 Slave Select output 7 CCU1 Timer 13 hardware run OCDS L2 Debug Line B13 MLI1 receive channel ready output SSC1 master receive / slave transmit input/output B OCDS L2 Debug Line B14 MLI1 receive channel valid input SSC1 master transmit / slave receive input/output B OCDS L2 Debug Line B15 MLI1 receive channel data input SSC1 clock input/output line B V0.3, 2003-09 TC1130 Table 1 Symbol Pin Definitions and Functions(cont’d) Pin P4 In PU/ Out PD1) Functions I/O Port 4 Port 4 is a 8-bit bidirectional general purpose I/O port which can be alternatively used for USB, MLI0 and SCU. USBCLK 48MHz input clock TCLK0B MLI0 transmit channel clock output B RCVI USB data input TREADY0B MLI0 transmit channel ready input B VPI USB D+ CMOS level mirror of differential signal TVALID0B MLI0 transmit channel valid output B VMI USB D- CMOS level mirror of differential signal TDATA0B MLI0 transmit channel data output B VPO USB D+ CMOS level output RCLK0B MLI0 receive channel clock input B VMO USB D- CMOS level output RREADY0B MLI0 receive channel ready output B USBOE Direction select for transmit or receive RVALID0B MLI0 receive channel valid input B RDATA0B MLI0 receive channel data input B BRKOUT#_A OCDS Break Out A P4.0 R8 P4.1 R9 P4.2 N7 I O I I I P4.3 N6 O I O O I O O O I I O PUC PUC PUC PUC P4.4 P6 P4.5 R7 P4.6 R6 P4.7 P5 HDRST N5 I/O PUA Hardware Reset Input/Reset Indication Output Assertion of this bidirectional open-drain pin causes a synchronous reset of the chip through external circuitry. This pin must be driven for a minimum duration. The internal reset circuitry drives this pin in response to a power-on, hardware, watchdog and power-down wake-up reset for a specific period of time. For a software reset, activation of this pin is programmable. PORST R5 I PUC Power-on Reset Input A low level on PORST causes an asynchronous reset of the entire chip. PORST is a fully asynchronous level sensitive signal. NMI T7 I PUC Non-Maskable Interrupt Input A high-to-low transition on this pin causes a NMI-Trap request to the CPU. Data Sheet PUC PUC PUC PUC 14 V0.3, 2003-09 TC1130 Table 1 Pin Definitions and Functions(cont’d) Symbol Pin In PU/ Out PD1) Functions TRST T11 I PDC JTAG Module Reset/Enable Input A low level at this pin resets and disables the JTAG module. A high level enables the JTAG module. TCK T12 I PUC JTAG Module Clock Input TDI T13 I PUC JTAG Module Serial Data Input TDO T10 O JTAG Module Serial Data Output TMS T9 I PUC JTAG Module State Machine Control Input TRCLK T8 O Trace Clock for OCDS_L2 Lines HWCFG0 M14 HWCFG1 L14 HWCFG2 T6 I I I PUC PUC PDC Hardware Configuration Inputs The Configuration Inputs define the boot options of the TC1130 after a hardware invoked reset operation. BRKIN T5 I PUC OCDS Break Input A low level on this pin causes a break in the chip’s execution when the OCDS is enabled. In addition, the level of this pin during power-on reset determines the boot configuration. MII_ TXCLK T2 I PDC Ethernet Controller Transmit Clock MII_TXD[3:0] and MII_TXEN are driven off the rising edge of the MII_TXCLK by the core and sampled by the PHY on the rising edge of the MII_TXCLK. MII_ RXCLK R2 I PDC Ethernet Controller Receive Clock MII_RXCLK is a continuous clock. Its frequency is 25 MHz for 100 Mbps operation, and 2.5 MHz for 10Mbps. MII_RXD[3:0], MII_RXDV and MII_EXER are driven by the PHY off the falling edge of MII_RXCLK and sampled on the rising edge of MII_RXCLK. MII_ MDIO R1 I/O PDA Ethernet Controller Management Data Input / Output When a read command is being executed, data which is clocked out of the PHY will be presented on the input line. When the Core is clocking control or data onto the MII_MDIO line, the signal will carry the information. D+ T14 I/O USB D+ data line D- T15 I/O USB D- data line Data Sheet 15 V0.3, 2003-09 TC1130 Table 1 Pin Definitions and Functions(cont’d) Symbol Pin In PU/ Out PD1) CS0 CS1 CS2 CS3 D9 D8 C9 B8 O O O O PUC PUC PUC PUC EBU Chip Select Output Line 0 EBU Chip Select Output Line 1 EBU Chip Select Output Line 2 EBU Chip Select Output Line 3 Each corresponds to a programmable region. Only one can be active at one time. CSCOMB N3 O PUC EBU Chip Select Output for combination function (Overlay Memory and Global) SDCLKI J1 I SDRAM clock input (clock feedback). SDCLKO H1 O SDRAM clock output.Accesses to SDRAM devices are synchronized to this clock RAS D6 O PUC EBU SDRAM Row Address Strobe Output CAS D5 O PUC EBU SDRAM Column Address Strobe Output CKE L4 O PUC EBU SDRAM Clock Enable Output BFCLKI D1 I Burst FLASH clock input (clock feedback). BFCLKO E1 O RD P2 O PUC EBU Read Control Line Output in the master mode Input in the slave mode. RD/WR T3 O PUC EBU Write Control Line Output in the master mode Input in the slave mode. WAIT B9 I PUC EBU Wait Control Line ALE R3 O PDC EBU Address Latch Enable Output MR/W P3 O PUC EBU Motorola-style Read / Write Output BAA A11 O PUC EBU Burst Address Advance Output For advancing address in a burst flash access ADV B11 O PUC EBU Burst Flash Address Valid Output Data Sheet Functions Burst FLASH clock output. Accesses to Burst FLASH devices are synchronized to this clock. 16 V0.3, 2003-09 TC1130 Table 1 Symbol Pin Definitions and Functions(cont’d) Pin In PU/ Out PD1) Functions AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 C8 C7 B6 C6 C5 A3 A2 C3 C2 D2 F1 E3 F3 G1 H2 G3 D7 B5 A4 B4 C4 B3 B2 B1 C1 D3 E2 F2 F4 G4 H3 G2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC EBU Address / Data Bus Input / Output Lines EBU Address / Data Bus Line 0 EBU Address / Data Bus Line 1 EBU Address / Data Bus Line 2 EBU Address / Data Bus Line 3 EBU Address / Data Bus Line 4 EBU Address / Data Bus Line 5 EBU Address / Data Bus Line 6 EBU Address / Data Bus Line 7 EBU Address / Data Bus Line 8 EBU Address / Data Bus Line 9 EBU Address / Data Bus Line 10 EBU Address / Data Bus Line 11 EBU Address / Data Bus Line 12 EBU Address / Data Bus Line 13 EBU Address / Data Bus Line 14 EBU Address / Data Bus Line 15 EBU Address / Data Bus Line 16 EBU Address / Data Bus Line 17 EBU Address / Data Bus Line 18 EBU Address / Data Bus Line 19 EBU Address / Data Bus Line 20 EBU Address / Data Bus Line 21 EBU Address / Data Bus Line 22 EBU Address / Data Bus Line 23 EBU Address / Data Bus Line 24 EBU Address / Data Bus Line 25 EBU Address / Data Bus Line 26 EBU Address / Data Bus Line 27 EBU Address / Data Bus Line 28 EBU Address / Data Bus Line 29 EBU Address / Data Bus Line 30 EBU Address / Data Bus Line 31 BC0 BC1 BC2 BC3 A5 A6 B7 A7 O O O O PUC PUC PUC PUC EBU Byte Control Line 0 EBU Byte Control Line 1 EBU Byte Control Line 2 EBU Byte Control Line 3 Data Sheet 17 V0.3, 2003-09 TC1130 Table 1 Symbol Pin Definitions and Functions(cont’d) Pin In PU/ Out PD1) Functions EBU Address Bus Input / Output Lines EBU Address Bus Line 0 EBU Address Bus Line 1 EBU Address Bus Line 2 EBU Address Bus Line 3 EBU Address Bus Line 4 EBU Address Bus Line 5 EBU Address Bus Line 6 EBU Address Bus Line 7 EBU Address Bus Line 8 EBU Address Bus Line 9 EBU Address Bus Line 10 EBU Address Bus Line 11 EBU Address Bus Line 12 EBU Address Bus Line 13 EBU Address Bus Line 14 EBU Address Bus Line 15 EBU Address Bus Line 16 EBU Address Bus Line 17 EBU Address Bus Line 18 EBU Address Bus Line 19 EBU Address Bus Line 20 EBU Address Bus Line 21 EBU Address Bus Line 22 EBU Address Bus Line 23 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 K1 L1 M1 N1 P1 J2 K2 L2 M2 N2 J3 K3 L3 M3 K4 A8 A9 A10 B10 C10 D10 T4 R4 P4 O O O O O O O O O O O O O O O O O O O O O O O O PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC XTAL1 XTAL2 M16 N16 I O Oscillator/PLL/Clock Generator Input/Output Pins XTAL1 is the input to the main oscillator amplifier and input to the internal clock generator. XTAL2 is the output of the main oscillator amplifier circuit. For clocking the device from an external source, XTAL1 is driven with the clock signal while XTAL2 is left unconnected. For crystal oscillator operation XTAL1 and XTAL2 are connected to the crystal with the appropriate recommended oscillator circuitry. VDDOSC3 VSSOSC3 VDDOSC P16 Main Oscillator Power Supply (3.3V) R16 Main Oscillator Ground L16 Main Oscillator Power Supply (1.5V) Data Sheet 18 V0.3, 2003-09 TC1130 Table 1 Pin Definitions and Functions(cont’d) Symbol Pin In PU/ Out PD1) Functions VSSOSC VDD L15 Main Oscillator Ground G7, G8 G9 G10 G13 K7,K8 K9 K10 Core and Logic Power Supply (1.5V) VDDP D4, D13, H4, J13, M4, N13, Ports Power Supply (3.3V) VSS E4 E13 H7, H8 H9 H10 H13 J4,J7 J8,J9 J10 M13 N4 Ground N.C. A1, A16, T1, T16 Not Connected These pins must not be connected. 1) Refers to internal pull-up or pull-down device connected and corresponding type. The notation ‘’ indicates that the internal pull-up or pull-down device is not enabled. Data Sheet 19 V0.3, 2003-09 TC1130 Parallel Ports The TC1130 has 72 digital input/output port lines, which are organized into four parallel 16-bit ports and one parallel 8-bit port, Port P0 to Port P4 with 3.3V nominal voltage. The digital parallel ports can be all used as general purpose I/O lines or they can perform input/output functions for the on-chip peripheral units. An overview on the port-toperipheral unit assignment is shown in Figure 4. Alternate Functions GPIO GPIO 16 Alternate Functions 16 GPTU/ ASC1/ ASC2/ GPIO0 SSC0/ SSC1/ CCU60/ MultiCAN/ MLI0/ EBU/ SCU/ External Interrupts GPIO3 SSC0/ SSC1/ CCU61/ MLI1/ OCDS 16 SSC0/ SSC1/ MultiCAN/ GPIO1 Ethernet/ EBU/ SCU/ OCDS TC1130 8 GPIO4 USB/ MLI0/ SCU Parallel Ports 16 ASC0/ ASC1/ ASC2/ GPIO2 SSC0/ SSC1/ IIC/ CCU60/EBU/ SCU Figure 4 Data Sheet MCA04951mod Parallel Ports of the TC1130 20 V0.3, 2003-09 TC1130 Serial Interfaces The TC1130 includes five serial peripheral interface units: – – – – – Asynchronous/Synchronous Serial Interface (ASC) High-Speed Synchronous Serial Interface (SSC) Inter IC Serial Interface (IIC) Universal Serial Bus Interface (USB) Micro Link Serial Bus Interface (MLI) Asynchronous/Synchronous Serial Interface (ASC) Figure 5 shows a global view of the functional block of three Asynchronous/ Synchronous Serial interfaces (ASC0, ASC1 and ASC2). Each ASC Module, (ASC0/ASC1/ASC2) communicates with the external world via one pair of I/O lines. The RXD line is the receive data input signal (in Synchronous Mode also output). TXD is the transmit output signal. Clock control, address decoding, and interrupt service request control are managed outside the ASC Module kernel. The Asynchronous/Synchronous Serial Interfaces provide serial communication between the TC1130 and other microcontrollers, microprocessors or external peripherals. Each ASC supports full-duplex asynchronous communication and half-duplex synchronous communication. In Synchronous Mode, data is transmitted or received synchronous to a shift clock which is generated by the ASC internally. In Asynchronous Mode, 8-bit or 9-bit data transfer, parity generation, and the number of stop bits can be selected. Parity, framing, and overrun error detection are provided to increase the reliability of data transfers. Transmission and reception of data are double-buffered. For multiprocessor communication, a mechanism is included to distinguish address bytes from data bytes. Testing is supported by a loop-back option. A 13-bit baud rate generator provides the ASC with a separate serial clock signal that can be very accurately adjusted by a prescaler implemented as a fractional divider. Data Sheet 21 V0.3, 2003-09 TC1130 Clock Control fASC0 RXD_I0 Address Decoder Interrupt Control ASC0 Module (Kernel) RXD_I1 P2.0/ RXD0 RXD_O P2.1/ TXD0 TXD_O EIR TBIR TIR RIR to DMA Clock Control fASC1 P2.8/ RXD1A RXD_I0 Address Decoder Interrupt Control P2.9/ TXD1A RXD_I1 ASC1 Module (Kernel) RXD_O TXD_O EIR TBIR TIR RIR Port Control P0.0/ RXD1B P0.1/ TXD1B to DMA Clock Control fASC1 RXD_I0 Address Decoder Interrupt Control RXD_I1 ASC2 Module (Kernel) Data Sheet P2.11/ TXD2A RXD_O TXD_O EIR TBIR TIR RIR P0.2/ RXD2B P0.3/ TXD2B to DMA Figure 5 P2.10/ RXD2A MCB04485_mod General Block Diagram of the ASC Interfaces 22 V0.3, 2003-09 TC1130 Features: • Full-duplex asynchronous operating modes – 8-bit or 9-bit data frames, LSB first – Parity bit generation/checking – One or two stop bits – Baud rate from 4.6875 MBaud to 1.1 Baud (@ 75 MHz clock) • Multiprocessor mode for automatic address/data byte detection • Loop-back capability • Half-duplex 8-bit synchronous operating mode – Baud rate from 9.375 MBaud to 762.9 Baud (@ 75 MHz clock) • Support for IrDA data transmission up to 115.2 KBaud maximum. • Double buffered transmitter/receiver • Interrupt generation – On a transmitter buffer empty condition – On a transmit last bit of a frame condition – On a receiver buffer full condition – On an error condition (frame, parity, overrun error) • FIFO – 8 byte receive FIFO (RXFIFO) – 8 byte transmit FIFO (TXFIFO) – Independent control of RXFIFO and TXFIFO – 9-bit FIFO data width – Programmable Receive/Transmit Interrupt Trigger Level – Receive and Transmit FIFO filling level indication – Overrun error generation – Underflow error generation Data Sheet 23 V0.3, 2003-09 TC1130 High-Speed Synchronous Serial Interface (SSC) Figure 6 shows a global view of the functional blocks of two High-Speed Synchronous Serial interfaces (SSC0 and SSC1). Each SSC supports full-duplex and half-duplex serial synchronous communication up to 37.5 MBaud (@ 75 MHz module clock) with receive and transmit FIFO support. The serial clock signal can be generated by the SSC itself (master mode) or can be received from an external master (slave mode). Data width, shift direction, clock polarity and phase are programmable. This allows communication with SPI-compatible devices. Transmission and reception of data is double-buffered. A shift clock generator provides the SSC with a separate serial clock signal. Eight slave select inputs are available for slave mode operation. Eight programmable slave select outputs (chip selects) are supported in master mode. Features: • Master and slave mode operation – Full-duplex or half-duplex operation – Automatic pad control possible • Flexible data format – Programmable number of data bits: 2 to 16 bit – Programmable shift direction: LSB or MSB shift first – Programmable clock polarity: idle low or high state for the shift clock – Programmable clock/data phase: data shift with leading or trailing edge of the shift clock • Baud rate generation minimum at 572.2 Baud (@ 75 MHz module clock) • Interrupt generation – On a transmitter empty condition – On a receiver full condition – On an error condition (receive, phase, baud rate, transmit error) • Four-pin interface • Flexible SSC pin configuration • Up to eight slave select inputs in slave mode • Up to eight programmable slave select outputs SLSO in master mode – Automatic SLSO generation with programmable timing – Programmable active level and enable control • 4-stage receive FIFO (RXFIFO) and 4-stage transmit FIFO (TXFIFO) – Independent control of RXFIFO and TXFIFO – 2 to 16 bit FIFO data width – Programmable receive/transmit interrupt trigger level – Receive and transmit FIFO filling level indication – Overrun error generation – Underflow error generation Data Sheet 24 V0.3, 2003-09 TC1130 fSSC0 Clock Control Master fCLC0 Slave Slave Address Decoder SSC0 Module (Kernel) Master MRSTA MRSTB MTSR P2.2/MRST0 MTSRA MTSRB MRST P2.3/MTSR0 Port 2 Control SCLKA SCLKB SLCK P2.4/SCLK0 1) M/S Select Enable1) P2.12/SLSO03 P2.14/SLSO04 EIR TIR RIR Interrupt Control SLSI1 Slave SLSO0 SLSO[2:1] to DMA Master P1.15/SLSI0 SLSI[7:2] 1) Port 1 Control P1.11/SLSO01 P1.13/SLSO02 SLSO[4:3] SLSO[7:5] P0.6/SLSO00 Port 0 Control P0.4/SLSI1 P0.7/SLSO10 Slave fSSC1 Clock Control fCLC1 SLSI1 P3.7/SLSO05 SLSI[7:2] 1) P3.9/SLSO06 SLSO0 Port 3 Control SLSO[2:1] P3.11/SLSO07 P3.8/SLSO15 Master SLSO[4:3] P3.10/SLSO16 SLSO[7:5] P3.11/SLSO17 Address Decoder Port 1 Control SSC1 Module (Kernel) P1.12/SLSO11 P1.14/SLSO12 P2.13/SLSO13 P2.15/SLSO14 EIR TIR RIR Interrupt Control Master Slave to DMA 1) M/S Select Enable1) Slave Master MRSTA MRSTB MTSR MTSRA MTSRB MRST Data Sheet Port 2 Control SCLKA SCLKB SLCK 1) Figure 6 P2.5/MRST1A These lines are not connected P3.13/MRST1B P2.6/MTSR1A P3.14/MTSR1B P2.7SCLK1A P3.15/SCLK1B MCB04486_mod General Block Diagram of the SSC Interfaces 25 V0.3, 2003-09 TC1130 Inter IC Serial Interface (IIC) Figure 7 shows a global view of the functional blocks of the Inter IC Serial Interface (IIC). The IIC module has four I/O lines, located at Port 2. The IIC module is further supplied by a clock control, interrupt control, and address decoding logic. One DMA request can be generated by IIC module. Clock Control fIIC SDA0 P2.12/SDA0 SCL0 Address Decoder IIC Module INT_P Interrupt Control P2.13/SCL0 Port 2 Control SDA1 SCL1 P2.14/SDA1 P2.15/SCL1 INT_E INT_D to DMA Figure 7 General Block Diagram of the IIC Interface The on-chip IIC Bus module connects the platform buses to other external controllers and/or peripherals via the two-line serial IIC interface. One line is responsible for clock transfer and synchronization (SCL), the other is responsible for the data transfer (SDA). The IIC Bus module provides communication at data rates of up to 400 Kbit/s and features 7-bit addressing as well as 10-bit addressing. This module is fully compatible to the IIC bus protocol. The module can operate in three different modes: Master mode, where the IIC controls the bus transactions and provides the clock signal. Slave mode, where an external master controls the bus transactions and provides the clock signal. Multimaster mode, where several masters can be connected to the bus, i.e. the IIC can be master or slave. The on-chip IIC bus module allows efficient communication via the common IIC bus. The module unloads the CPU of low level tasks like • • • • • (De)Serialization of bus data. Generation of start and stop conditions. Monitoring the bus lines in slave mode. Evaluation of the device address in slave mode. Bus access arbitration in multimaster mode. Data Sheet 26 V0.3, 2003-09 TC1130 Features • • • • • • • Software compatible to V1.0 of C161RI. Extended buffer allows up to 4 send/receive data bytes to be stored. Selectable baud rate generation. Support of standard 100 KBaud and extended 400 KBaud data rates. Operation in 7-bit addressing mode or 10-bit addressing mode. Flexible control via interrupt service routines or by polling. Dynamic access to up to 2 physical IIC busses. Data Sheet 27 V0.3, 2003-09 TC1130 Universal Serial Bus Interface (USB) Figure 8 shows a global view of the functional blocks of the Universal Serial Bus Interface (USB). The USB module is further supplied by clock control, interrupt control, address decoding, and port control logic. One DMA request can be generated by USB module. Clock Control f USB USBCLKB P4.0 /USBCLK RCVIB P4.1 /RCVI VPIB Address Decoder VMIB VPOB ISR0 ISR1 ISR2 ISR3 Interrupt Control P4.2 /VPI Port 4 Control P4.4 /VPO VMOB USB Module (Kernel) P4.3 /VMI P4.5 /VMO USBOEB P4.6 /USBOE ISR4 ISR5 D+ ISR6 D- ISR7 To DMA Figure 8 General Block Diagram of the USB The USB handles all transactions between the serial USB bus and the internal (parallel) bus of the microcontroller. The USB module includes several units which are required to support data handling with the USB bus: the on-chip USB transceiver (optionally), the flexible USB buffer block with a 32 bit wide RAM, the buffer control unit with sub modules for USB and CPU memory access control, the UDC_IF device interface for USB protocol handling, the microcontroller interface unit (MCU) with the USB specific special function registers and the interrupt generation unit. A clock generation unit provides the clock signal for the USB module for full speed and low speed USB operation. Data Sheet 28 V0.3, 2003-09 TC1130 Features • • • • • • • • • • • • • • • • • • • • • • • USB1.1 Device Standard Interface Differential I/O allow cable length up to 5m without additional hardware at target’s end. Hot attach USB1.1 full speed device USB protocol handling in hardware Clock and data recovery from USB Bit stripping and bit stuffing functions CRC5 checking, CRC16 generation and checking Serial to parallel data conversion Maintenance of data synchronization bits (DATA0/DATA1 Toggle Bits) Supports multiple configurations, interfaces and alternate settings Sixteen endpoints with user configurable endpoint information Flexible intermediate buffering of transmission data Powerful data handling capability, FIFO-support Back-to-back transfers fully supported by module automatism Multi packet transfer without CPU load Handles data transfer with minimum CPU load Auto increment and single address modes selectable for easy data access Powerful interrupt generation Meets suspend power consumption restrictions in Power Down Mode Remote wakeup from USB bus activity Explicit support of setup information Enhanced status monitoring Data Sheet 29 V0.3, 2003-09 TC1130 Micro Link Serial Bus Interface (MLI) Figure 9 shows a global view of the functional blocks of two Micro Link Serial Bus Interfaces (MLI0 & MLI1). Clock Control f MLI0 TCLK TREADYA TVALIDA TDATA Address Decoder RCLKA Port 0 Control RREADYA RDATAA MLI0 Module (Kernel) DMA INT_O TCLK [3:0] TREADYB INT_O TVALIDB [7:4] TDATA RCLKB MLI Interface Port 4 Control f MLI1 P3.8 /TCLK1 TREADYA Address Decoder TVALIDA INT_O [1:0] INT_O DMA P4.4/RCLK0B P4.5/ RREADY0B P4.6/ RVALID0B P4.7/ RDATA0B TCLK Interrupt Control P4.0/ TCLK0B P4.1/ TREADY0B P4.2/ TVALID0B P4.3/ TDATA0B RREADYB RVALIDB RDATAB Clock Control P0.12/RCLK0A P0.13/ RREADY0A P0.14/ RVALID0A P0.15/ RDATA0A RVALIDA Interrupt Control P0.8/ TCLK0A P0.9/ TREADY0A P0.10/ TVALID0A P0.11/ TDATA0A [7:4] MLI1 Module (Kernel) TDATA RCLKA Port 3 Control RREADYA RVALIDA RDATAA MLI Interface P3.9 / TREADY1A P3.10 / TVALID1A P3.11 / TDATA1 P3.12/ RCLK1A P3.13 / RREADY1A P3.14 / RVALID1A P3.15 / RDATA1A MLI_Interfaces Figure 9 Data Sheet General Block Diagram of the MLI0 and MLI1 30 V0.3, 2003-09 TC1130 The Micro Link Serial Bus Interface is dedicated for the serial communication between controllers of the AUDO - NG family. The communication is intended to be fast and intelligent due to an address translation system, and it is not necessary to have any special program in the second controller. Features: • Serial communication from the MLI transmitter to MLI receiver of another controller • Module supports connection of each MLI with up to four MLI from other controllers (see implementation sub-chapter for details for this product) • Fully transparent read/write access supported (= remote programming) • Complete address range of target controller available • Special protocol to transfer data, address offset, or address offset and data • Error control using a parity bit • 32 - bits, 16 - bits, and 8 - bits data transfers • Address offset width: from 1 to 16 - bits • Baud rate: fMLI / 2 (symmetric shift clock approach), baud rate definition by the corresponding fractional divider Data Sheet 31 V0.3, 2003-09 TC1130 General Purpose Timer Unit Figure 10 shows a global view of all functional blocks of the General Purpose Timer Unit (GPTU). IN0 Clock Control fGPTU0 IN1 IN2 IN3 P0.0/GPTU_0 IN4 Address Decoder IN5 P0.1/GPTU_1 IN6 P0.2/GPTU_2 IN7 SR0 Interrupt Control Figure 10 GPTU Module Port 0 Control OUT0 SR1 OUT1 SR2 SR3 OUT2 OUT3 SR4 OUT4 SR5 OUT5 SR6 OUT6 SR7 OUT7 P0.3/GPTU_3 P0.4/GPTU_4 P0.5/GPTU_5 P0.6/GPTU_6 P0.7/GPTU_7 General Block Diagram of the GPTU Interface The GPTU consists of three 32-bit timers designed to solve such application tasks as event timing, event counting, and event recording. The GPTU communicates with the external world via eight I/O lines located at Port 0. The three timers of GPTU Module T0, T1, and T2, can operate independently from each other or can be combined: General Features: • • • • All timers are 32-bit precision timers with a maximum input frequency of fGPTU. Events generated in T0 or T1 can be used to trigger actions in T2 Timer overflow or underflow in T2 can be used to clock either T0 or T1 T0 and T1 can be concatenated to form one 64-bit timer Features of T0 and T1: • Each timer has a dedicated 32-bit reload register with automatic reload on overflow • Timers can be split into individual 8-, 16-, or 24-bit timers with individual reload registers Data Sheet 32 V0.3, 2003-09 TC1130 • Overflow signals can be selected to generate service requests, pin output signals, and T2 trigger events • Two input pins can define a count option Features of T2: • Count up or down is selectable • Operating modes: – Timer – Counter – Quadrature counter (incremental/phase encoded counter interface) • Options: – External start/stop, one-shot operation, timer clear on external event – Count direction control through software or an external event – Two 32-bit reload/capture registers • Reload modes: – Reload on overflow or underflow – Reload on external event: positive transition, negative transition, or both transitions • Capture modes: – Capture on external event: positive transition, negative transition, or both transitions – Capture and clear timer on external event: positive transition, negative transition, or both transitions • Can be split into two 16-bit counter/timers • Timer count, reload, capture, and trigger functions can be assigned to input pins. T0 and T1 overflow events can also be assigned to these functions. • Overflow and underflow signals can be used to trigger T0 and/or T1 and to toggle output pins • T2 events are freely assignable to the service request nodes. Data Sheet 33 V0.3, 2003-09 TC1130 Capture/Compare Unit 6 (CCU6) Figure 11 shows a global view of all functional blocks of two Capture/Compare Units (CCU60 & CCU61). Both of the CCU6 modules is further supplied by clock control, interrupt control, address decoding, and port control logic. One DMA request can be generated by each CCU6 module. Each CCU6 provides two independent timers (T12, T13), which can be used for PWM generation, especially for AC-motor control. Additionally, special control modes for block commutation and multi-phase machines are supported. Timer 12 Features • Three capture/compare channels, each channel can be used either as capture or as compare channel. • Generation of a three-phase PWM supported (six outputs, individual signals for highside and lowside switches) • 16 bit resolution, maximum count frequency = peripheral clock • Dead-time control for each channel to avoid short-circuits in the power stage • Concurrent update of the required T12/13 registers • Center-aligned and edge-aligned PWM can be generated • Single-shot mode supported • Many interrupt request sources • Hysteresis-like control mode Timer 13 Features • • • • • One independent compare channel with one output 16 bit resolution, maximum count frequency = peripheral clock Can be synchronized to T12 Interrupt generation at period-match and compare-match Single-shot mode supported Additional Features • • • • • • • Block commutation for Brushless DC-drives implemented Position detection via Hall-sensor pattern Automatic rotational speed measurement for block commutation Integrated error handling Fast emergency stop without CPU load via external signal (CTRAP) Control modes for multi-channel AC-drives Output levels can be selected and adapted to the power stage Data Sheet 34 V0.3, 2003-09 TC1130 /CTRAP fCCU Clock Control P2.12 /CTRAP0 CCPOS0 P2.13 /CCPOS00 CCPOS1 P2.14 /CCPOS01 CCPOS2 Address Decoder P2.15 /CCPOS02 CC60 P2.6 /CC600 COUT60 CCU60 Module (Kernel) CC61 COUT61 P2.7 /COUT600 Port 2 Control CC62 P2.8 /CC601 P2.9 /COUT601 P2.10 /CC602 COUT62 P2.11 /COUT602 To DMA COUT63 T12HR SRC0 SRC1 SRC2 SRC3 T13HR /CTRAP CCPOS0 CCPOS1 CCPOS2 CC60 Interrupt Control COUT60 CCU61 Module (Kernel) CC61 Port 3 Control COUT61 CC62 SRC0 SRC1 SRC2 SRC3 P0.5 / CCU60_T12HR P0.6 / CCU60_T13HR P3.7 /CTRAP1 P3.8 /CCPOS10 P3.9 /CCPOS11 P3.10 /CCPOS12 P3.1 /CC610 P3.2 /COUT610 P3.3 /CC611 P3.4 /COUT611 P3.5 /CC612 COUT62 P3.6 /COUT612 COUT63 T12HR To DMA P2.5 /COUT603 T13HR P3.0 /COUT613 P3.11 / CCU61_T12HR P3.12 / CCU61_T13HR TC1130_CCU6_imple Figure 11 Data Sheet General Block Diagram of the CCU6 35 V0.3, 2003-09 TC1130 MultiCAN Figure 12 shows a global view of all functional blocks of the MultiCAN module. fCAN Clock Control Address Decoder Message Object Buffer 128 Objects CAN Node 3 TXDC3 CAN Node 2 TXDC2 INT_O15 RXDC3 RXDC2 TXDC1A Linked List Control CAN Node 1 CAN Node 0 INT_O [3:0] Port 0 Control RXDC1A TXDC1B RXDC1B TXDC0A DMA Interrupt Control P0.15 / TXDCAN3 P0.14 / RXDCAN3 MultiCAN Module Kernel fCLC INT_O [15:4] RXDC0A TXDC0B RXDC0B Port 1 Control CAN Control P0.13 / TXDCAN2 P0.12 / RXDCAN2 P0.11 / TXDCAN1A P0.10 / RXDCAN1A P0.9 / TXDCAN0A P0.8 / RXDCAN0A P1.1 / TXDCAN0B P1.0 / RXDCAN0B P1.3 / TXDCAN1B P1.2 / RXDCAN1B MultiCAN_TC1130_impl Figure 12 General Block Diagram of the MultiCAN Interfaces The MultiCAN module contains 4 Full-CAN nodes operating independently or exchanging data and remote frames via a gateway function. Transmission and reception of CAN frames is handled in accordance to CAN specification V2.0 part B (active). Each CAN node can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. All CAN nodes share a common set of message objects, where each message object may be individually allocated to one of the CAN nodes. Besides serving as a storage container for incoming and outgoing frames, message objects may be combined to build gateways between the CAN nodes or to setup a FIFO buffer. The message objects are organized in double chained lists, where each CAN node has it’s own list of message objects. A CAN node stores frames only into message objects that are allocated to the list of the CAN node. It only transmits messages from objects of this list. A powerful, command driven list controller performs all list operations. Data Sheet 36 V0.3, 2003-09 TC1130 The bit timings for the CAN nodes are derived from the peripheral clock (fCAN) and are programmable up to a data rate of 1 MBaud. A pair of receive and transmit pins connects each CAN node to a bus transceiver. Features • • • • • • • • • • Compliant to ISO 11898. CAN functionality according to CAN specification V2.0 B active. Dedicated control registers are provided for each CAN node. A data transfer rate up to 1 MBaud is supported. Flexible and powerful message transfer control and error handling capabilities are implemented. Advanced CAN bus bit timing analysis and baud rate detection can be performed for each CAN node via the frame counter. Full-CAN functionality: A set of 128 message objects can be individually – allocated (assigned) to any CAN node – configured as transmit or receive object – setup to handle frames with 11-bit or 29-bit identifier – counted or assigned a timestamp via a frame counter – configured to remote monitoring mode Advanced Acceptance Filtering: – Each message object provides an individual acceptance mask to filter incoming frames. – A message object can be configured to accept only standard or only extended frames or to accept both standard and extended frames. – Message objects can be grouped into 4 priority classes. – The selection of the message to be transmitted first can be performed on the basis of frame identifier, IDE bit and RTR bit according to CAN arbitration rules. Advanced Message Object Functionality: – Message Objects can be combined to build FIFO message buffers of arbitrary size, which is only limited by the total number of message objects. – Message objects can be linked to form a gateway to automatically transfer frames between 2 different CAN buses. A single gateway can link any two CAN nodes. An arbitrary number of gateways may be defined. Advanced Data Management: – The Message objects are organized in double chained lists. – List reorganizations may be performed any time, even during full operation of the CAN nodes. – A powerful, command driven list controller manages the organization of the list structure and ensures consistency of the list. – Message FIFOs are based on the list structure and can easily be scaled in size during CAN operation. Data Sheet 37 V0.3, 2003-09 TC1130 – Static Allocation Commands offer compatibility with TwinCAN applications, which are not list based. • Advanced Interrupt Handling: – Up to 16 interrupt output lines are available. Most interrupt requests can be individually routed to one of the 16 interrupt output lines. – Message postprocessing notifications can be flexibly aggregated into a dedicated register field of 256 notification bits. Data Sheet 38 V0.3, 2003-09 TC1130 Ethernet Controller The MAC controller implements the IEEE 802.3 and operates either at 100 Mbps or 10 Mbps. Figure 13 shows a global view of the Ethernet Controller module with the module specific interface connections. Ethernet Controller P1.14 / MII_RxER P1.13 / MII_RxD[3] P1.12 / MII_RxD[2] P1.11 / MII_RxD[1] P1.10 / MII_RxD[0] P1.9 / MII_COL DMUR RB P1.8 / MII_CRS Port Control P1.7 / MII_RxDV P1.6 / MII_MDC FPI (M/S) MAC MII P1.5 / MII_TxEN P1.4 / MII_TxER P1.3 / MII_TxD[3] DMUT TB P1.2 / MII_TxD[2] P1.1 / MII_TxD[1] P1.0 / MII_TxD[0] MII_TxCLK MII_TxCLK MII_TDIO MCB04942mod Figure 13 General Block Diagram of the Ethernet Controller The Ethernet controller comprises the following functional blocks: 1. 2. 3. 4. 5. Media Access Controller (MAC) Receive Buffer (RB) Transmit Buffer (TB) Data Management Unit in Receive Direction (DMUR) Data Management Unit in Transmit Direction (DMUT) Data Sheet 39 V0.3, 2003-09 TC1130 RB as well as TB provides on-chip data buffering whereas DMUR and DMUT perform data transfer from/to the shared memory. Two interfaces are provided by the Ethernet Controller Module: 1. MII interface for connection of Ethernet PHYs via eighteen Input / Output lines 2. Master/slave FPI bus interface for connection to the on-chip system bus for data transfer as well as configuration. Features • • • • • • • Media Independent Interface (MII) according to IEEE 802.3 Support 10 or 100 Mbps MII-based Physical devices. Support Full Duplex Ethernet. Support data transfer between Ethernet Controller and COM-DRAM. Support data transfer between Ethernet Controller and SDRAM via EBU. 256 x 32 bit Receive buffer and Transmit buffer each. Support burst transfers up to 8 x 32 Byte. Media Access Controller (MAC) • • • • • • • • • • • 100/10-Mbps operations Full IEEE 802.3 compliance Station management signaling Large on-chip CAM (Content Addressable Memory) Full duplex mode 80-byte transmit FIFO 16-byte receive FIFO PAUSE Operation Flexible MAC Control Support Support Long Packet Mode and Short Packet Mode PAD generation Media Independent Interface (MII) • • • • • • • • • Media independence. Multi-vendor point of interoperability. Support connection of MAC layer and Physical (PHY) layer devices. Capable of supporting both 100 Mb/s and 10 Mb/s data rates. Data and delimiters are synchronous to clock references. Provides independent four bit wide transmit and receive data paths. Support connection of PHY layer and Station Management (STA) devices. Provides a simple management interface. Capable of driving a limited length of shielded cable. Data Sheet 40 V0.3, 2003-09 TC1130 On-Chip Memories The TC1130 provides the following on-chip memories: • Program Memory Interface (PMI) with – 32 KBytes Scratch-pad Code RAM (SRAM) – 16 KBytes Instruction Cache Memory (I-CACHE) • Data Memory Interface (DMI) with – 28 KBytes Scratch-pad Data RAM (SRAM) – 4 KBytes Data Cache Memory (D-CACHE) • Data Memory Unit (DMU) with – 64 KBytes SRAM • 16 KBytes Boot ROM (BROM) Data Sheet 41 V0.3, 2003-09 TC1130 Address Map Table 2 defines the specific segment oriented address blocks of the TC1130 with its address range, size, and PMI/DMI access view. Table 3 shows the block address map of the Segment 15 which includes on-chip peripheral units and ports. Table 2 TC1130 Block Address Map Seg- Address ment Range 0 – 7 0000 0000H – 7FFF FFFFH 8 8000 0000H – 8FFF FFFFH 9 9000 0000H – 9FDF FFFFH 10 Size Description DMI Acc. PMI Acc. 2 GB MMU Space via FPI via FPI 256 MB External Memory Space mapped from Segment 10 via LMB via LMB 256 MB Reserved via FPI via FPI via LMB via LMB A000 0000H – 252 MB External Memory Space AFBF FFFFH AFC0 0000H – 64 KB DMU Space AFC0 FFFFH AFC1 0000H – ~4 MB AFFF FFFFH 11 12 Reserved B000 0000H – BFFF FFFFH 256 MB Reserved via FPI via FPI C000 0000H – C000 FFFFH C001 0000H – CFFF FFFFH 64 KB DMU via LMB via LMB ~ 256 MB Reserved Data Sheet 42 c a c h e d n o nc a c h e d c a c h e d V0.3, 2003-09 TC1130 TC1130 Block Address Map(cont’d) Seg- Address ment Range 13 Size Description DMI Acc. PMI Acc. D000 0000H – D000 7FFFH 32 KB DMI Local Data RAM (LDRAM) DMI local via LMB D000 8000H – D3FF FFFFH D400 0000H – D400 7FFFH D400 8000H – D7FF FFFFH D800 0000H – DDFF FFFFH DE00 0000H – DEFF FFFFH ~ 64 MB Reserved DF00 0000H – DFFF BFFFH ~16 MB Reserved 32 KB PMI Local Code Scratchpad RAM (SPRAM) 96 MB 16 MB E800 0000H – E83F FFFFH 4 MB E840 0000H – E84F FFFFH 1 MB E850 0000H – E85F FFFFH E860 0000H – EFFF FFFFH Data Sheet PMI local via LMB via LMB – – via FPI via FPI ~64 MB Reserved External Memory Space Emulator Memory Space DFFF C000H – 16 KB Boot ROM Space DFFF FFFFH E000 0000H – 128 MB External Memory Space E7FF FFFFH 14 via LMB via LMB Reserved for mapped space for – lower 4 MByte of Local Memory in segment 12 (Transformed by LFI bridge to C000 0000H – C03F FFFFH) Reserved for mapped space for lower 1 MByte of Local Memory in segment 13 (Transformed by LFI bridge to D000 0000H – D00F FFFFH) 1 MB Reserved for mapped space for 1 MByte of Local Memory in segment 13 (Transformed by LFI bridge to D400 0000H – D40F FFFFH) 122 MB Reserved 43 via LMB – acces s only from FPI bus side of LFI access only from FPI bus side of LFI – – non-cached Table 2 V0.3, 2003-09 TC1130 TC1130 Block Address Map(cont’d) Seg- Address ment Range 15 Size Description F000 0000H – F00F FFFFH 1 MB On-Chip System Peripherals & via Ports FPI F010 0000H – F027 FFFFH F028 0000H – F200 00FFH F200 0100H – F200 05FFH F200 0600H – F7E0 FEFFH 1.5 MB Peripherals on SMIF Interface of DMA Controller ~29.5 MB Reserved – – 1280 Bytes Ethernet Controller Registers via FPI – via FPI F7E0 FF00H – F7E0 FFFFH 256 Bytes CPU Slave Interface Registers via (CPS) LMB F7E1 0000H – F7E1 FFFFH 64 KB Core SFRs F7E2 0000H – F7FF FFFFH F800 0000H – F87F FFFFH ~1.8 MB Reserved F880 0000H – FFFF FFFFH 120 MB Reserved Table 3 ~94 MB Reserved 8 MB DMI Acc. – LMB Peripheral Space (EBU via and local memory DMU control LMB registers) – PMI Acc. via FPI – via LMB non-cached Table 2 – via LMB – Block Address Map of Segment 15 Symbol Description Address Range Size System Peripheral Bus (SPB) SCU System Control Unit (incl. WDT) F000 0000H - F000 00FFH 256 Bytes SBCU FPI Bus Control Unit F000 0100H - F000 01FFH 256 Bytes STM System Timer F000 0200H - F000 02FFH 256 Bytes OCDS On-Chip Debug Support (Cerberus) F000 0300H - F000 03FFH 256 Bytes – Reserved F000 0400H - F000 04FFH 256 Bytes – Reserved F000 0500H - F000 05FFH 256 Bytes Data Sheet 44 V0.3, 2003-09 TC1130 Table 3 Block Address Map of Segment 15(cont’d) Symbol Description Address Range GPTU General Purpose Timer Unit F000 0600H - F000 06FFH 256 Bytes – Reserved F000 0700H - F000 07FFH 256 Bytes – Reserved F000 0800H - F000 08FFH 256 Bytes – Reserved F000 0900H - F000 09FFH 256 Bytes – Reserved F000 0A00H - F0000AFFH 256 Bytes – Reserved F000 0B00H - F0000BFFH 256 Bytes P0 Port 0 F000 0C00H -F0000CFFH 256 Bytes P1 Port 1 F000 0D00H -F0000DFFH 256 Bytes P2 Port 2 F000 0E00H -F000 0EFFH 256 Bytes P3 Port 3 F000 0F00H - F000 0FFFH 256 Bytes P4 Port 4 F000 1000H - F000 10FFH 256 Bytes – Reserved F000 1100H - F000 11FFH 256 Bytes – Reserved F000 1200H - F000 12FFH 256 Bytes – Reserved F000 1300H - F000 13FFH 256 Bytes – Reserved F000 1400H - F000 14FFH 256 Bytes – Reserved F000 1500H - F000 15FFH 256 Bytes – Reserved F000 1600H - F000 16FFH 256 Bytes – Reserved F000 1700H - F000 17FFH 256 Bytes – Reserved F000 1800H - F000 18FFH 256 Bytes – Reserved F000 1900H - F000 19FFH 256 Bytes CCU60 Capture/Compare Unit 0 F000 2000H - F000 20FFH 256 Bytes CCU61 Capture/Compare Unit 1 F000 2100H - F000 21FFH 256 Bytes – Reserved F000 2200H - F000 3BFFH – DMA Direct Memory Access Controller F000 3C00H - F0003EFFH 3 × 256 Bytes – Reserved F000 3F00H - F000 3FFFH – CAN MultiCAN Controller F000 4000H - F000 5FFFH 8 KBytes – Reserved F000 6000H - F00E1FFFH USB USB RAM based Registers F00E 2000H - F00E 219FH 416 Bytes USB USB RAM F00E 21A0H - F00E 27FFH 1.6 KBytes USB USB Registers F00E 2800H - F00E 28FFH 256 Bytes Data Sheet 45 Size – V0.3, 2003-09 TC1130 Table 3 Block Address Map of Segment 15(cont’d) Symbol Description Address Range – F00E 2900H - F00F FFFFH – Reserved Size Units on SMIF Interface of DMA Controller – Reserved F010 0000H - F010 00FFH 256 Byte SSC0 Synchronous Serial Interface 0 F010 0100H - F010 01FFH 256 Byte SSC1 Synchronous Serial Interface 1 F010 0200H - F010 02FFH 256 Byte ASC0 Async./Sync. Serial Interface 0 F010 0300H - F010 03FFH 256 Byte ASC1 Async./Sync. Serial Interface 1 F010 0400H - F010 04FFH 256 Byte ASC2 Async./Sync. Serial Interface 2 F010 0500H - F010 05FFH 256 Byte I2C Inter IC F010 0600H - F010 06FFH 256 Byte – Reserved F010 0700H - F010BFFFH – MLI0 Multi Link Interface 0 F010 C000H -F010C0FFH 256 Bytes MLI1 Multi Link Interface 1 F010 C100H -F010C1FFH 256 Bytes MCHK Memory Checker F010 C200H -F010C2FFH 256 Bytes – Reserved F010 C300H-F01D FFFFH – MLI0_ SP0 MLI0 Small Transfer Window 0 F01E 0000H- F01E 1FFFH 8 KBytes MLI0_ SP1 MLI0 Small Transfer Window 1 F01E 2000H- F01E 3FFFH 8 KBytes MLI0_ SP2 MLI0 Small Transfer Window 2 F01E 4000H- F01E 5FFFH 8 KBytes MLI0_ SP3 MLI0 Small Transfer Window 3 F01E 6000H- F01E 7FFFH 8 KBytes MLI1_ SP0 MLI1 Small Transfer Window 0 F01E 8000H- F01E 9FFFH 8 KBytes MLI1_ SP1 MLI1 Small Transfer Window 1 F01E A000H- F01E BFFFH 8 KBytes MLI1_ SP2 MLI1 Small Transfer Window 2 F01E C000H- F01E DFFFH 8 KBytes MLI1_ SP3 MLI1 Small Transfer Window 3 F01E E000H- F01E FFFFH 8 KBytes – Reserved F01F 0000H- F01F FFFFH – MLI0_ LP0 MLI0 Large Transfer Window 0 F020 0000H - F020 FFFFH 64 K Bytes Data Sheet 46 V0.3, 2003-09 TC1130 Table 3 Block Address Map of Segment 15(cont’d) Symbol Description Address Range Size MLI0_ LP1 MLI0 Large Transfer Window 1 F021 0000H - F021 FFFFH 64 K Bytes MLI0_ LP2 MLI0 Large Transfer Window 2 F022 0000H - F022 FFFFH 64 K Bytes MLI0_ LP3 MLI0 Large Transfer Window 3 F023 0000H - F023 FFFFH 64 K Bytes MLI1_ LP0 MLI1 Large Transfer Window 0 F024 0000H - F024 FFFFH 64 K Bytes MLI1_ LP1 MLI1 Large Transfer Window 1 F025 0000H - F025 FFFFH 64 K Bytes MLI1_ LP2 MLI1 Large Transfer Window 2 F026 0000H - F026 FFFFH 64 K Bytes MLI1_ LP3 MLI1 Large Transfer Window 3 F027 0000H - F027 FFFFH 64 K Bytes – Reserved F028 0000H - F200 00FFH – ECU Ethernet Controller Unit F200 0100H - F200 05FFH 1280Bytes – Reserved F200 0600H - F7E0FEFFH – CPU (Part of System Peripheral Bus) CPU SFRs – CPU Slave Interface F7E0 FF00H -F7E0FFFFH Reserved F7E1 0000H –F7E17FFFH – MMU F7E1 8000H –F7E180FFH 256 Bytes Reserved F7E1 8100H -F7E1BFFFH – Memory Protection Registers F7E1 C000H-F7E1EFFFH 12K Bytes Reserved F7E1 F000H- F7E1FCFFH – Core Debug Register (OCDS) F7E1 FD00H-F7E1FDFFH 256 Bytes Core Special Function Registers (CSFRs) F7E1 FE00H-F7E1FEFFH 256 Bytes General Purpose Register (GPRs) F7E1 FF00H-F7E1 FFFFH 256 Bytes Reserved – F7E2 0000H -F7FFFFFFH 256 Bytes Local Memory Buses (LMB) EBU Data Sheet External Bus Interface Unit F800 0000H - F800 03FFH 1KBytes 47 V0.3, 2003-09 TC1130 Table 3 Block Address Map of Segment 15(cont’d) Symbol Description Address Range Size DMU Data Memory Unit F800 0400H - F800 04FFH 256 Bytes - Reserved F800 0500H -F87F FBFFH – DMI Data Memory Interface Unit F87F FC00H-F87FFCFFH 256 Bytes PMI Program Memory Interface Unit F87F FD00H-F87FFDFFH 256 Bytes LBCU Local Memory Bus Control Unit F87F FE00H - F87F FEFFH 256 Bytes LFI LMB to FPI Bus Bridge F87F FF00H - F87F FFFFH 256 Bytes – Reserved F880 0000H - FFFF FFFFH – Memory Protection System The TC1130 memory protection system specifies the addressable range and read/write permissions of memory segments available to the currently executing task. The memory protection system controls the position and range of addressable segments in memory. It also controls the kinds of read and write operations allowed within addressable memory segments. Any illegal memory access is detected by the memory protection hardware, which then invokes the appropriate Trap Service Routine (TSR) to handle the error. Thus, the memory protection system protects critical system functions against both software and hardware errors. The memory protection hardware can also generate signals to the Debug Unit to facilitate tracing illegal memory accesses. In TC1130, TriCore supports two address spaces: The virtual address space and The physical address space. Both address space are 4GB in size and divided into 16 segments with each segment being 256MB. The upper 4 bits of the 32-bit address are used to identify the segment. Virtual segments are numbered 0 - 15. But a virtual address is always translated into a physical address before accessing memory. The virtual address is translated into a physical address using one of two translation mechanisms: (a) direct translation, and (b) Page Table Entry (PTE) based translation. If the virtual address belongs to the upper half of the virtual address space then the virtual address is directly used as the physical address (direct translation). If the virtual address belongs to the lower half of the address space, then the virtual address is used directly as the physical address if the processor is operating in Physical mode (direct translation) or translated using a Page Table Entry if the processor is operating in Virtual mode (PTE translation). These are managed by Memory Management Unit (MMU) Memory protection is enforced using separate mechanisms for the two translation paths. Protection for direct translation Memory protection for addresses that undergo direct translation is enforced using the range based protection that has been used in the previous generation of the TriCore architecture. The range based protection mechanism provides support for protecting Data Sheet 48 V0.3, 2003-09 TC1130 memory ranges from unauthorized read, write, or instruction fetch accesses. The TriCore architecture provides up to four protection register sets with the PSW.PRS field controlling the selection of the protection register set. Because the TC1130 uses a Harvard-style memory architecture, each Memory Protection Register Set is broken down into a Data Protection Register Set and a Code Protection Register Set. Each Data Protection Register Set can specify up to four address ranges to receive particular protection modes. Each Code Protection Register Set can specify up to two address ranges to receive particular protection modes. Each of the Data Protection Register Sets and Code Protection Register Sets determines the range and protection modes for a separate memory area. Each contains register pairs which determine the address range (the Data Segment Protection Registers and Code Segment Protection Registers) and one register (Data Protection Mode Register) which determines the memory access modes which apply to the specified range. Protection for PTE based translation Memory protection for addresses that undergo PTE based translation is enforced using the PTE used for the address translation. The PTE provides support for protecting a process from unauthorized read, write, or instruction fetches by other processes. The PTE has the following bits that are provided for the purpose of protection: l XE (Execute Enable) enables instruction fetch to the page. l WE (Write Enable) enables data writes to the page. l RE (Read Enable) enables data reads from the page. Furthermore, User-0 accesses to virtual addresses in the upper half of the virtual address space are disallowed when operating in Virtual mode. In Physical mode, User0 accesses are disallowed only to segments 14 and 15. Any User-0 access to a virtual address that is restricted to User-1 or Super-visor mode will cause a Virtual Address Protection (VAP) Trap in both the Physical and Virtual modes. Memory Checker The Memory Checker Module (MCHK) allows to check the data consistency of memories. It uses DMA moves to read from the selected address area and to write the value read in a memory checker input register (the moves should be 32 bit moves). A polynomial checksum calculation is done with each write operation to the memory checker input register Data Sheet 49 V0.3, 2003-09 TC1130 On-Chip Bus System The TC1130 includes two bus systems: – Local Memory Bus (LMB) – On-Chip FPI Bus (FPI) The LMB-to-FPI (LFI) bridge interconnects the FPI bus and LMB Bus. Local Memory Bus (LMB) The Local Memory Bus interconnects the memory units and functional units, such as CPU and DMU. The main target of the LMB bus is to support devices with fast response times, optimized for speed. This allows the DMI and PMI fast access to local memory and reduces load on the FPI bus. The Tricore system itself is located on LMB bus. Via External Bus Unit, it interconnects TC1130 and external components. The Local Memory Bus is a synchronous, pipelined, split bus with variable block size transfer support. It supports 8, 16, 32 & 64 bits single beat transactions and variable length 64 bits block transfers. Key Features The LMB provides the following features: • • • • • • • • • Synchronous, Pipelined, Multi-master, 64-bit high performance bus Optimized for high speed and high performance 32 bit address, 64 bit data busses Support Split transactions Support Variable block size transfer Burst Mode Read/Write to Memories Connect Caches and on-chip memory and FPI Bus Slave controlled wait state insertion Support Locked transaction (read-modify-write) Data Sheet 50 V0.3, 2003-09 TC1130 On-Chip FPI Bus The FPI Bus interconnects the functional units of the TC1130, such as the DMA and onchip peripheral components. The FPI Bus is designed to be quick to acquire by on-chip functional units, and quick to transfer data. The low setup overhead of the FPI Bus access protocol guarantees fast FPI Bus acquisition, which is required for time-critical applications.The FPI Bus is designed to sustain high transfer rates. For example, a peak transfer rate of up to 800 MBytes/s can be achieved with a 100 MHz bus clock and 32bit data bus. Multiple data transfers per bus arbitration cycle allow the FPI Bus to operate at close to its peak bandwidth. Features • • • • • • • • Supports multiple bus masters Supports demultiplexed address/data operation Address bus up to 32 bits and data buses are 64 bits wide Data transfer types include 8-, 16-, 32- and 64 bit sizes Supports Burst transfer Single- and multiple-data transfers per bus acquisition cycle Designed to minimize EMI and power consumption Controlled by an Bus Control Unit (BCU) – Arbitration of FPI Bus master requests – Handling of bus error. LFI The LMB-to-FPI Interface (LFI) block provides the circuitry to interface (bridge) the FPI bus to the Local Memory Bus (LMB). LFI Features • • • • • • • • Compatible with the FPI 3.2 and LMB bus Specification V2.4 Supports Burst/Single transactions, from FPI to LMB. Supports Burst/Single transactions, from LMB to FPI High efficiency and performance: – fastest access across the bridge takes three cycles, using a bypass. – There are no dead cycles on arbitration. Acts as the default master on FPI side. Supports abort, error and retry conditions on both sides of the bridge. Supports FPI’s clock the same, or half, as the LMB’s clock frequency. LMB clock is shut when no transactions are issue to LFI from both buses and none are in process in the LFI to minimize the power consumption. Data Sheet 51 V0.3, 2003-09 TC1130 LMB External Bus Unit The LMB External Bus Control Unit (EBU) of the TC1130 is the interface between external resources, like memories and peripheral units, and the internal resources connected to on-chip buses if enabled. The basic structure and external interconnections of the EBU are shown in Figure 14. 32 4 24 AD[31:0] BC[3:0] A[23:0] RD PMI RD/WR ALE 4 TriCore CS[3:0] LMB MMU CSCOMB ADV BAA DMI WAIT LFI MR/W EBU_LMB BFCLKI BFCLKO FPI CKE CAS To Peripherals RAS SDCLKI SDCLKO P0.4/BREQ Port 0 Control P0.5/HOLD P0.6/HLDA Port 2 Control P2.0/CSEMU Port 1 Control P1.15/RMW MCB04941_mod Figure 14 Data Sheet EBU Structure and Interfaces 52 V0.3, 2003-09 TC1130 The EBU is mainly used for the operation that masters on LMB bus access external memories through EBU. The EBU controls all transactions required for this operations and in particular handles the arbitration of the external bus between multi-masters. The types of external resources accessed by the EBU are: • • • • • • INTEL style peripherals (separate RD and WR signals) ROMs, EPROMs Static RAMs PC 100 SDRAMs (Burst Read/Write Capacity / Multi-Bank/Page support) Specific types of Burst Mode Flashes (Intel 28F800F3/28F160F3, AMD 29BL162) Special support for external emulator/debug hardware Features • • • • • • • • • • • • • Support Local Memory Bus (LMB 64-bit) Support External bus frequency: LMB frequency =1:1 or 1:2 Highly programmable access parameters Support Intel-style peripherals/devices Support PC 100 SDRAM (burst access, multibanking, precharge, refresh) Support 16-and 32-bit SDRAM data bus and 64,128 and 256MBit devices Support Burst flash (Intel 28F800F3/160F3,AMD 29BL162) Support Multiplexed access (address &data on the same bus) when PC 100 SDRAM is not implemented Support Data Buffering: Code Prefetch Buffer, Read/Write Buffer. External master arbitration compatible to C166 and other Tricore devices 4 programmable address regions (1 dedicated for emulator) Support Little-endian Signal for controlling data flow of slow-memory buffer Data Sheet 53 V0.3, 2003-09 TC1130 Direct Memory Access (DMA) The Direct Memory Access Controller executes DMA transactions from a source address location to a destination address location, without intervention of the CPU. One DMA transaction is controlled by one DMA channel. Each DMA channel has assigned its own channel register set. The total of 8 channels are provided by one DMA sub-block. The DMA module is connected to 3 bus interfaces in TC1130, the Flexible Peripheral Interconnect Bus (FPI), the DMA Bus and the Micro Link Bus. It can do transfers on each of the buses as well as between the buses. In addition it bridges accesses from the Flexible Peripheral Interconnect Bus to the peripherals on the DMA Bus, allowing easy access to these peripherals by CPU. Clock control, address decoding, DMA request wiring, and DMA interrupt service request control are implementation specific and managed outside the DMA controller kernel. Features • 8 independent DMA channels – Up to 8 selectable request inputs per DMA channel – Programmable priority of DMA channels within a DMA sub-block (2 levels) – Software and hardware DMA request generation – Hardware requests by selected peripherals and external inputs • Programmable priority of the DMA sub-block on the bus interfaces • Buffer capability for move actions on the buses (min. 1 move per bus is buffered). • Individually programmable operation modes for each DMA channel – Single mode: stops and disables DMA channel after a predefined number of DMA transfers – Continuous mode: DMA channel remains enabled after a predefined number of DMA transfers; DMA transaction can be repeated. – Programmable address modification • Full 32-bit addressing capability of each DMA channel – 4 GByte address range – Support of circular buffer addressing mode • Programmable data width of a DMA transaction: 8-bit, 16-bit, or 32-bit • Micro Link supported • Register set for each DMA channel – Source and destination address register – Channel control and status register – Transfer count register • Flexible interrupt generation (the service request node logic for the MLI channels is also implemented in the DMA module) • All buses/interfaces connected to the DMA module must work at the same frequency. • Read/write requests of the System Bus Side to the Remote Peripherals are bridged to the DMA Bus (only the DMA is master on the DMA bus) Data Sheet 54 V0.3, 2003-09 TC1130 The basic structure and external interconnections of the DMA are shown in Figure 15 DMA Controller f DMA Clock Control Bus Interface 0 M/S Arbiter/ Switch Control Address Decoder To FPI Bus 4 MultiCAN ASC0 DMA Sub-Block 0 2 ASC0 ASC1 2 ASC2 8 2 SSC1 1 CCU60 CCU61 1 DMA Request Wiring Matrix 4 8 MLI0 Request Assignment and Priorisation Unit 0 Bus Interface 1 M/S ASC2 SSC0 SSC1 IIC Transaction Control Engine 4 Bus Interface 2 SMIF MLI1 1 I2C DMA Bus 2 SSC0 Channel 00-07 Registers Switch ASC1 DMA Bus 2 MLI0 MLI1 Mem Check 1 USB SCU (Ext.Trg) Interrupt Control 4 4 SR [15:12] DMA Interrupt Control Unit SR [3:0] TC1130_DMAImplementation Figure 15 Data Sheet DMA Controller Structure and Interconnections 55 V0.3, 2003-09 TC1130 System Timer The STM within the TC1130 is designed for global system timing applications requiring both high precision and long range. The STM provides the following features: • • • • • • • Free-running 56-bit counter All 56 bits can be read synchronously Different 32-bit portions of the 56-bit counter can be read synchronously Flexible interrupt generation on partial STM content compare match Driven by clock fSTM after reset (default after reset is fSTM = fSYS = 150 MHz) Counting starts automatically after a reset operation STM is reset under following reset causes: – Wake-up reset (PMG_CON.DSRW must be set) – Software reset (RST_REQ.RRSTM must be set) – Power-on reset • STM (and clock divider) is not reset at watchdog reset and hardware reset (HDRST = 0) The STM is an upward counter, running with the system clock frequency fSYS (after reset fSTM = fSYS). It is enabled per default after reset, and immediately starts counting up. Other than via reset, it is no possible to affect the contents of the timer during normal operation of the application, it can only be read, but not written to. Depending on the implementation of the clock control of the STM, the timer can optionally be disabled or suspended for power-saving and debugging purposes via a clock control register The maximum clock period is 256/fSTM. At fSTM = 150 MHz (maximum), for example, the STM counts 15.2 years before overflowing. Thus, it is capable of continuously timing the entire expected product life-time of a system without overflowing. Data Sheet 56 V0.3, 2003-09 TC1130 S TM M odule 31 23 15 0 7 C o m p a re R e g is te r C M P 0 31 23 15 7 0 C o m p a re R e g is te r C M P 1 S T M IR 1 In te rru p t C o n tro l C lo c k C o n tro l 55 47 39 31 23 15 7 0 5 6 -B it S y s te m T im e r S T M IR 0 E n a b le / D is a b le 00H CAP fSTM 00H T IM 6 T IM 5 A d d re s s D ecoder T IM 4 T IM 3 PORST T IM 2 T IM 1 T IM 0 M C A04795_m od Figure 16 Data Sheet Block Diagram of the STM Module 57 V0.3, 2003-09 TC1130 Watchdog Timer The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and recover from software or hardware failure. The WDT helps to abort an accidental malfunction of the TC1130 in a user-specified time period. When enabled, the WDT will cause the TC1130 system to be reset if the WDT is not serviced within a userprogrammable time period. The CPU must service the WDT within this time interval to prevent the WDT from causing a TC1130 system reset. Hence, routine service of the WDT confirms that the system is functioning properly. In addition to this standard “Watchdog” function, the WDT incorporates the EndInit feature and monitors its modifications. A system-wide line is connected to the ENDINIT bit implemented in a WDT control register, serving as an additional write-protection for critical registers (besides Supervisor Mode protection). Registers protected via this line can only be modified when Supervisor Mode is active and bit ENDINIT = 0. A further enhancement in the TC1130’s Watchdog Timer is its reset prewarning operation. Instead of immediately resetting the device on the detection of an error, as known from standard Watchdogs, the WDT first issues an Non-maskable Interrupt (NMI) to the CPU before finally resetting the device at a specified time period later. This gives the CPU a chance to save system state to memory for later examination of the cause of the malfunction, an important aid in debugging. Features • 16-bit Watchdog counter • Selectable input frequency: fSYS/256 or fSYS/16384 • 16-bit user-definable reload value for normal Watchdog operation, fixed reload value for Time-Out and Prewarning Modes • Incorporation of the ENDINIT bit and monitoring of its modifications • Sophisticated password access mechanism with fixed and user-definable password fields • Proper access always requires two write accesses. The time between the two accesses is monitored by the WDT and limited. • Access Error Detection: Invalid password (during first access) or invalid guard bits (during second access) trigger the Watchdog reset generation. • Overflow Error Detection: An overflow of the counter triggers the Watchdog reset generation. • Watchdog function can be disabled; access protection and ENDINIT monitor function remain enabled. • Double Reset Detection: If a Watchdog induced reset occurs twice without a proper access to its control register in between, a severe system malfunction is assumed and the TC1130 is held in reset until a power-on reset. This prevents the device from being periodically reset if, for instance, connection to the external memory has been lost such that even system initialization could not be performed. Data Sheet 58 V0.3, 2003-09 TC1130 • Important debugging support is provided through the reset prewarning operation by first issuing an NMI to the CPU before finally resetting the device after a certain period of time. System Control Unit The System Control Unit (SCU) of the TC1130 handles the system control tasks. All these system functions are tightly coupled, thus, they are conveniently handled by one unit, the SCU. The system tasks of the SCU are: • PLL Control – PLL_CLC Clock Control Register • Reset Control – Generation of all internal reset signals – Generation of external HDRST reset signal • Boot Scheme – Hardware Booting Scheme – Software Booting Scheme • Power Management Control – Enabling of several power-down modes – Control of the PLL in power-down modes • Watchdog Timer • OCDS2 Trace Port Control • Device Identification Registers Data Sheet 59 V0.3, 2003-09 TC1130 Interrupt System An interrupt request can be serviced by the CPU which is called “Service Provider”. Interrupt requests are referred as “Service Requests” in this document. Each peripheral in the TC1130 can generate service requests. Additionally, the Bus Control Unit, the Debug Unit, the DMA Controller and even the CPU itself can generate service requests to the Service Provider. As shown in Figure 17, each unit that can generate service requests is connected to one or multiple Service Request Nodes (SRN). Each SRN contains a Service Request Control Register mod_SRCx, where “mod” is the identifier of the service requesting unit and “x” an optional index. The SRNs are connected to the Interrupt Control Unit (ICU) via the CPU Interrupt Arbitration Bus. The ICU arbitrates service requests for the CPU and administers the Interrupt Arbitration Bus. Units which can generate service requests are: – Asynchronous/Synchronous Serial Interfaces (ASC0 & ASC1 & ASC2) with 4 SRNs each – High-Speed Synchronous Serial Interfaces (SSC0 & SSC1) with 3 SRNs each – Inter IC Interface (IIC) with 3 SRNs – Universal Serial Bus (USB) with 8 SRNs – Micro Link Interface MLI0 with 4 SRNs and MLI1 with 2 SRNs – General Purpose Timer Unit (GPTU) with 8 SRNs – Capture/Compare Unit (CCU60 & CCU61) with 4 SRNs each – MultiCAN (CAN) with 16 SRNs – Ethernet Controller with 9 SRNs – External Interrupts with 4 SRNs – Direct Memory Access Controller (DMA) with 4 SRNs – DMA Bus with 1 SRN – System Timer (STM) with 2 SRNs – Bus Control Units (SBCU and LBCU) with 1 SRN each – Peripheral Control Processor (PCP) with 12 SRNs – Central Processing Unit (CPU) with 4 SRNs – Floating Point Unit (FPU) with 1 SRN – Debug Unit (OCDS) with 1 SRN The CPU can make service requests directly to itself (via the ICU). The CPU Service Request Nodes are activated through software. Data Sheet 60 V0.3, 2003-09 TC1130 CPU Interrupt Arbitration Bus Service Requestors ASC0 ASC1 ASC2 SSC0 SSC1 MLI0 MLI1 MultiCAN Service Req. Nodes 4 4 4 3 3 4 2 16 4 SRNs 4 SRNs 4 SRNs 3 SRNs 3 SRNs 4 SRNs 2 SRNs 16 SRNs Interrupt Service Providers 4 Service Req. Nodes 4 4 USB GPTU ETHERNET STM FPU OCDS DMA BUS 8 9 2 1 1 1 8 SRNs 8 SRNs 9 SRNs 2 SRNs 1 SRN 1 SRN 1 SRN Software Interrupts 4 CPU CPU Interrupt Control Unit 3 ICU Int. Req. PIPN 3 4 Int. Ack. CCPN 2 Service Req. Nodes 16 4 8 4 4 SRNs 8 3 4 SRN 3 SRNs Service Requestors 4 3 Ext. Int. IIC 8 4 9 2 1 1 4 1 1 4 4 SRNs 4 SRNs 1 SRN 1 SRN 4 SRNs 4 4 1 1 4 CCU60 CCU61 LBCU SBCU DMA 1 Interrupt System Figure 17 Data Sheet Block Diagram of the TC1130 Interrupt System 61 V0.3, 2003-09 TC1130 Boot Options The TC1130 booting schemes provides a number of different boot options for the start of code execution. Table 4 shows the boot options available in the TC1130. Table 4 Boot Selections BRKIN1) TM1) HWCFG Type of Boot [2:0] PC Start Value (User Entry) 1 1 0 1 0 0 000 Bootstrap Loader. Serial boot from ASC to PMI scratchpad, run loaded program DFFF FFFCH2) (D400 0000H) 001 Bootstrap Loader. Serial boot from CAN to PMI scratchpad, run loaded program DFFF FFFCH2) (D400 0000H) 010 Bootstrap Loader. Serial boot from SSC to PMI scratchpad, run loaded program DFFF FFFCH2) (D400 0000H) 011 External memory, EBU as master DFFF FFFCH2) (A000 0000H) 100 External memory, EBU as slave DFFF FFFCH2) (A000 0000H) 101 Reserved ---- 110 PMI scratchpad D400 0000H 111 Reserved (STOP) ---- 000 Tristate chip ---- 001 Go to external emulator space DFFFFFFCH2) (DE00 0000H) 010-111 Reserved (STOP) ---- 000-111 Reserved (STOP) ---- 1) This input signal is active low. 2) This is the BootROM entry address; The start address of user program in parentheses Data Sheet 62 V0.3, 2003-09 TC1130 Power Management System The TC1130 power management system allows software to configure the various processing units so that they automatically adjust to draw the minimum necessary power for the application. There are three power management modes: • Run Mode • Idle Mode • Deep Sleep Mode Table 5 describes these features of the power management modes. Table 5 Power Management Mode Summary Mode Description Run The system is fully operational. All clocks and peripherals are enabled, as determined by software. Idle The CPU clock is disabled, waiting for a condition to return it to Run Mode. Idle Mode can be entered by software when the processor has no active tasks to perform. All peripherals remain powered and clocked. Processor memory is accessible to peripherals. A reset, Watchdog Timer event, a falling edge on the NMI pin, or any enabled interrupt event will return the system to Run Mode. Deep Sleep The system clock is shut off; only an external signal will restart the system. Entering this state requires an orderly shut-down controlled by the Power Management State Machine (PMSM). Besides these explicit software-controlled power-saving modes, TC1130 supports automatic power-saving in that operating units, which are currently not required or idle, are shut off automatically until their operation is required again. Data Sheet 63 V0.3, 2003-09 TC1130 On-Chip Debug Support The On-Chip Debug Support of the TC1130 consists of the following building blocks: • • • • • • • • • OCDS L1 module of TriCore OCDS L2 interface of TriCore OCDS L1 module in the BCU of the FPI Bus OCDS L1 facilities within the DMA OCDS L2 interface of DMA OCDS System Control Unit (OSCU) Multi Core Break Switch (MCBS) JTAG based Debug Interface (Cerberus JDI) Suspend functionality of peripherals Features • TriCore L1 OCDS: – Hardware event generation unit – Break by DEBUG instruction or break signal – Full Single-Step support in hardware, possible also with software break – Access to memory, SFRs, etc. on the fly • DMA L1 OCDS: – Output break request on errors – Suspending of pre-selected channels • Level 2 trace port with 16 pins that outputs either TriCore, or DMA trace • OCDS System Control Unit (Cerberus OSCU) – Minimum number of pins required (no OCDS enable pin) – Hardware allows hot attach of a debugger to a running system – System is secure (can be locked from internal) • Multi Core Break Switch (Cerberus MCBS): – TriCore, DMA, break pins, and BCUs as break sources – TriCore as break targets; other parts can in addition be suspended – Synchronous stop and restart of the system – Break to Suspend converter Figure 18 shows a basic block diagram of the building blocks. Data Sheet 64 V0.3, 2003-09 TC1130 . OCDS L1 BCU OCDS L1 TriCore Watchdog timer TMS TCK TRST JTAG Controller Cerberus TDO TDI OSCU JDI Debug I/F DMA FPI BRKIN BRKOUT Periph.n Break and Suspend Signals OCDS2[15:0] OCDS L2 Enable, Control and Reset 16 DMA L2 Multiplexer Periph.1 MCBS Break Switch TC1130 OCDS Block Diagram Figure 18 Data Sheet OCDS Support Basic Block Diagram 65 V0.3, 2003-09 TC1130 Clock Generation Unit The Clock Generation Unit (CGU) allows a very flexible clock generation for TC1130. The power consumption is indirect proportional to the frequency, whereas the performance of the microcontroller is direct proportional to the frequency. During user program execution the frequency can be programmed for an optimal ratio between performance and power consumption. Therefore the power consumption can be adapted to the actual application state. Features The Clock Generation Unit serves different purposes: • PLL Feature for multiplying clock source by different factors • Direct Drive for direct clock put through • Comfortable state machine for secure switching between basic PLL, direct or prescaler operation • Power Down Mode support • USB Clock source and control The Clock Generation Unit in the TC1130, shown in Figure 19, consists of an oscillator circuit and one Phase-Locked Loop (PLL). The PLL can convert a low-frequency external clock signal to a high-speed internal clock for maximum performance. The PLL also has fail-safe logic that detects degenerate external clock behavior such as abnormal frequency deviations or a total loss of the external clock. It can execute emergency actions if it losses the lock on the external clock. In general, the Clock Generation Unit (CGU) is controlled through the System Control Unit (SCU) module of the TC1130. XTAL1 Clock Generation Unit CGU Oscillator Circuit fOSC Osc. Run Detect. XTAL2 1:1/1:2 Divider P Divider >1 Phase Detect. fVCO VCO 1 MUX 0 fSYS MUX fCPU K:1/K:2 Divider Divider f USB MUX N Divider PLL P4.0/ USBCLK Lock Detector OGC MOSC OSCR Register OSC_CON PDIV OSC [2:0] DISC PLL_ LOCK NDIV [6:0] VCO_ SEL[1:0] VCO_ KDIV SYS BYPASS [3:0] FSL Register PLL_CLC PLL_ BYPASS USBC LDIV USBC LSEL Register SCU_CON System Control Unit SCU MCA04940mod Figure 19 Data Sheet Clock Generation Unit Block Diagram 66 V0.3, 2003-09 TC1130 Recommended Oscillator Circuits VDDOSC VDDOSC3 XTAL1 VDDOSC fOSC External Clock Signal TC1130 Oscillator 4 - 40 MHz fOSC XTAL1 TC1130 Oscillator XTAL2 C1 VDDOSC3 XTAL2 C2 Fundamental Mode Crystal VSSOSC VSSOSC osc_Cedar Figure 20 Oscillator Circuitries For the main oscillator of the TC1130, the following external passive components are recommended: – Crystal: 0~40 MHz – C1, C2: 10 pF A block capacitor between VDDOSC3 and VSSOSC, VDDOSC and VSSOSC is recommended, too. Data Sheet 67 V0.3, 2003-09 TC1130 Power Supply The TC1130 provides an ingenious power supply concept in order to improve the EMI behavior as well as to minimize the crosstalk within on-chip modules. Figure 21 shows the TC1130’s power supply concept, where certain logic modules are individually supplied with power. This concept improves the EMI behavior by reduction of the noise cross coupling. V SS (1.5 V) V DD DMU OSC DMI PMI GPIO Ports (P0-P4) VDDOSC3 (3.3V) VDDOSC (1.5V) VSS VSS Figure 21 Data Sheet CPU & Peripheral Logic VDDP (3.3 V) VSS EBU Ports MCB04953mod TC1130 Power Supply Concept 68 V0.3, 2003-09 TC1130 Power Sequencing During Power-Up reset pin PORST has to be held active until both power supply voltages have reached at least their minimum values. During the Power-Up time (rising of the supply voltages from 0 to their regular operating values) it has to be ensured, that the core VDD power supply reaches its operating value first, and then the GPIO VDDP power supply. During the rising time of the core voltage it must be ensured that 0< VDD-VDDP <0.5 V. During power-down, the core and GPIO power supplies VDD and VDDP respectively, have to be switched off completely until all capacitances are discharged to zero, before the next power-up. Note: The state of the pins are undefined when only the port voltage VDDP is switched on. Data Sheet 69 V0.3, 2003-09 TC1130 Identification Register Values Table 6 TC1130 Identification Registers Short Name Address Value SCU_ID F000 0008H 002C C001H MANID F000 0070H 0000 1820H CHIPID F000 0074H 0000 8C01H RTID F000 0078H 0000 0000H SBCU_ID F000 0108H 0000 6A0AH STM_ID F000 0208H 0000 C005H JDP_ID F000 0308H 0000 6307H GPTU_ID F000 0608H 0001 C002H CCU60_ID F000 2008H 0042 C004H CCU61_ID F000 2108H 0042 C004H DMA_ID F000 3C08H 001A C011H CAN_ID F000 4008H 002B C021H USB_ID F00E 2808H 0000 4A00H SSC0_ID F010 0108H 0000 4530H SSC1_ID F010 0208H 0000 4530H ASC0_ID F010 0308H 0000 44E2H ASC1_ID F010 0408H 0000 44E2H ASC2_ID F010 0508H 0000 44E2H IIC_ID F010 0608H 0000 4604H MLI0_ID F010 C008H 0025 C004H MLI1_ID F010 C108H 0025 C004H MCHK_ID F010 C208H 001B C001H CPS_ID F7E0 FF08H 0015 C006H MMU_ID F7E1 8008H 0009 C002H CPU_ID F7E1 FE18H 000A C005H EBU_ID F800 0008H 0014 C004H DMU_ID F800 0408H 002D C001H DMI_ID F87F FC08H 0008 C004H PMI_ID F87F FD08H 000B C004H Data Sheet 70 V0.3, 2003-09 TC1130 Table 6 TC1130 Identification Registers Short Name Address Value LBCU_ID F87F FE08H 000F C005H LFI_ID F87F FF08H 000C C005H Data Sheet 71 V0.3, 2003-09 TC1130 Absolute Maximum Rating Targets Parameter Symbol Limit Values Unit Notes min. max. TA TST TJ VDDC -40 85 °C under bias -65 150 °C – -40 125 °C under bias -0.5 1.7 V – Voltage at 3.3V power supply pins with respect to VSS2) VDDP -0.5 4.0 V – Voltage on any pin with respect to VSS2) VIN -0.5 4.0 V – Input current on any pin during overload condition IIN -10 10 mA 3) Absolute sum of all input currents ΣIIN during overload condition – |100| mA 3) fsys fFPI PD – 150 MHz – – 100 MHz – – tbd W Ambient temperature Storage temperature Junction temperature Voltage at 1.5V power supply pins with respect to VSS1) CPU & LMB Bus Frequency FPI Bus Frequency Power dissipation – 1) Applicable for VDD and VDDOSC. 2) Applicable for VDDP and VDDOSC3. The maximum voltage difference must not exceed 4.0V in any case (i.e. Supply Voltage = 4.0V and Input Voltage = -0.5V is not allowed). 3) Restricted life time: TBD Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (VIN > VDD or VIN < VSS) the voltage on VDD pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings. Data Sheet 72 V0.3, 2003-09 TC1130 Operating Condition The following operating conditions must not be exceeded in order to ensure correct operation of the TC1130. All parameters specified in the following table refer to these operating conditions, unless otherwise noticed. Parameter Digital supply voltage Digital ground voltage Digital core supply current Ambient temperature under bias CPU clock Overload current Short circuit current Symbol min. max. Unit Notes Conditions VDDC VDDP VSS IDD TA 1.43 1.58 V 3.14 3.47 V fSYS IOV ISC Limit Values 0 V 525 mA -40 +85 °C –1) 150 MHz – -1 1 mA -3 3 -1 1 -3 3 |50| – 2)3) duty cycle ≤ 25% mA 4) duty cycle ≤ 25% Absolute sum of overload + short circuit currents Σ|IOV| + |ISC| – Inactive device pin current (VDD = VDDP = 0) IID -1 1 mA External load capacitance CL – 50 pF 2000 – V ESD strength – mA 3) duty cycle ≤ 25% |100| – Human Body Model (HBM) 1) The TC1130 uses a static design, so the minimum operation frequency is 0 MHz. Due to test time restriction no lower frequency boundary is tested, however. 2) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. VOV > VDDP + 0.5 V or VOV < VSS - 0.5 V). The absolute sum of input overload currents on all digital IO pins may not exceed 50 mA. The supply voltage must remain within the specified limits. 3) Not 100% tested, guaranteed by design and characterization. Data Sheet 73 V0.3, 2003-09 TC1130 4) Applicable for digital inputs. Parameter Interpretation The parameters listed on the following pages partly represent the characteristics of the TC1130 and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column “Symbol”: CC (Controller Characteristics): The logic of the TC1130 will provide signals with the respective timing characteristics. SR (System Requirement): The external system must provide signals with the respective timing characteristics to the TC1130. Data Sheet 74 V0.3, 2003-09 TC1130 DC Characteristics DC-Characteristics VSS = 0 V; TA = -40°C to +125°C Parameter Symbol Limit Values min. Unit Test Condition max. GPIO pins, Dedicated pins and EBU pins VIL VIH Input low voltage Input high voltage Output low voltage Output high voltage Pull-up current 1) Pull-down current 2) Input leakage current 3) Pin Capacitance 4) SR -0.3 0.8 V LvTTL SR 2.0 VDDP + 0.3 V LvTTL 0.4 V IOL = 2mA – V IOH = -2mA 149 µA − 7.2 µA – 156 µA – 15.7 µA – ±350 nA VIN = 0V VIN = 0V VIN = VDDP VIN = VDDP 0 < VIN < VDDP – 10 pF 0.1 V 1.5 V VOL CC – VOH CC 2.4 |IPUA| CC − |IPUC| CC |IPDA| CC |IPDC| CC IOZ1 CC CIO CC f = 1 MHz TA = 25 °C Oscillator Pins VILX SR 0 Input high voltage at XTAL1 VIHX SR 1.4 Input low voltage at XTAL1 Notes: 1) The current is applicable to the pins, for which a pull up has been specified. Refer to Table 1. IPUx refers to the pull up current for type x in absolute values. 2) The current is applicable to the pins, for which a pull down has been specified. Refer to Table 1. IPDx refers to the pull down current for type x in absolute values. 3) Excluded following pins : NMI, TRST, TCK, TDI, TMS, MII_TXCLK, MII_RXCLK, MII_MDIO, ALE, P2.1,HWCFG0, HWCFG1, HWCFG2, BRKIN, PORST, HDRST. 4) Not 100% tested, guaranteed by design characterization. Data Sheet 75 V0.3, 2003-09 TC1130 USB Interface Table 7 DC Electrical Characteristics Parameter Symbol Limit Values Unit min. typ. max. 3.14 3.3 3.47 V Supply Voltage Intern VDDE Input Level 1.4 1.5 1.6 V Differential Input Level 0.2 Differential Common Mode Range 0.8 Single Ended Receiver Threshold low < 0.8 Test Conditions Supply Voltage Supply Voltage Extern VDDP V |V(D+) - V(D-)| 2.5 V Range of Sensitivity high > 2.0 V < 0.3 V with 1.5 kΩ to 3.6 V 3.6 V with 15 kΩ to ground 10 µA 0 < Vin < 3.3V Unit Test Conditions 20 ns Capacitive load 50 pF 110 % Capacitive load 50 pF Output Levels Static Output Low Static Output High 2.8 3.3 Leakage Current Hi_Z State Data Line Leakage Table 8 -10 Full Speed Electrical Characteristic Parameter Symbol Limit Values min. typ. max. Driver Characteristics Rise / Fall Time 4 Rise / Fall Time Matching 90 Crossover Voltage of differential Signals 1.3 2.0 V Capacitive load 50 pF Driver Output Impedance 28 44 Ω Steady State Driver Termination Impedance 1.425 1.575 kΩ Data Sheet 100 1.5 76 V0.3, 2003-09 TC1130 VDDP VDDP 1.5kΩ RS D+ 22 Ω USB VDDP Interface RS D22 Ω Figure 22 Data Sheet USB Interface 77 V0.3, 2003-09 TC1130 IIC Pins Each IIC Pin is an open drain output pin with different characteristics than other pins. The related characteristics are given in the following table Parameter Output low voltage Symbol VOL CC Limit values min. max. - 0.4 Unit Test Conditions V 3 mA sink current 6 mA sink current 0.6 Input high voltage1) VIH SR 0.7VDDP VDDP+0.5 V - Input low voltage1) VIL SR -0.5 0.3VDDP V - 1) Guaranteed by design characterization Note: No 5 V IIC interface is supported with these pads. Only voltages lower than 3.63 V must be applied to these pads. Note: IIC pins have no Pull-Up and Pull-Down devices. Data Sheet 78 V0.3, 2003-09 TC1130 Power Supply Current Parameter Active mode supply current Idle mode supply current Deep sleep mode supply current Symbol IDD IID IDS Limit values Unit Test Conditions typ. 1) max. 314 679 mA Sum of IDDS 2) 153 345 mA 156 322 mA 74 154 mA 66 130 mA 6 15 mA 2 19 mA 2 19 mA 3.6 58 µA IDD at VDD 3) IDD at VDDP Sum of IDDS2)4) IDD at VDD3)4) IDD at VDDP4) Sum of IDDS2)5) IDD at VDD3)5) IDD at VDDP5) 1) Typical values are measured at 25°C, CPU clock at xxx MHz and nominal supply voltage, i.e. 3.3V for VDDP, VDDOSC3 and 1.5V for VDD, VDDOSC. These currents are measured using a typical application pattern. The power consumption of modules can increase or decrease using other application programs. 2) These power supply currents are defined as the sum of all currents at the VDD power supply lines: VDD + VDDP + VDDOSC3 + VDDOSC 3) This measurement includes the TriCore and Logic power supply lines. 4) CPU is in idle state, input clock to all peripherals are enabled, 5) Clock generation is disabled at the source. Data Sheet 79 V0.3, 2003-09 TC1130 AC Characteristics Note: The values in Blue color are gotten from STA. Power, Pad and Reset Timing Parameter Symbol Limit Values min. max. xxxx – V 30 ms – ms Min. VDDP voltage to ensure defined pad states VDDPPA Oscillator start-up time1) tOSCS CC – tPOA CC 50 Minimum PORST active time after power supplies are stable at operating levels CC HRST pulse width tHD CC 1024 cycles2) Ports inactive after any reset active3) tPI CC – 1) Not measured, guaranteed by device characterization 2) Any HDRST activation is internally prolonged to 1024 FPI bus clock cycles 3) Not measured, guaranteed by design characterization Data Sheet Unit 80 fSYS 30 ns V0.3, 2003-09 TC1130 V DDPPA V DDPPA VDDP VDD V DDPR to s c s OSC tP O A tP O A PORST th d th d HDRST Pads ta te u n d e fin e d 2) 1) 2) Pads tpi 1 ) a s p ro g ra m m e d 1) 2) Pads ta te u n d e fin e d 2 ) T ri-s ta te , p u ll d e v ic e a c tiv e re s e t_ b e h PLL Parameters Phase Locked Loop (PLL) When PLL operation is configured (PLL_CLC.LOCK = 1) the on-chip phase locked loop is enabled and provides the master clock. The PLL multiplies the input frequency by the factor F (fMC = fOSC × F) which results from the input divider, the multiplication factor (N Factor), and the output divider (F = NDIV+1 / (PDIV+1 × KDIV+1)). The PLL circuit synchronizes the master clock to the input clock. This synchronization is done smoothly, i.e. the master clock frequency does not change abruptly. Due to this adaptation to the input clock the frequency of fMC is constantly adjusted so it is locked to fOSC. The slight variation causes a jitter of fMC which also affects the duration of individual TCMs. The timing listed in the AC Characteristics refers to TCPs. Because fCPU is derived from fMC, the timing must be calculated using the minimum TCP possible under the respective circumstances. The actual minimum value for TCP depends on the jitter of the PLL. As the PLL is constantly adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator) the relative deviation for periods of more than one TCP is lower than for one single TCP (see formula and Figure 23). Data Sheet 81 V0.3, 2003-09 TC1130 This is especially important for bus cycles using waitstates and e.g. for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is negligible. The value of the accumulated PLL jitter depends on the number of consecutive VCO output cycles within the respective timeframe. The VCO output clock is divided by the output prescaler (K = KDIV+1) to generate the master clock signal fMC. Therefore, the number of VCO cycles can be represented as K × N, where N is the number of consecutive fMC cycles (TCM). For a period of N × TCM the accumulated PLL jitter is defined by the corresponding deviation DN: DN [ns] = ±(1.5 + 6.32 × N / fMC); fMC in [MHz], N = number of consecutive TCMs. So, for a period of 3 TCMs @ 20 MHz and K = 12: D3 = ±(1.5 + 6.32 × 3 / 20) = 2.448 ns. This formula is applicable for K × N < 95. For longer periods the K×N=95 value can be used. This steady value can be approximated by: DNmax [ns] = ±(1.5 + 600 / (K × fMC)). A cc. jitte r D N ns K =1 5 K =12 K =10 K =8 K =6 K =5 ±8 ±7 ±6 M Hz ±5 10 ±4 ±3 ±2 z MH 0 2 Hz 40 M ±1 0 1 5 15 10 20 25 N m cb 04413_x c.v sd Figure 23 Approximated Accumulated PLL Jitter Note: The bold lines indicate the minimum accumulated jitter which can be achieved by selecting the maximum possible output prescaler factor K. Data Sheet 82 V0.3, 2003-09 TC1130 Different frequency bands can be selected for the VCO, so the operation of the PLL can be adjusted to a wide range of input and output frequencies: Table 9 VCO Bands for PLL Operation PLL_CLC.VCOSEL VCO Frequency Range Base Frequency Range 1) 00 400 ... 500 MHz 250 ... 320 MHz 01 500 ... 600 MHz 300 ... 400 MHz 10 600 ... 700 MHz 350 ... 480 MHz 11 Reserved 2) 1) Base Frequency Range is the free running operation frequency of the PLL, when no input clock is available. 2) This option can not be used. Data Sheet 83 V0.3, 2003-09 TC1130 AC Characteristics (Operating Conditions apply) 2.4V 2.0V 2.0V test points 0.8V 0.8V 0.4V AC inputs during testing are driven at 2.4V for a logic “1” and 0.4V for a logic “0”. Timing measurements are made at VIHmin for a logic “1” and VILmax for a logic “0”. Figure 24 Data Sheet Input/Output Waveforms for AC Tests - for GPIO, Dedicated and EBU pins 84 V0.3, 2003-09 TC1130 Input Clock Timing (Operating Conditions apply) Parameter Symbol Limits min Oscillator clock frequency with PLL Input clock frequency driving at XTAL1 with PLL max 40 MHz 40 MHz 55 % SR Input Clock Duty Cycle (t1 /t2 ) Input Clock at XTAL1 fOSC SR 4 fOSCDD - Unit SR 45 VIHX 0.5 VDD VILX t1 t2 t OSCDD Figure 25 Data Sheet Input Clock Timing 85 V0.3, 2003-09 TC1130 Port Timing (Operating Conditions apply; CL = 50 pF) Parameter Symbol Limits min Port data valid from TRCLK 1) 1) t1 CC − Unit max 13 ns Port data is output with respect to the FPI clock. The TRCLK is used as a reference here since the FPI clock is not available as an external pin and TRCLK is same frequency as CPU clock. Port lines maintain its state for at least 2 CPU clocks. TRCLK FPI_CLK t1 Figure 26 Data Sheet New State Old State Port Lines Port Timing 86 V0.3, 2003-09 TC1130 Timing for EBU_LMB Clock Outputs SDCLKO Output Clock Timing (Operating Conditions apply; CL = 50 pF) Parameter Symbol Limits Unit min SDCLKO period SDCLKO high time SDCLKO low time SDCLKO rise time SDCLKO fall time SDCLKO duty cycle t2/(t2 + t3) t1 CC t2 CC t3 CC t4 CC t5 CC DC CC max 10 – – ns 4.5 – − ns 3 – − ns − – 2.5 ns − – 2.5 ns 45 50 55 % BFCLKO Output Clock Timing (Operating Conditions apply; CL = 50 pF) Parameter Symbol Limit Values min. Clock period BFCLKO high time BFCLKO low time BFCLKO rise time BFCLKO fall time BFCLKO duty cycle t2/(t2 + t3)1) 1) t1 t2 t3 t4 t5 DC Unit typ. max. CC 20 – – ns CC 9 – – ns CC 9 – – ns CC – – 3.5 ns CC – – 2.5 ns CC 45 50 55 % This duty cycle is not applicable when BFCON.extclock equals to 10 (1/3 of LMBCLK frequency) BFCLKO/ SDCLKO 0.5 V DD t2 t3 t5 t Figure 27 Data Sheet EBU Clock Output Timing 87 V0.3, 2003-09 TC1130 Timing for SDRAM Access Signals (Operating Conditions apply; CL = 50 pF1)) Parameter Symbol Limits min Unit max t1 t2 t3 t4 t5 CC − 8.0 ns CC 1.0 − ns CC − 8.0 ns CC 1.0 − ns CC − 8.0 ns CSx, RAS, CAS, RD/WR, BC(3:0) output hold time from SDCLKO t6 CC 1.0 − ns AD(31:0) output valid time from SDCLKO t7 t8 t9 t10 CC − 8.0 ns CC 1.0 − ns SR 4.0 − ns SR 3.0 − ns CKE output valid time from SDCLKO CKE output hold time from SDCLKO Address output valid time from SDCLKO Address output hold time from SDCLKO CSx, RAS, CAS, RD/WR, BC(3:0) output valid time from SDCLKO AD(31:0) output hold time from SDCLKO AD(31:0) input setup time to SDCLKO AD(31:0) input hold time from SDCLKO 1) If application conditions other than 50 pf capacitive load are used, then the proper correlation factor should be used for your specific application condition. For design team, the load should be set according to the system requirement. Data Sheet 88 V0.3, 2003-09 TC1130 Write Access SDCLKO t1 CKE t2 t3 Address t4 Column ROW t5 CSx t5 t6 t6 RAS t5 t6 CAS t5 t6 RD/WR t5 BC[3:0] t6 t7 t8 D(0) AD[31:0] D(n) Read Access SDCLKO CKE Address t1 t3 t4 t5 CSx RAS Column ROW t5 t6 t6 t5 t6 CAS RD/WR t5 BC[3:0] t6 t10 t9 D(0) AD[31:0] D(n) SDRAM_Timing Figure 28 Data Sheet SDRAM Access Timing 89 V0.3, 2003-09 TC1130 Timing for Burst Flash Access Signals Operating Conditions apply; CL = 50 pF) Parameter Symbol Limits min Unit max CC − 11.0 ns CC 10.0 − ns CC − 9.0 ns CC − 10.0 ns ADV output valid time from BFCLKO t1 t2 t3 t4 t5 CC − 10.0 (7.0) ns ADV output hold time from BFCLKO t6 CC 3.0 (0.0) − ns BAA output valid time from BFCLKO t7 CC − 10.0 (7.0) ns BAA output hold time from BFCLKO t8 t9 t10 t11 t12 CC 3.0 − ns SR 5.0 − ns SR 3.0 − ns SR 5.0 − ns SR 3.0 − ns Address output valid time from BFCLKO Address output hold time from BFCLKO CSx output valid time from BFCLKO RD output valid time from BFCLKO AD(31:0) input setup time to BFCLKO AD(31:0) input hold time from BFCLKO WAIT input setup time to BFCLKO WAIT input hold time from BFCLKO Data Sheet 90 V0.3, 2003-09 TC1130 Address Phase(s) Command Command Burst Delay Phase(s) Phase(s) Phase(s) Burst Phase(s) Recovery New Addr. Phase Phase(s) BFCLKO t2 t1 Address Address CSx t3 ADV t5 RD BAA D[31:0] t6 t4 t8 t7 D(0) t9 t10 D(n-1) t11 t12 WAIT BF_Timing Figure 29 Burst Flash Access Timing Note: Output delays are always referenced to BFCLKO. The reference clock for input characteristics depends on bit BFCON.FDBKEN. BFCON.FDBKEN = 0: BFCLKO is the input reference clock. BFCON.FDBKEN = 1: BFCLKI is the input reference clock (EBULMB clock feedback enabled) Data Sheet 91 V0.3, 2003-09 TC1130 Timing for Demultiplexed Access Signals (Operating Conditions apply; CL = 50 pF) 1) Parameter Symbol Limits min Unit max ALE, CSx, RD/WR, RD, MR/W, BC(3:0) output valid t1 time from output clock CC − 3.2 ns ALE, CSx, RD/WR, RD, MR/W, BC(3:0) output hold t2 time from output clock CC 0.0 − ns CC − 3.5 ns CC 0.0 − ns SR 10.6 − ns SR 0.0 − ns CC − 2.6 ns CC 0.0 − ns SR 1.3 − ns SR 0.9 − ns CC − 6.3 ns CC 1.3 − ns CC 10 − ns CC 0 − ns Address output valid time from output clock Address output hold time from output clock WAIT input setup time to output clock WAIT input hold time from output clock AD(31:0) output valid time from output clock AD(31:0) output hold time from output clock AD(31:0) input setup time to output clock AD(31:0) input hold time from output clock RMW output valid time from output clock RMW output hold time from output clock ADV width AD(31:0) output hold time from RD/WR t3 t4 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 1) The purpose for characterization of Asynchronous access is to provide the performance of all of the signals to user. User can decide whether an extra cycle is needed or not based on above parameters to generate signals with correct timing sequence. It is user’s responsibility to program the correct phase length according to the memory/peripheral device specification and EBU specification. Data Sheet 92 V0.3, 2003-09 TC1130 Write Access Address Phase(s) Command Delay Phase(s) (ext.) Command Delay Phase(s) (int.) Command Phase(s) Data Hold Phase(s) Recovery Phase SDCLKO t15 t1 ADV t2 t3 Address t4 Address t2 t1 CSx t1 RD/WR t2 t16 t1 MR/W t5 t6 CMDELAY t7 WAIT t1 t8 t1 BC[3:0] t2 t2 t9 t10 DataOut AD[31:0] Read Access Address Phase(s) SDCLKO/ SDCLKI ADV t 15 t1 Command Delay Phase(s) (ext.) Command Delay Phase(s) (int.) Recovery Phase Command Phase(s) t2 t3 Address CSx t4 Address t2 t1 t2 t1 RD t2 MR/W t5 t6 CMDELAY t7 WAIT t1 t8 t1 BC[3:0] t2 t11 DataIn AD[31:0] RMW t12 t14 t13 Demux_Timing Figure 30 Data Sheet Demultiplexed Asynchronous Device Access Timing 93 V0.3, 2003-09 TC1130 Timing for Multiplexed Access Signals (Operating Conditions apply; CL = 50 pF)1) Parameter Symbol Limits min Unit max ALE, CSx, RD/WR, RD, MR/W, BC(3:0) output valid t1 time from output clock CC − 3.2 ns ALE, CSx, RD/WR, RD, MR/W, BC(3:0) output hold t2 time from output clock CC 0.0 − ns CC − 2.6 ns CC 0.0 − ns SR 1.4 − ns SR 0.8 − ns SR 10.6 − ns SR 0.0 − ns CC − 6.3 ns CC 1.3 − ns CC 10.0 − ns CC 0 − ns AD(31:0) output valid time from output clock AD(31:0) output hold time from output clock AD(31:0) input setup time to output clock AD(31:0) input hold time from output clock WAIT input setup time to output clock WAIT input hold time from output clock RMW output valid time from output clock RMW output hold time from output clock ADV width AD(31:0) output hold time from RD/WR t3 t4 t5 t6 t9 t10 t11 t12 t13 t14 1) The purpose for characterization of Asynchronous access is to provide the performance of all of the signals to user. User can decide whether an extra cycle is needed or not based on above parameters to generate signals with correct timing sequence. It is user’s responsibility to program the correct phase length according to the memory/peripheral device specification and EBU Specification. Data Sheet 94 V0.3, 2003-09 TC1130 Write Access Address Phase(s) Address Hold Phase(s) Command Command Delay Delay Phase(s) Phase(s) (ext.) (int.) Command Phase(s) Data Hold Phase(s) Recovery Phase(s) SDCLKO ADV t13 t1 t2 t3 AD[31:0] t4 t3 Data Address t4 t2 t1 CSx t1 RD/WR t2 t14 t1 MR/W t7 t8 CMDELAY t9 WAIT t1 t10 t1 BC[3:0] t2 t2 Read Access Address Phase(s) SDCLKO/ SDCLKI ADV t 13 t1 Address Hold Phase(s) Command Delay Phase(s) (int.) CSx Command Phase(s) Recovery Phase(s) t2 t3 AD[31:0] Command Delay Phase(s) (ext.) t5 t4 Address t6 Data t2 t1 t1 RD t2 1 t2 MR/W t7 t8 CMDELAY t9 WAIT t1 t10 t1 BC[3:0] t2 t12 t11 RMW Mux_Timing Figure 31 Data Sheet Write Access in Multiplexed Access 95 V0.3, 2003-09 TC1130 Timing for External Bus Arbitration Signals (Operating Conditions apply; CL = 50 pF) Parameter Symbol Limits min HOLD input setup time to output clock HOLD input hold time from output clock HLDA output valid time from output clock HLDA output hold time from output clock HLDA input setup time to output clock HLDA input hold time from output clock BREQ output valid time from output clock BREQ output hold time from output clock CSx drive from EBUCLK CSx high-impedance from EBUCLK Other signals high-impedance from EBUCLK Other signals drive from EBUCLK Data Sheet 96 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 Unit max SR 7.3 − ns SR 0.0 − ns CC − 6.2 ns CC 1.0 − ns SR 7.4 − ns SR 0.0 − ns CC − 6.4 ns CC 1.0 − ns CC − 3.1 ns CC − 3.1 ns CC − 3.2 ns CC − 3.2 ns V0.3, 2003-09 TC1130 Arbiter Mode SDCLKO HOLD t1 t2 t4 t3 HLDA BREQ t8 t7 t9 t10 CSx t9 Other signals t12 t11 Participant Mode SDCLKO t7 t8 BREQ HLDA t5 t6 t1 HOLD CSx Other signals t2 t9 t10 t12 t11 Arbitration_Timing Figure 32 Data Sheet External Bus Arbitration Timing 97 V0.3, 2003-09 TC1130 Timing for Ethernet Signals (Operating Conditions apply; CL = 50 pF) Parameter Symbol Limits min ETXCLK period (10 Mbps Ethernet) ETXCLK high time (10 Mbps Ethernet) ETXCLK low time (10 Mbps Ethernet) ETXCLK period (100 Mbps Ethernet) ETXCLK high time (100 Mbps Ethernet) ETXCLK low time (100 Mbps Ethernet) ERXCLK period (10 Mbps Ethernet) ERXCLK high time (10 Mbps Ethernet) ERXCLK low time (10 Mbps Ethernet) ERXCLK period (100 Mbps Ethernet) ERXCLK high time (100 Mbps Ethernet) ERXCLK low time (100 Mbps Ethernet) ERXD(3:0) input setup to ERXCLK ERXD(3:0) input hold from ERXCLK ERXDV input setup to ERXCLK ERXDV input hold from ERXCLK ERXER input setup to ERXCLK ERXER input hold from ERXCLK ETXD(3:0) output valid from ETXCLK ETXEN output valid from ETXCLK ETXER output valid from ETXCLK EMDC clock period EMDC high time EMDC low time EMDIO input setup to EMDC (sourced by STA) EMDIO input hold from EMDC (sourced by STA) EMDIO output valid from EMDC (sourced by PHY) t1 t2 t3 t1 t2 t3 t1 t2 t3 t1 t2 t3 t4 t5 t4 t5 t4 t5 t6 t6 t6 t7 t8 t9 t10 t11 t12 Unit max SR 400.0 − ns SR 140 260 ns SR 140 260 ns SR 40.0 − ns SR 14 26 ns SR 14 26 ns SR 400.0 − ns SR 140 260 ns SR 140 260 ns SR 40.0 − ns SR 14 26 ns SR 14 26 ns SR 10.0 − ns SR − 10.0 ns SR 10.0 − ns SR − 10.0 ns SR 10.0 − ns SR − 10.0 ns CC − 25.0 ns CC − 25.0 ns CC − 25.0 ns CC 400.0 − ns CC 160 − ns CC 160 − ns SR 10.0 − ns SR − 10.0 ns CC − 300.0 ns Note: Any other parameters which are not stated here, please refer to ANSI/IEEE Std 802.3, Section 22.3. Data Sheet 98 V0.3, 2003-09 TC1130 t1 ETXCLK ERXCLK t2 t3 t4 ERXD(3:0) ERXDV ERXER t5 valid data t6 ETXD(3:0) ETXEN ETXER valid data t7 EMDC t8 t9 t10 EMDIO (sourced by STA) t11 valid data t12 EMDIO (sourced by PHY) Figure 33 Data Sheet valid data Ethernet Timing 99 V0.3, 2003-09 TC1130 SSC Master Mode Timing (Operating Conditions apply; CL = 50 pF) Parameter Symbol Limit Values min. max. Unit SCLK clock frequency 1 / t SCLK CC - 25 MHz SCLK clock high time t1 CC 18 - ns SCLK clock low time t2 CC 18 - ns SCLK clock rise time t3 CC - 11 ns SCLK clock fall time t4 CC - 11 ns MTSR/SLSOx low/high from SCLK t 5 edge CC - 2.0 ns MRST setup to SCLK edge t6 SR 7 - ns MRST hold from SCLK edge t7 SR 5 - ns tSCLK t1 t2 t4 t3 0.9 V DD 0.1 V DD SCLK (CON.PO,CON.PH = 00 or 11) t2 SCLK t1 t3 t4 0.9 V DD 0.1 V DD (CON.PO,CON.PH = 01 or 10) t5 MTSR State n-1 State n State n+1 t5 SLSOx 1) t6 MRST t7 Data valid Data valid 1) The transition SLSOx is based on the following setup: SSOTC.TRAIL = 0 and the first SCLK high pulse is in the first one of a transmission. Figure 34 Data Sheet SSC Master Mode Timing 100 V0.3, 2003-09 TC1130 Timing for MLI Interface (Operating Conditions apply; CL = 50 pF) Parameter Symbol Limit Values Unit min. max. 26.67 – ns CC 9 – ns CC 9 – ns CC – 3 ns CC – 3 ns CC 0 8 ns t6 RDATAx, RVALIDx inputs setup to RCLK t7 SR tbd – ns SR 5.3 – ns RDATAx, RVALIDx inputs hold from RCLK t8 SR tbd – ns RREADYx outputs delay hold RCLK t9 CC tbd tbd ns TCLK/RCLK clock period t0 CC/SR TCLK high time TCLK low time TCLK rise time TCLK fall time TDATAx, TVALIDx outputs delay from TCLK t1 t2 t3 t4 t5 TREADYx inputs setup to TCLK Data Sheet 101 V0.3, 2003-09 TC1130 t3 t4 t0 t1 T C LK x t2 t5 t5 T D AT Ax T V A LI D x t6 t6 T R EAD Yx t0 t1 R C LK x t2 t7 t8 R D AT Ax R V A LI D x Figure 35 MLI Interface Timing Note: The generation of RREADYx is in the input clock domain of the receiver. The reception of TXREADY is asynchronous to TCLKx (input synchronization with each edge of TCLKx). Meeting the setup time for TXREADY guarantees recognition of the TXREADY at a certain clock edge. Data Sheet 102 V0.3, 2003-09 TC1130 Timing for JTAG Signals (Operating Conditions apply; CL = 50 pF) Parameter Symbol Limits min tTCK CC t1 CC t2 CC t3 CC t4 CC TCK clock period TCK high time TCK low time TCK clock rise time TCK clock fall time Unit max 50 − ns 10 − ns 29 − ns − 0.4 ns − 0.4 ns 0.9 VDD 0.5 VDD 0.1 VDD TCK t1 t2 t4 t3 tTCK Figure 36 Data Sheet TCK Clock Timing 103 V0.3, 2003-09 TC1130 Parameter Symbol Limits min TMS setup to TCK TMS hold to TCK TDI setup to TCK TDI hold to TCK TDO valid output from TCK TDO high impedance to valid output from TCK TDO valid output to high impedance from TCK t1 t2 t1 t2 t3 t4 t5 Unit max SR 7.85 − ns SR 3.0 − ns SR 10.9 − ns SR 3.0 − ns CC − 10.7 ns CC − 23.0 ns CC − 26.0 ns TCK t1 t2 t1 t2 TMS TDI t4 t3 t5 TDO Figure 37 Data Sheet JTAG Timing 104 V0.3, 2003-09 TC1130 Timing for OCDS Trace and Breakpoint Signals (Operating Conditions apply;CL(TRCLK) = 25 pF, CL = 50 pF) Parameter Symbol Limits min t1 t1 t1 t1 BRK_OUT valid from TRCLK OCDS2_STATUS[4:0] valid from TRCLK OCDS2_INDIR_PC[7:0] valid from TRCLK OCDS2_BRKPT[2:0] valid from TRCLK Unit max CC − 5.2 ns CC 1.7 3.7 ns CC 1.7 3.7 ns CC 1.7 3.7 ns TRCLK t1 CPU Trace Signals Note: Figure 38 Data Sheet Old State t1 New State CPU Trace Signals include BRK_IN, BRK_OUT, OCDS2_INDIR_PC[7:0] and OCDS_BRKPT[2:0]. OCDS2_STATUS[4:0], OCDS Trace Signals Timing 105 V0.3, 2003-09 TC1130 Timing for USB Transceiver Signals (Operating Conditions apply; CL = 50 pF) Parameter Symbol Limits min tFR CC 4 tFF CC 4 Full speed mode rise time Full speed mode fall time D+ D- 90% Unit max 20 ns 20 ns 90% 10% 10% tF tR rise_fall_USB.emf Figure 39 Data Sheet AC Testing: Input, Output Waveforms 106 V0.3, 2003-09 TC1130 Package Outline Plastic Package, P-LBGA-208-2 (SMD) (Low Profile Ball Grid Array Package) Figure 40 P-LBGA-208-2 Package You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Dimensions in mm SMD = Surface Mounted Device Data Sheet 107 V0.3, 2003-09 TC1130 Data Sheet 108 V0.3, 2003-09 Infineon goes for Business Excellence “Business excellence means intelligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results. Better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction.” Dr. Ulrich Schumacher http://www.infineon.com Published by Infineon Technologies AG