INFINEON TC1130_08

Data Sheet, V1.1, Dec 2008
TC1130
32-Bit Single-Chip Microcontroller
Microcontrollers
N e v e r
s t o p
t h i n k i n g .
Edition 2008-12
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2008.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet, V1.1, Dec 2008
TC1130
32-Bit Single-Chip Microcontroller
Microcontrollers
N e v e r
s t o p
t h i n k i n g .
TC1130 Data Sheet
Revision History:
2008-12
Previous Version:
V1.0, 2005-02
Page
Subjects (major changes since last revision)
77, 78, 79
,81, 82
Added “Operating Conditons apply” statement
V1.1
Controller Area Network (CAN): License of Robert Bosch GmbH
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
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TC1130
Table of Contents
Page
1
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2
2.1
2.2
2.3
2.4
General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3
4
5
6
3
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.4
3.4.1
3.4.2
3.4.3
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
3.18
3.19
3.20
3.21
3.22
3.23
3.24
3.25
3.26
3.27
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Protection System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection for Direct translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection for PTE based translation . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Bus System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Local Memory Bus (LMB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flexible Peripheral Interconnect Bus (FPI) . . . . . . . . . . . . . . . . . . . . . .
LFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LMB External Bus Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Direct Memory Access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Asynchronous/Synchronous Serial Interface (ASC) . . . . . . . . . . . . . . . . .
High-Speed Synchronous Serial Interface (SSC) . . . . . . . . . . . . . . . . . . .
Inter IC Serial Interface (IIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Universal Serial Bus Interface (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MultiCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Micro Link Serial Bus Interface (MLI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Purpose Timer Unit (GPTU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capture/Compare Unit 6 (CCU6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ethernet Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boot Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Identification Register Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
20
21
27
27
28
28
29
29
29
30
31
33
35
37
38
41
43
45
47
50
52
54
56
58
60
62
63
64
65
67
70
71
72
4
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Data Sheet
I-1
V1.1, 2008-12
TC1130
Table of Contents
Page
4.1
4.1.1
4.1.2
4.1.3
4.2
4.2.1
4.2.2
4.2.3
4.2.3.1
4.2.3.2
4.2.4
4.2.5
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.8.1
4.3.8.2
4.3.8.3
4.3.8.4
4.3.8.5
4.3.8.6
4.3.9
4.3.9.1
4.3.9.2
4.3.9.3
4.3.9.4
General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Absolute Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Operating Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
USB Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Full Speed Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 79
IIC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Power, Pad and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
PLL Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Input Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Timing for JTAG Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Timing for OCDS Trace and Breakpoint Signals . . . . . . . . . . . . . . . . . . 92
EBU Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
SDCLKO Output Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
BFCLKO Output Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Timing for SDRAM Access Signals . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Timing for Burst Flash Access Signals . . . . . . . . . . . . . . . . . . . . . . . 96
Timing for Demultiplexed Access Signals . . . . . . . . . . . . . . . . . . . . . 98
Timing for Multiplexed Access Signals . . . . . . . . . . . . . . . . . . . . . . 100
Peripheral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Timing for Ethernet Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
SSC Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
MLI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Timing for USB Transceiver Signals . . . . . . . . . . . . . . . . . . . . . . . . 106
5
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Data Sheet
I-2
V1.1, 2008-12
32-Bit Single-Chip Microcontroller
TriCore™ Family
1
TC1130
Summary of Features
• High Performance 32-bit TriCore™ V1.3 CPU with 4-Stage Pipeline
• Floating Point Unit (FPU)
• Dual Issue super-scalar implementation
– MAC Instruction maximum triple issue
• Circular Buffer and bit-reverse addressing modes for DSP algorithms
• Very fast interrupt response time
• Hardware controlled context switch for task switch and interrupts
• Memory Management Unit (MMU)
• On-chip Memory
– 28-Kbyte Data Memory (SPRAM)
– 32-Kbyte Code Memory (SPRAM)
– 16-Kbyte Instruction Cache (ICACHE)
– 4-Kbyte Data Cache (DCACHE)
– 64-Kbyte SRAM Data Memory Unit (DMU)
– 16-Kbyte Boot ROM
• On-chip Bus Systems
– 64-bit High Performance Local Memory Bus (LMB) for fast access between caches
and on-local memories and FPI Interface
– On-chip Flexible Peripheral Interconnect Bus (FPI) for interconnections of
functional units
• DMA Controller with 8 channels for data transfer operations between peripheral units
and memory locations
• Two high speed Micro Link Interfaces (MLI0/1) for controller communication and
emulation
• Flexible External Bus Interface Unit (EBU) to access external data memories
• One Multifunctional General Purpose Timer Unit (GPTU) with three 32-bit timer/
counters
• Two Capture and Compare units (CCU60/1) for PWM signal generation, each with
– 3-channel, 16 bit Capture and Compare unit
– 1-channel, 16 bit Compare unit
• Three Asynchronous/Synchronous Serial Channels (ASC0/1/2) with baud-rate
generator, parity, framing and overrun error detection, support FIFO and IrDA data
transmission
• Two High Speed Synchronous Serial Channels (SSC0/1) with programmable data
length, FIFO support and shift direction
Data Sheet
1
V1.1, 2008-12
TC1130
Summary of Features
• One MultiCAN module with four CAN nodes and 128 message buffers for high
efficiency data handling
• Fast Ethernet Controller with 10/100 Mbit/sec MII-Based physical devices support
• USB module with compliance to USB Specification Revision 1.1, with support for
1.5 MBaud to 12 MBaud devices
• Inter-IC (IIC) module with two physical IIC buses
• Digital I/O ports with 3.3 V I/O capabilities
• Level 2 On-chip Debug Support
• Power Management System
• Clock Generation Unit with PLL
• Maximum CPU and Bus clock frequency at 150 MHz without MMU and 120 MHz with
MMU
• Ambient temperature under bias: -40° to +85°C
• P-LBGA-208 package
Data Sheet
2
V1.1, 2008-12
Figure 2-1
Data Sheet
3
8
PORT4
8
8
7
DTxCLK
MDIO
D+ RxCLK
15
16
PORT3
4 8
13
11 2 1
16
PORT2
8
4
IIC
2
Channels
SSC1
16
PORT1
2
ASC0
FIFO,
IrDA
Cerberus
16 1 3 3 3 1 6 3 2 1 1
SSC0
BRKOUT
STM
16
PORT0
23
24
32
JTAG
PLL
8
5
7
JTAG I/O
BRKIN
XTAL2
XTAL1
Control
EBU_Control
A[23:0]
AD[31:0]
External
Interrupts
ASC2
FIFO,
IrDA
EBU
2 2 3 2 2
ASC1
FIFO,
IrDA
SCU
(PWR)
Power
Management,
Watchdog Timer,
Reset
PMI
(ProgramMemory
Interface)
32 KB Scratch Pad RAM
16 KB Instruction Cache
Block Diagram
8
DMA Bus, 32 Bit
MultiCAN
CCU6
SBCU
GPTU
4 nodes CCU61 CCU60 3Timers FPI BUS
64
2.1
MLI0
Ethernet
FPI Bus (Flexible Peripheral Interface), 32 Bit
OCDS2
TriCoreTM 1M
CPU
CPS
OCDS
FPU
VSS
VDD
General Device Information
MLI1
USB
LFI
Bridge
DMI
128
(Data Memory Interface)
28 KB Scratch Pad RAM
4 KB Data Cache
1.5-3.3V
TC1130
BlockDiagram
2
Cedar_BLK
Mem
Checker
Boot-ROM
16 KB
DMA
8
channels
SMIF
LBCU
LMB
BUS
DMU
64KB
SRAM
MMU
LMB (Local Memory Bus) 64 Bit
TC1130
General Device Information
TC1130 Block Diagram
V1.1, 2008-12
TC1130
General Device Information
2.2
Logic Symbol
General Control
EBU Control
PORST
HDRST
NMI
HWCFG[0:2]
RD
RD/WR
WAIT
MR/W
BFCLKI
BFCLKO
ALE
BAA
ADV
CS[0:3]
CSCOMB
CKE
Port 0 16-Bit
3
Port 1 16-Bit
Port 2 16-Bit
SSC0/1, CCU61, MLI1, OCDS
Port 4 8-Bit
USB, MLI0, SCU
TDO
TMS
BRKIN
4
TC1130
TRCLK
MII_TxCLK
MII_RxCLK
MII_MDIO
D+
4
OCDS / JTAG Control
Ethernet Clock
USB
DXTAL1
XTAL2
VDDOSC3
VSSOSC3
A[0:23]
AD[0:31]
Digital Circuitry
Power Supply
Port 3 16-Bit
TRST
TCK
TDI
RAS
CAS
SDCLKI
SDCLKO
BC[0:3]
Alternate Functions
GPTU, MultiCAN, SSC0/1,
ASC1/2, CCU60, MLI0, EBU,
SCU, External Interrupts
SSC0/1, MultiCAN, Ethernet,
EBU, SCU, OCDS
ASC0/1/2, SSC0/1, IIC,
CCU60, EBU, SCU
9
VDD
6
VDDP
14
VSS
Oscillator
VDDOSC
VSSOSC
MCB04945mod
Figure 2-2
Data Sheet
TC1130 Logic Symbol
4
V1.1, 2008-12
TC1130
General Device Information
2.3
Pin Configuration
A
B
C
D
E
F
G
H
J
K
Reser
ved
P3.10
P3.11
P3.12
P2.15
P2.14
P2.11
P2.9
P2.8
P2.7
15
P3.0
P3.1
P3.8
P3.2
P3.3
P3.6
P3.5
P3.9
P3.15
P2.12
VSS
P0.3
P2.4
P0.1
P0.9
D-
15
14
P1.9
P1.10
P1.11
P1.14
P1.13
P1.15
P3.4
P3.7
P3.14
P2.13
HW
CFG1
HW
CFG0
P2.5
P2.3
P0.10
D+
14
13
P1.8
P1.7
P1.5
V DDP
VSS
P1.12
VDD
V SS
V DDP
P3.13
P2.10
VSS
VDDP
P2.2
P0.8
TDI
13
12
P1.6
P1.3
P1.1
P1.2
P2.6
P2.0
P0.5
TCK
12
11
BAA
ADV
P1.4
P1.0
P0.0
P2.1
P0.4
TRST
11
10
A17
A18
A19
A20
9
A16
WAIT
CS2
CS0
8
A15
CS3
AD0
CS1
7
BC3
BC2
AD1
AD16
6
BC1
AD2
AD3
RAS
5
BC0
AD17
AD4
CAS
4
AD18
AD19
AD20
V DDP
V SS
AD28
AD29
V DDP
V SS
A14
CKE
V DDP
3
AD5
AD21
AD7
AD25
AD11
AD12
AD15
AD30
A10
A11
A12
A13
2
AD6
AD22
AD8
AD9
AD26
AD27
AD31
AD14
A5
A6
A7
A8
A9
RD
MII_
MII_
2
RXCLK TXCLK
1
Reser
ved
AD23
AD24 BFCLKI BFCLKO AD10
A0
A1
A2
A3
A4
MII_
MDIO
Reser
ved
A
B
K
L
M
N
P
R
T
16
C
D
L
M
V DDOSC XTAL1
208-Pin P-LBGA Package Pin
Configuration (top view)
for TC1130
N
XTAL2
P
R
VDD
VSS
OSC3
F
Reser 16
ved
V DD
V SS
V SS
VDD
P0.7
P0.2
P0.6
TDO
10
V DD
V SS
V SS
VDD
P0.11
P0.12
P4.1
TMS
9
V DD
V SS
V SS
VDD
P0.14
P0.13
P4.0
V DD
V SS
V SS
VDD
P4.2
P0.15
P4.5
NMI
7
P4.3
P4.4
P4.6
HW
CFG2
6
PORST BRKIN
5
HDRST P4.7
E
T
AD13 SDCLKO SDCLKI
G
H
J
VSS
A23
CS
MR/W
COMB
A22
ALE
TRCLK 8
A21
4
RD/WR 3
1
MCP04950mod
Figure 2-3
Data Sheet
TC1130 Pins: P-BGA-208 Package (top view)
5
V1.1, 2008-12
TC1130
General Device Information
2.4
Table 2-1
Symbol
Pin Definitions and Functions
Pin Definitions and Functions
Pin
P0
P0.0
N11
P0.1
P15
P0.2
P10
P0.3
M15
P0.4
R11
P0.5
R12
P0.6
R10
P0.7
N10
P0.8
R13
P0.9
R15
P0.10
R14
P0.11
N9
Data Sheet
In
PU/
Out PD1)
Functions
I/O
Port 0
Port 0 is a 16-bit bi-directional general purpose I/O port
which can be alternatively used for GPTU, MultiCAN,
ASC1/2, SSC0/1, MLI0, EBU and SCU.
GPTU_0
GPTU input/output line 0
RXD1B
ASC1 receiver input/output B
GPTU_1
GPTU input/output line 1
TXD1B
ASC1 transmitter output B
GPTU_2
GPTU input/output line 2
RXD2B
ASC2 receiver input/output B
GPTU_3
GPTU input/output line 3
TXD2B
ASC2 transmitter output B
GPTU_4
GPTU input/output line 4
SLSI1
SSC1 Slave Select input
BREQ
EBU Bus Request Output
GPTU_5
GPTU input/output line 5
HOLD
EBU Hold Request Input
CC60_T12HR CCU60 Timer 12 hardware run
BRKOUT_B OCDS Break Out B
GPTU_6
GPTU input/output line 6
HLDA
EBU Hold Acknowledge Input/Output
CC60_T13HR CCU60 Timer 13 hardware run
SLSO0_0
SSC0 Slave Select output 0
GPTU_7
GPTU input/output line 7
SLSO1_0
SSC1 Slave Select output 0
RXDCAN0_A CAN node 0 receiver input A
REQ0
External Trigger Input 0
TCLK0A
MLI0 transmit channel clock output A
TXDCAN0_A CAN node 0 transmitter output A
TREADY0A MLI0 transmit channel ready input A
REQ1
External Trigger Input 1
RXDCAN1_A CAN node 1 receiver input A
REQ2
External Trigger Input 2
TVALID0A
MLI0 transmit channel valid output A
TXDCAN1_A CAN node 1 transmitter output A
REQ3
External Trigger Input 3
TDATA0A
MLI0 transmit channel data output A
I/O
I/O
I/O
O
I/O
I/O
I/O
O
I/O
I
O
I/O
I
I
O
I/O
I/O
I
O
I/O
O
I
I
O
O
I
I
I
I
O
O
I
O
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
6
V1.1, 2008-12
TC1130
General Device Information
Table 2-1
Pin Definitions and Functions (cont’d)
Symbol
Pin
In
PU/
Out PD1)
Functions
P0.12
P9
P0.13
P8
P0.14
N8
P0.15
P7
I
I
I
O
I
O
I
I
I
O
I
I
RXDCAN2
RCLK0A
REQ4
TXDCAN2
REQ5
RREADY0A
RXDCAN3
REQ6
RVALID0A
TXDCAN3
REQ7
RDATA0A
Data Sheet
PUC
PUC
PUC
PUC
7
CAN node 2 receiver input
MLI0 receive channel clock input A
External Trigger Input 4
CAN node 2 transmitter output
External Trigger Input 5
MLI0 receive channel ready output A
CAN node 3 receiver input
External Trigger Input 6
MLI0 receive channel valid input A
CAN node 3 transmitter output
External Trigger Input 7
MLI0 receive channel data input A
V1.1, 2008-12
TC1130
General Device Information
Table 2-1
Symbol
Pin Definitions and Functions (cont’d)
Pin
P1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
In
PU/
Out PD1)
Functions
I/O
Port 1
Port 1 serves as 16-bit bi-directional general purpose
I/O port which can be used for input/output for Ethernet
controller, MultiCAN, CAN, OCDS L2, SSC0/1, EBU
and SCU.
MII_TXD0
Ethernet controller transmit data
output line 0
RXDCAN0_B CAN node 0 receiver input B
SWCFG0
Software configuration 0
OCDSA_0
OCDS L2 Debug Line A0
MII_TXD1
Ethernet controller transmit data
output line 1
SWCFG1
Software configuration 1
TXDCAN0_B CAN node 0 transmitter output B
OCDSA_1
OCDS L2 Debug Line A1
MII_TXD2
Ethernet controller transmit data
output line 2
RXDCAN1_B CAN node 1 receiver input B
SWCFG2
Software configuration 2
OCDSA_2
OCDS L2 Debug Line A2
MII_TXD3
Ethernet controller transmit data
output line 3
TXDCAN1_B CAN node 1 transmitter output B
SWCFG3
Software configuration 3
OCDSA_3
OCDS L2 Debug Line A3
MII_TXER
Ethernet controller transmit error
output line
SWCFG4
Software configuration 4
OCDSA_4
OCDS L2 Debug Line A4
MII_TXEN
Ethernet controller transmit enable
output line
SWCFG5
Software configuration 5
OCDSA_5
OCDS L2 Debug Line A5
MII_MDC
Ethernet controller management data
clock output line
SWCFG6
Software configuration 6
OCDSA_6
OCDS L2 Debug Line A6
D11
O
PUC
C12
I
I
O
O
PUC
D12
I
O
O
O
PUC
B12
I
I
O
O
PUC
C11
O
I
O
O
PUC
C13
I
O
O
PUC
A12
I
O
O
PUC
I
O
Data Sheet
8
V1.1, 2008-12
TC1130
General Device Information
Table 2-1
Pin Definitions and Functions (cont’d)
Symbol
Pin
In
PU/
Out PD1)
Functions
P1.7
B13
I
MII_RXDV
P1.8
A13
P1.9
A14
P1.10
B14
I
O
I
I
O
I
I
O
I
C14
I
O
I
F13
I
O
O
I
E14
I
O
O
I
D14
I
O
O
I
P1.11
P1.12
P1.13
P1.14
P1.15
Data Sheet
F14
O
I
O
I
O
I
O
PUC
PUC
SWCFG7
OCDSA_7
MII_CRS
SWCFG8
OCDSA_8
MII_COL
SWCFG9
OCDSA_9
MII_RXD0
PUC
SWCFG10
OCDSA_10
MII_RXD1
PUC
SWCFG11
OCDSA_11
SLSO0_1
MII_RXD2
PUC
SWCFG12
OCDSA_12
SLSO1_1
MII_RXD3
PUC
SWCFG13
OCDSA_13
SLSO0_2
MII_RXER
PUC
PUC
PUC
SLSO1_2
SWCFG14
OCDSA_14
SLSI0
RMW
SWCFG15
OCDSA_15
9
Ethernet Controller receive data valid
input line
Software configuration 7
OCDS L2 Debug Line A7
Ethernet Controller carrier input line
Software configuration 8
OCDS L2 Debug Line A8
Ethernet Controller collision input line
Software configuration 9
OCDS L2 Debug Line A9
Ethernet Controller receive data input
line 0
Software configuration 10
OCDS L2 Debug Line A10
Ethernet Controller receive data input
line 1
Software configuration 11
OCDS L2 Debug Line A1
SSC0 Slave Select output 1
Ethernet Controller receive data input
line 2
Software configuration 12
OCDS L2 Debug Line A12
SSC1 Slave Select output 1
Ethernet Controller receive data input
line 3
Software configuration 13
OCDS L2 Debug Line A13
SSC0 Slave Select output 2
Ethernet Controller receive error input
line
SSC1 Slave Select output 2
Software configuration 14
OCDS L2 Debug Line A14
SSC0 Slave Select Input
EBU Read Modify Write
Software configuration 15
OCDS L2 Debug Line A15
V1.1, 2008-12
TC1130
General Device Information
Table 2-1
Symbol
Pin Definitions and Functions (cont’d)
Pin
P2
In
PU/
Out PD1)
Functions
I/O
Port 2
Port 2 is a 16-bit bi-directional general purpose I/O port
which can be alternatively used for ASC0/1/2, SSC0/1,
CCU60, IIC, EBU and SCU.
RXD0
ASC0 receiver input/output line
CSEMU
EBU Chip Select Output for Emulator
Region
TXD0
ASC0 transmitter output line
TESTMODE Test Mode Select Input
MRST0
SSC0 master receive/slave transmit
input/output
MTSR0
SSC0 master transmit/slave receive
input/output
SCLK0
SSC0 clock input/output line
COUT60_3
CCU60 compare channel 3 output
MRST1A
SSC1 master receive/slave transmit
input/output A
CC60_0
CCU60 input/output of capture
compare channel 0
MTSR1A
SSC1 master transmit/slave receive
input/output A
COUT60_0
CCU60 output of capture/compare
channel 0
SCLK1A
SSC1 clock input/output line A
CC60_1
CCU60 input/output of capture/
compare channel 1
RXD1A
ASC1 receiver input/output line A
COUT60_1
CCU60 output of capture/compare
channel 1
TXD1A
ASC1 transmitter output line A
CC60_2
CCU60 input/output of capture/
compare channel 2
RXD2A
ASC2 receiver input/output line A
COUT60_2
CCU60 output of capture/compare
channel 2
TXD2A
ASC2 transmitter output line A
SDA0
IIC Serial Data line 0
CTRAP0
CCU60 trap input
SLSO0_3
SSC0 Slave Select output 3
P2.0
P12
I/O
O
PUC
P2.1
P11
PUC
P2.2
P13
O
I
I/O
P2.3
P14
I/O
PUC
P2.4
P2.5
N15
N14
I/O
O
I/O
PUC
PUC
P2.6
N12
I/O
PUC
PUC
I/O
P2.7
K16
O
PUC
J16
I/O
I/O
PUC
H16
I/O
O
PUC
L13
O
I/O
PUC
P2.11
G16
I/O
O
PUC
P2.12
K15
P2.8
P2.9
P2.10
Data Sheet
O
I/O
I
O
⎯
10
V1.1, 2008-12
TC1130
General Device Information
Table 2-1
Pin Definitions and Functions (cont’d)
Symbol
Pin
In
PU/
Out PD1)
P2.13
K14
P2.14
F16
P2.15
E16
I/O
I
O
I
I/O
O
I
I/O
O
Data Sheet
⎯
⎯
⎯
Functions
SCL0
CCPOS0_0
SLSO1_3
CCPOS0_1
SDA1
SLSO0_4
CCPOS0_2
SCL1
SLSO1_4
11
IIC clock line 0
CCU60 Hall input signal 0
SSC1 Slave Select output 3
CCU60 Hall input signal 1
IIC Serial Data line 1
SSC0 Slave Select output 4
CCU60 Hall input signal 2
IIC clock line 1
SSC1 Slave Select output 4
V1.1, 2008-12
TC1130
General Device Information
Table 2-1
Symbol
Pin Definitions and Functions (cont’d)
Pin
P3
P3.0
A15
P3.1
B15
P3.2
In
PU/
Out PD1)
Functions
I/O
Port 3
Port 3 is a 16-bit bi-directional general purpose I/O
port which can be alternatively used for MLI1, CCU61,
SSC0/1 and OCDS Level 2 debug lines.
OCDSB_0
OCDS L2 Debug Line B0
COUT61_3
CCU61 compare channel 3 output
OCDSB_1
OCDS L2 Debug Line B1
CC61_0
CCU61 input/output of capture/
compare channel 0
OCDSB_2
OCDS L2 Debug Line B2
COUT61_0
CCU61 output of capture/compare
channel 0
OCDSB_3
OCDS L2 Debug Line B3
CC61_1
CCU61 input/output of capture/
compare channel 1
OCDSB_4
OCDS L2 Debug Line B4
COUT61_1
CCU61 output of capture/compare
channel 1
OCDSB_5
OCDS L2 Debug Line B5
CC61_2
CCU61 input/output of capture/
compare channel 2
OCDSB_6
OCDS L2 Debug Line B6
COUT61_2
CCU61 output of capture/compare
channel 2
OCDSB_7
OCDS L2 Debug Line B7
CTRAP1
CCU61 trap input
SLSO0_5
SSC0 Slave Select output 5
OCDSB_8
OCDS L2 Debug Line B8
CCPOS1_0
CCU61 Hall input signal 0
TCLK1
MLI1 transmit channel clock output
SLSO1_5
SSC1 Slave Select output 5
OCDSB_9
OCDS L2 Debug Line B9
CCPOS1_1
CCU61 Hall input signal 1
TREADY1
MLI1 transmit channel ready input
SLSO0_6
SSC0 Slave Select output 6
OCDSB_10
OCDS L2 Debug Line B10
CCPOS1_2
CCU61 Hall input signal 2
TVALID1
MLI1 transmit channel valid output
SLSO1_6
SSC1 Slave Select output 6
O
O
O
I/O
PUC
D15
O
O
PUC
P3.3
E15
O
I/O
PUC
P3.4
G14
O
O
PUC
P3.5
G15
O
I/O
PUC
P3.6
F15
O
O
PUC
P3.7
H14
PUC
P3.8
C15
P3.9
H15
P3.10
B16
O
I
O
O
I
O
O
O
I
I
O
O
I
O
O
Data Sheet
PUC
PUC
PUC
PUC
12
V1.1, 2008-12
TC1130
General Device Information
Table 2-1
Pin Definitions and Functions (cont’d)
Symbol
Pin
In
PU/
Out PD1)
Functions
P3.11
C16
PUC
P3.12
D16
P3.13
K13
O
O
O
I
O
I
O
I
O
O
I/O
P3.14
J14
O
I
I/O
PUC
P3.15
J15
O
I
I/O
PUC
OCDSB_11
OCDS L2 Debug Line B11
TDATA1
MLI1 transmit channel data output
SLSO0_7
SSC0 Slave Select output 7
CC61_T12HR CCU61 Timer 12 hardware run
OCDSB_12
OCDS L2 Debug Line B12
RCLK1
MLI1 receive channel clock input
SLSO1_7
SSC1 Slave Select output 7
CC61_T13HR CCU61 Timer 13 hardware run
OCDSB_13
OCDS L2 Debug Line B13
RREADY1
MLI1 receive channel ready output
MRST1B
SSC1 master receive/slave
transmit input/output B
OCDSB_14
OCDS L2 Debug Line B14
RVALID1
MLI1 receive channel valid input
MTSR1B
SSC1 master transmit/slave
receive input/output B
OCDSB_15
OCDS L2 Debug Line B15
RDATA1
MLI1 receive channel data input
SCLK1B
SSC1 clock input/output line B
Data Sheet
PUC
PUC
13
V1.1, 2008-12
TC1130
General Device Information
Table 2-1
Symbol
Pin Definitions and Functions (cont’d)
Pin
P4
In
PU/
Out PD1)
Functions
I/O
Port 4
Port 4 is an 8-bit bi-directional general purpose I/O
port which can be alternatively used for USB, MLI0 and
SCU.
USBCLK
48 MHz input clock
TCLK0B
MLI0 transmit channel clock output B
RCVI
USB data input
TREADY0B MLI0 transmit channel ready input B
VPI
USB D+ CMOS level mirror of
differential signal
TVALID0B
MLI0 transmit channel valid output B
VMI
USB D- CMOS level mirror of
differential signal
TDATA0B
MLI0 transmit channel data output B
VPO
USB D+ CMOS level output
RCLK0B
MLI0 receive channel clock input B
VMO
USB D- CMOS level output
RREADY0B MLI0 receive channel ready output B
USBOE
Direction select for transmit or receive
RVALID0B
MLI0 receive channel valid input B
RDATA0B
MLI0 receive channel data input B
BRKOUT_A OCDS Break Out A
P4.0
R8
P4.1
R9
P4.2
N7
I
O
I
I
I
N6
O
I
P4.3
O
O
I
O
O
O
I
I
O
PUC
PUC
PUC
PUC
P4.4
P6
P4.5
R7
P4.6
R6
P4.7
P5
HDRST
N5
I/O
PUA
Hardware Reset Input/Reset Indication Output
Assertion of this bi-directional open-drain pin causes a
synchronous reset of the chip through external
circuitry. This pin must be driven for a minimum 4 fCPU
clock cycles.
The internal reset circuitry drives this pin in response
to a power-on, hardware, watchdog and power-down
wake-up reset for a specific period of time. For a
software reset, activation of this pin is programmable.
PORST
R5
I
PUC
Power-on Reset Input
A low level on PORST causes an asynchronous reset
of the entire chip. PORST is a fully asynchronous level
sensitive signal.
NMI
T7
I
PUC
Non-Maskable Interrupt Input
A high-to-low transition on this pin causes an
NMI-Trap request to the CPU.
Data Sheet
PUC
PUC
PUC
PUC
14
V1.1, 2008-12
TC1130
General Device Information
Table 2-1
Pin Definitions and Functions (cont’d)
Symbol
Pin
In
PU/
Out PD1)
Functions
TRST
T11
I
PDC
JTAG Module Reset/Enable Input
A low level at this pin resets and disables the JTAG
module. A high level enables the JTAG module.
TCK
T12
I
PUC
JTAG Module Clock Input
TDI
T13
I
PUC
JTAG Module Serial Data Input
TDO
T10
O
⎯
JTAG Module Serial Data Output
TMS
T9
I
PUC
JTAG Module State Machine Control Input
TRCLK
T8
O
⎯
Trace Clock for OCDS_L2 Lines
HWCFG0 M14
HWCFG1 L14
HWCFG2 T6
I
I
I
PUC
PUC
PDC
Hardware Configuration Inputs
The Configuration Inputs define the boot options of the
TC1130 after a hardware invoked reset operation.
BRKIN
T5
I
PUC
OCDS Break Input
A low level on this pin causes a break in the chip’s
execution when the OCDS is enabled. In addition, the
level of this pin during power-on reset determines the
boot configuration.
MII_
TXCLK
T2
I
PDC
Ethernet Controller Transmit Clock
MII_TXD[3:0] and MII_TXEN are driven off the rising
edge of the MII_TXCLK by the core and sampled by
the PHY on the rising edge of the MII_TXCLK.
MII_
RXCLK
R2
I
PDC
Ethernet Controller Receive Clock
MII_RXCLK is a continuous clock. Its frequency is
25 MHz for 100 Mbit/sec operation, and 2.5 MHz for
10 Mbit/sec. MII_RXD[3:0], MII_RXDV and MII_EXER
are driven by the PHY off the falling edge of
MII_RXCLK and sampled on the rising edge of
MII_RXCLK.
MII_
MDIO
R1
I/O
PDA
Ethernet Controller Management Data Input/
Output
When a read command is being executed, the data
that is clocked out of the PHY will be presented on the
input line. When the Core is clocking control or data
onto the MII_MDIO line, the signal will carry the
information.
D+
T14
I/O
⎯
USB D+ Data Line
Data Sheet
15
V1.1, 2008-12
TC1130
General Device Information
Table 2-1
Pin Definitions and Functions (cont’d)
Functions
Symbol
Pin
In
PU/
Out PD1)
D-
T15
I/O
⎯
USB D- Data Line
CS0
CS1
CS2
CS3
D9
D8
C9
B8
O
O
O
O
PUC
PUC
PUC
PUC
EBU Chip Select Output Line 0
EBU Chip Select Output Line 1
EBU Chip Select Output Line 2
EBU Chip Select Output Line 3
Each corresponds to a programmable region. Only
one can be active at one time.
CSCOMB N3
O
PUC
EBU Chip Select Output for combination function
(Overlay Memory and Global)
SDCLKI
J1
I
⎯
SDRAM Clock Input (Clock Feedback)
SDCLKO
H1
O
⎯
SDRAM Clock Output
Accesses to SDRAM devices are synchronized to this
clock.
RAS
D6
O
PUC
EBU SDRAM Row Address Strobe Output
CAS
D5
O
PUC
EBU SDRAM Column Address Strobe Output
CKE
L4
O
PUC
EBU SDRAM Clock Enable Output
BFCLKI
D1
I
⎯
Burst Flash Clock Input (Clock Feedback)
BFCLKO
E1
O
⎯
RD
P2
O
PUC
RD/WR
T3
O
PUC
EBU Write Control Line
Output in master mode
Input in slave mode
WAIT
B9
I
PUC
EBU Wait Control Line
ALE
R3
O
PDC
EBU Address Latch Enable Output
MR/W
P3
O
PUC
EBU Motorola-style Read/Write Output
BAA
A11
O
PUC
ADV
B11
O
PUC
EBU Burst Address Advance Output
For advancing address in a Burst Flash access
EBU Burst Flash Address Valid Output
Data Sheet
Burst Flash Clock Output
Accesses to Burst Flash devices are synchronized to
this clock.
EBU Read Control Line
Output in master mode
Input in slave mode
16
V1.1, 2008-12
TC1130
General Device Information
Table 2-1
Pin Definitions and Functions (cont’d)
Functions
Symbol
Pin
In
PU/
Out PD1)
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C8
C7
B6
C6
C5
A3
A2
C3
C2
D2
F1
E3
F3
G1
H2
G3
D7
B5
A4
B4
C4
B3
B2
B1
C1
D3
E2
F2
F4
G4
H3
G2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
EBU Address/Data Bus Input/Output Lines
EBU Address/Data Bus Line 0
EBU Address/Data Bus Line 1
EBU Address/Data Bus Line 2
EBU Address/Data Bus Line 3
EBU Address/Data Bus Line 4
EBU Address/Data Bus Line 5
EBU Address/Data Bus Line 6
EBU Address/Data Bus Line 7
EBU Address/Data Bus Line 8
EBU Address/Data Bus Line 9
EBU Address/Data Bus Line 10
EBU Address/Data Bus Line 11
EBU Address/Data Bus Line 12
EBU Address/Data Bus Line 13
EBU Address/Data Bus Line 14
EBU Address/Data Bus Line 15
EBU Address/Data Bus Line 16
EBU Address/Data Bus Line 17
EBU Address/Data Bus Line 18
EBU Address/Data Bus Line 19
EBU Address/Data Bus Line 20
EBU Address/Data Bus Line 21
EBU Address/Data Bus Line 22
EBU Address/Data Bus Line 23
EBU Address/Data Bus Line 24
EBU Address/Data Bus Line 25
EBU Address/Data Bus Line 26
EBU Address/Data Bus Line 27
EBU Address/Data Bus Line 28
EBU Address/Data Bus Line 29
EBU Address/Data Bus Line 30
EBU Address/Data Bus Line 31
BC0
BC1
BC2
BC3
A5
A6
B7
A7
O
O
O
O
PUC
PUC
PUC
PUC
EBU Byte Control Line 0
EBU Byte Control Line 1
EBU Byte Control Line 2
EBU Byte Control Line 3
Data Sheet
17
V1.1, 2008-12
TC1130
General Device Information
Table 2-1
Pin Definitions and Functions (cont’d)
Functions
Symbol
Pin
In
PU/
Out PD1)
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
K1
L1
M1
N1
P1
J2
K2
L2
M2
N2
J3
K3
L3
M3
K4
A8
A9
A10
B10
C10
D10
T4
R4
P4
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
XTAL1
XTAL2
M16
N16
I
O
⎯
⎯
Oscillator/PLL/Clock Generator Input/Output Pins
XTAL1 is the input to the main oscillator amplifier and
input to the internal clock generator. XTAL2 is the
output of the main oscillator amplifier circuit. For
clocking of the device from an external source, XTAL1
is driven with the clock signal while XTAL2 is left
unconnected. For crystal oscillator operation, XTAL1
and XTAL2 are connected to the crystal with the
appropriate recommended oscillator circuitry.
VDDOSC3
VSSOSC3
VDDOSC
P16
⎯
⎯
Main Oscillator Power Supply (3.3 V)
R16
⎯
⎯
Main Oscillator Ground
L16
⎯
⎯
Main Oscillator Power Supply (1.5 V)
Data Sheet
EBU Address Bus Input/Output Lines
EBU Address Bus Line 0
EBU Address Bus Line 1
EBU Address Bus Line 2
EBU Address Bus Line 3
EBU Address Bus Line 4
EBU Address Bus Line 5
EBU Address Bus Line 6
EBU Address Bus Line 7
EBU Address Bus Line 8
EBU Address Bus Line 9
EBU Address Bus Line 10
EBU Address Bus Line 11
EBU Address Bus Line 12
EBU Address Bus Line 13
EBU Address Bus Line 14
EBU Address Bus Line 15
EBU Address Bus Line 16
EBU Address Bus Line 17
EBU Address Bus Line 18
EBU Address Bus Line 19
EBU Address Bus Line 20
EBU Address Bus Line 21
EBU Address Bus Line 22
EBU Address Bus Line 23
18
V1.1, 2008-12
TC1130
General Device Information
Table 2-1
Pin Definitions and Functions (cont’d)
Symbol
Pin
In
PU/
Out PD1)
Functions
VSSOSC
VDD
L15
⎯
⎯
Main Oscillator Ground
G7
⎯
G8
G9
G10
G13
K7,K8
K9
K10
⎯
Core and Logic Power Supply (1.5 V)
VDDP
D4
D13
H4
J13
M4
N13
⎯
⎯
Ports Power Supply (3.3 V)
VSS
E4
E13
H7
H8
H9
H10
H13
J4,J7
J8,J9
J10
M13
N4
⎯
⎯
Ground
N.C.
A1
A16
T1
T16
⎯
⎯
Not Connected
These pins must not be connected.
1) Refers to internal pull-up or pull-down device connected and corresponding type. The notation ‘⎯’ indicates
that the internal pull-up or pull-down device is not enabled.
Note: P2.12 to P2.15 are always configured as open drain.
Data Sheet
19
V1.1, 2008-12
TC1130
Functional Description
3
Functional Description
3.1
On-Chip Memories
The TC1130 provides the following on-chip memories:
• Program Memory Interface (PMI) with
– 32-Kbyte Scratch-pad Code RAM (SPRAM)
– 16-Kbyte Instruction Cache Memory (ICACHE)
• Data Memory Interface (DMI) with
– 28-Kbyte Scratch-pad Data RAM (SPRAM)
– 4-Kbyte Data Cache Memory (DCACHE)
• Data Memory Unit (DMU) with
– 64-Kbyte SRAM
• 16-Kbyte Boot ROM (BROM)
Data Sheet
20
V1.1, 2008-12
TC1130
Functional Description
3.2
Address Map
Table 3-1 defines the specific segment oriented address blocks of the TC1130 with its
address range, size, and PMI/DMI access view. Table 3-2 shows the block address map
of the Segment 15 which includes on-chip peripheral units and ports.
Table 3-1
TC1130 Block Address Map
Seg- Address
ment Range
0 – 7 0000 0000H –
7FFF FFFFH
8
8000 0000H –
8FFF FFFFH
9
9000 0000H –
9FDF FFFFH
10
11
12
A000 0000H –
AFBF FFFFH
Size
Description
2 GB
MMU Space
256 MB External Memory Space
mapped from Segment 10
256 MB Reserved
via
LMB
via
LMB
DMU Space
AFC0 0000H – 64 KB
AFC0 FFFFH
AFC1 0000H – ~4 MB Reserved
AFFF FFFFH
B000 0000H – 256 MB Reserved
BFFF FFFFH
via
FPI
via
FPI
C000 0000H –
C000 FFFFH
64 KB
DMU
via
LMB
via
LMB
C001 0000H –
CFFF FFFFH
~ 256
MB
Reserved
Data Sheet
252 MB External Memory Space
DMI
PMI
Acc.
Acc.
via FPI via
FPI
via
via
LMB
LMB
via FPI via
FPI
21
c
a
c
h
e
d
n
o
nc
a
c
h
e
d
c
a
c
h
e
d
V1.1, 2008-12
TC1130
Functional Description
TC1130 Block Address Map (cont’d)
Seg- Address
ment Range
D000 0000H –
D000 6FFFH
D000 7000H –
D3FF FFFFH
D400 0000H –
D400 7FFFH
13
Size
Description
28 KB
DMI Local Data RAM
(LDRAM)
~ 64 MB Reserved
32 KB
PMI Local Code Scratch Pad
RAM (SPRAM)
D400 8000H –
D7FF FFFFH
~64 MB Reserved
D800 0000H –
DDFF FFFFH
96 MB
E000 0000H –
E7FF FFFFH
128 MB External Memory Space
E800 0000H –
E83F FFFFH
4 MB
E840 0000H –
E84F FFFFH
1 MB
E850 0000H –
E85F FFFFH
1 MB
Data Sheet
PMI
Acc.
via
LMB
via
LMB
PMI
local
via
LMB
via
LMB
–
–
External Memory Space
Emulator Memory Space
DE00 0000H – 16 MB
DEFF FFFFH
DF00 0000H – ~16 MB Reserved
DFFF BFFFH
Boot ROM Space
DFFF C000H – 16 KB
DFFF FFFFH
14
DMI
Acc.
DMI
local
via FPI via
FPI
via
LMB
access
only
from
FPI
bus
side of
LFI
Reserved for mapped space
access
for lower 1 Mbyte of Local
only
Memory in Segment 13
from
(Transformed by LFI bridge to FPI
D000 0000H – D00F FFFFH) bus
side of
Reserved for mapped space
for 1 Mbyte of Local Memory in LFI
Segment 13
(Transformed by LFI bridge to
D400 0000H – D40F FFFFH)
Reserved for mapped space
for lower 4 Mbytes of Local
Memory in Segment 12
(Transformed by LFI bridge to
C000 0000H – C03F FFFFH)
22
via
LMB
access
only
from
FPI
bus
side of
LFI
access
only
from
FPI
bus
side of
LFI
non-cached
Table 3-1
V1.1, 2008-12
TC1130
Functional Description
Table 3-1
TC1130 Block Address Map (cont’d)
Seg- Address
ment Range
14 E860 0000H –
EFFF FFFFH
15 F000 0000H –
FFFF FFFFH
Table 3-2
Size
Description
122 MB Reserved
256 MB See Table 3-2
DMI
Acc.
–
PMI
Acc.
–
n
o
nvia
via
c
LMB or LMB or a
via
via
c
FPI
FPI
h
e
d
Block Address Map of Segment 15
Symbol Description
Address Range
Size
System Peripheral Bus (SPB)
SCU
System Control Unit (incl. WDT)
F000 0000H - F000 00FFH 256 Bytes
SBCU
FPI Bus Control Unit
F000 0100H - F000 01FFH 256 Bytes
STM
System Timer
F000 0200H - F000 02FFH 256 Bytes
OCDS
On-Chip Debug Support
(Cerberus)
F000 0300H - F000 03FFH 256 Bytes
–
Reserved
F000 0400H - F000 04FFH 256 Bytes
–
Reserved
F000 0500H - F000 05FFH 256 Bytes
GPTU
General Purpose Timer Unit
F000 0600H - F000 06FFH 256 Bytes
–
Reserved
F000 0700H - F000 07FFH 256 Bytes
–
Reserved
F000 0800H - F000 08FFH 256 Bytes
–
Reserved
F000 0900H - F000 09FFH 256 Bytes
–
Reserved
F000 0A00H - F000 0AFFH 256 Bytes
–
Reserved
F000 0B00H - F000 0BFFH 256 Bytes
P0
Port 0
F000 0C00H - F000 0CFFH 256 Bytes
P1
Port 1
F000 0D00H - F000 0DFFH 256 Bytes
P2
Port 2
F000 0E00H - F000 0EFFH 256 Bytes
P3
Port 3
F000 0F00H - F000 0FFFH 256 Bytes
P4
Port 4
F000 1000H - F000 10FFH 256 Bytes
–
Reserved
F000 1100H - F000 11FFH 256 Bytes
Data Sheet
23
V1.1, 2008-12
TC1130
Functional Description
Table 3-2
Block Address Map of Segment 15 (cont’d)
Symbol Description
Address Range
Size
–
Reserved
F000 1200H - F000 12FFH 256 Bytes
–
Reserved
F000 1300H - F000 13FFH 256 Bytes
–
Reserved
F000 1400H - F000 14FFH 256 Bytes
–
Reserved
F000 1500H - F000 15FFH 256 Bytes
–
Reserved
F000 1600H - F000 16FFH 256 Bytes
–
Reserved
F000 1700H - F000 17FFH 256 Bytes
–
Reserved
F000 1800H - F000 18FFH 256 Bytes
–
Reserved
F000 1900H - F000 19FFH 256 Bytes
CCU60
Capture/Compare Unit 0
F000 2000H - F000 20FFH 256 Bytes
CCU61
Capture/Compare Unit 1
F000 2100H - F000 21FFH 256 Bytes
–
Reserved
F000 2200H - F000 3BFFH –
DMA
Direct Memory Access Controller
F000 3C00H - F000 3EFFH 3 × 256
Bytes
–
Reserved
F000 3F00H - F000 3FFFH –
CAN
MultiCAN Controller
F000 4000H - F000 5FFFH 8 Kbytes
–
Reserved
F000 6000H - F00E 1FFFH –
USB
USB RAM based Registers
F00E 2000H - F00E 219FH 416 Bytes
USB
USB RAM
F00E 21A0H - F00E 27FFH 1.6 Kbytes
USB
USB Registers
F00E 2800H - F00E 28FFH 256 Bytes
–
Reserved
F00E 2900H - F00F FFFFH –
Units on SMIF Interface of DMA Controller
–
Reserved
F010 0000H - F010 00FFH 256 Bytes
SSC0
Synchronous Serial Interface 0
F010 0100H - F010 01FFH 256 Bytes
SSC1
Synchronous Serial Interface 1
F010 0200H - F010 02FFH 256 Bytes
ASC0
Async./Sync. Serial Interface 0
F010 0300H - F010 03FFH 256 Bytes
ASC1
Async./Sync. Serial Interface 1
F010 0400H - F010 04FFH 256 Bytes
ASC2
Async./Sync. Serial Interface 2
F010 0500H - F010 05FFH 256 Bytes
I2C
Inter IC
F010 0600H - F010 06FFH 256 Bytes
–
Reserved
F010 0700H - F010 BFFFH –
MLI0
Micro Link Interface 0
F010 C000H - F010 C0FFH 256 Bytes
MLI1
Micro Link Interface 1
F010 C100H - F010 C1FFH 256 Bytes
Data Sheet
24
V1.1, 2008-12
TC1130
Functional Description
Table 3-2
Block Address Map of Segment 15 (cont’d)
Symbol Description
Address Range
MCHK
Memory Checker
F010 C200H - F010 C2FFH 256 Bytes
–
Reserved
F010 C300H - F01D FFFFH –
MLI0_
SP0
MLI0 Small Transfer Window 0
F01E 0000H - F01E 1FFFH 8 Kbytes
MLI0_
SP1
MLI0 Small Transfer Window 1
F01E 2000H - F01E 3FFFH 8 Kbytes
MLI0_
SP2
MLI0 Small Transfer Window 2
F01E 4000H - F01E 5FFFH 8 Kbytes
MLI0_
SP3
MLI0 Small Transfer Window 3
F01E 6000H - F01E 7FFFH 8 Kbytes
MLI1_
SP0
MLI1 Small Transfer Window 0
F01E 8000H - F01E 9FFFH 8 Kbytes
MLI1_
SP1
MLI1 Small Transfer Window 1
F01E A000H - F01E BFFFH 8 Kbytes
MLI1_
SP2
MLI1 Small Transfer Window 2
F01E C000H- F01E DFFFH 8 Kbytes
MLI1_
SP3
MLI1 Small Transfer Window 3
F01E E000H - F01E FFFFH 8 Kbytes
–
Reserved
F01F 0000H - F01F FFFFH –
MLI0_
LP0
MLI0 Large Transfer Window 0
F020 0000H - F020 FFFFH 64 Kbytes
MLI0_
LP1
MLI0 Large Transfer Window 1
F021 0000H - F021 FFFFH 64 Kbytes
MLI0_
LP2
MLI0 Large Transfer Window 2
F022 0000H - F022 FFFFH 64 Kbytes
MLI0_
LP3
MLI0 Large Transfer Window 3
F023 0000H - F023 FFFFH 64 Kbytes
MLI1_
LP0
MLI1 Large Transfer Window 0
F024 0000H - F024 FFFFH 64 Kbytes
MLI1_
LP1
MLI1 Large Transfer Window 1
F025 0000H - F025 FFFFH 64 Kbytes
MLI1_
LP2
MLI1 Large Transfer Window 2
F026 0000H - F026 FFFFH 64 Kbytes
Data Sheet
25
Size
V1.1, 2008-12
TC1130
Functional Description
Table 3-2
Block Address Map of Segment 15 (cont’d)
Symbol Description
Address Range
Size
MLI1_
LP3
MLI1 Large Transfer Window 3
F027 0000H - F027 FFFFH 64 Kbytes
–
Reserved
F028 0000H - F200 00FFH –
ECU
Ethernet Controller Unit
F200 0100H - F200 05FFH 1280Bytes
–
Reserved
F200 0600H - F7E0 FEFFH –
CPU (Part of System Peripheral Bus)
CPU
SFRs
CPU Slave Interface
F7E0 FF00H - F7E0 FFFFH 256 Bytes
Reserved
F7E1 0000H - F7E1 7FFFH –
MMU
F7E1 8000H - F7E1 80FFH 256 Bytes
Reserved
F7E1 8100H - F7E1 BFFFH –
Memory Protection Registers
F7E1 C000H -F7E1 EFFFH 12 Kbytes
Reserved
F7E1 F000H - F7E1 FCFFH –
Core Debug Register (OCDS)
F7E1 FD00H -F7E1 FDFFH 256 Bytes
Core Special Function Registers
(CSFRs)
F7E1 FE00H -F7E1 FEFFH 256 Bytes
General Purpose Register (GPRs) F7E1 FF00H - F7E1 FFFFH 256 Bytes
–
Reserved
F7E2 0000H - F7FF FFFFH –
Local Memory Buses (LMB)
EBU
External Bus Interface Unit
F800 0000H - F800 03FFH 1 Kbyte
DMU
Data Memory Unit
F800 0400H - F800 04FFH 256 Bytes
–
Reserved
F800 0500H - F87F FBFFH –
DMI
Data Memory Interface Unit
F87F FC00H - F87F FCFFH 256 Bytes
PMI
Program Memory Interface Unit
F87F FD00H - F87F FDFFH 256 Bytes
LBCU
Local Memory Bus Control Unit
F87F FE00H - F87F FEFFH 256 Bytes
LFI
LMB to FPI Bus Bridge
F87F FF00H - F87F FFFFH 256 Bytes
–
Reserved
F880 0000H - FFFF FFFFH –
Data Sheet
26
V1.1, 2008-12
TC1130
Functional Description
3.3
Memory Protection System
The TC1130 memory protection system specifies the addressable range and read/write
permissions of memory segments available to the currently executing task. The memory
protection system controls the position and range of addressable segments in memory.
It also controls the types of read and write operations allowed within addressable
memory segments. Any illegal memory access is detected by the memory protection
hardware, which then invokes the appropriate Trap Service Routine (TSR) to handle the
error. Thus, the memory protection system protects critical system functions against both
software and hardware errors. The memory protection hardware can also generate
signals to the Debug Unit to facilitate tracing illegal memory accesses.
In TC1130, TriCore™ supports two address spaces: the virtual address space and the
physical address space. Both address spaces are 4 Gbytes in size and are divided into
16 segments with each segment being 256 Mbytes. The upper 4 bits of the 32-bit
address are used to identify the segment. Virtual segments are numbered 0 - 15. But a
virtual address is always translated into a physical address before accessing memory.
The virtual address is translated into a physical address using one of two translation
mechanisms: (a) direct translation, and (b) Page Table Entry (PTE) based translation. If
the virtual address belongs to the upper half of the virtual address space then the virtual
address is directly used as the physical address (direct translation). If the virtual address
belongs to the lower half of the address space, then the virtual address is used directly
as the physical address if the processor is operating in physical mode (direct translation)
or translated using a Page Table Entry if the processor is operating in Virtual mode (PTE
translation). These are managed by Memory Management Unit (MMU).
Memory protection is enforced using separate mechanisms for the two translation paths.
3.3.1
Protection for Direct translation
Memory protection for addresses that undergo direct translation is enforced using the
range based protection that has been used in the previous generation of the TriCore™
architecture. The range based protection mechanism provides support for protecting
memory ranges from unauthorized read, write, or instruction fetch accesses. The
TriCore™ architecture provides up to four protection register sets with the PSW.PRS
field controlling the selection of the protection register set. Because the TC1130 uses a
Harvard-style memory architecture, each Memory Protection Register Set is broken
down into a Data Protection Register Set and a Code Protection Register Set. Each Data
Protection Register Set can specify up to four address ranges to receive particular
protection modes. Each Code Protection Register Set can specify up to two address
ranges to receive particular protection modes.
Each of the Data Protection Register Sets and Code Protection Register Sets
determines the range and protection modes for a separate memory area. Each contains
register pairs which determine the address range (the Data Segment Protection
Registers and Code Segment Protection Registers) and one register (Data Protection
Data Sheet
27
V1.1, 2008-12
TC1130
Functional Description
Mode Register) which determines the memory access modes which apply to the
specified range.
3.3.2
Protection for PTE based translation
Memory protection for addresses that undergo PTE based translation is enforced using
the PTE used for the address translation. The PTE provides support for protecting a
process from unauthorized read, write, or instruction fetches by other processes. The
PTE has the following bits that are provided for the purpose of protection:
• Execute Enable (XE) enables instruction fetch to the page
• Write Enable (WE) enables data writes to the page
• Read Enable (RE) enables data reads from the page
Furthermore, User-0 accesses to virtual addresses in the upper half of the virtual
address space are disallowed when operating in virtual mode. In physical mode, User-0
accesses are disallowed only to segments 14 and 15. Any User-0 access to a virtual
address that is restricted to User-1 or supervisor mode will cause a Virtual Address
Protection (VAP) Trap in both the physical and virtual modes.
3.3.3
Memory Checker
The Memory Checker module (MCHK) makes it possible to check the data consistency
of memories. It uses DMA moves to read from the selected address area and to write the
value read in a memory checker input register (the moves should be 32-bit moves). A
polynomial checksum calculation is done with each write operation to the memory
checker input register.
Data Sheet
28
V1.1, 2008-12
TC1130
Functional Description
3.4
On-Chip Bus System
The TC1130 includes two bus systems:
• Local Memory Bus (LMB)
• Flexible Peripheral Interface Bus (FPI)
The LMB-to-FPI (LFI) bridge interconnects the FPI bus and LMB Bus.
3.4.1
Local Memory Bus (LMB)
The Local Memory Bus interconnects the memory units and functional units, such as
CPU and DMU. The main objective of the LMB bus is to support devices with fast
response time. This allows the DMI and PMI fast access to local memory and reduces
load on the FPI bus. The TriCore™ system itself is located on the LMB bus. Via External
Bus Unit, it interconnects TC1130 and external components.
The Local Memory Bus is a synchronous, pipelined, split bus with variable block size
transfer support. It supports 8, 16, 32 and 64 bits single beat transactions and variable
length 64 bits block transfers.
Features:
The LMB provides the following features:
•
•
•
•
•
•
•
•
•
Synchronous, Pipelined, Multimaster, 64-bit high performance bus
Optimized for high speed and high performance
32-bit address, 64-bit data buses
Central, simple per cycle arbitration
Slave controlled wait state insertion
Address pipelining (max depth - 2)
Supports Split transactions
Supports Variable block size transfer
Supports Locked transaction (read-modify-write)
3.4.2
Flexible Peripheral Interconnect Bus (FPI)
The FPI Bus is an on-chip bus that is used in modular and highly integrated
microprocessors and microcontrollers (systems-on-chips). FPI Bus is designed for
memory mapped data transfers between its bus agents. Bus agents are on-chip function
blocks (modules), equipped with an FPI Bus interface and connected via FPI Bus
signals. An FPI Bus agent acts as an FPI Bus master when it initiates data read or data
write operations once bus ownership has been granted to the agent. An FPI Bus agent
that is addressed by an FPI Bus operation acts as an FPI Bus slave when it performs the
requested data read or write operation.
Data Sheet
29
V1.1, 2008-12
TC1130
Functional Description
Features:
The FPI Bus is designed with the requirements of high-performance systems in mind.
The features are:
•
•
•
•
•
•
•
•
•
•
•
Core independent
Multimaster capability (up to 16 masters)
Demultiplexed operation
Clock synchronous
Peak transfer rate of up to 800 Mbytes/sec (@ 100 MHz bus clock)
Address and data bus scalable (address bus up to 32 bits, data bus up to 64 bits)
8-/16-/32- and 64-bit data transfers
Broad range of transfer types from single to multiple data transfers
Split transaction support for agents with long response time
Burst transfer capability
EMI and power consumption minimized
3.4.3
LFI
The LMB-to-FPI Interface (LFI) block provides the circuitry to interface (bridge) the FPI
bus and the Local Memory Bus (LMB).
LFI Features:
• Full support for bus transactions found within current TriCore™ 1.3 based systems:
– Single 8/16/32-bit Write/Read transfers from FPI to LMB
– Single 8/16/32/64-bit Write/Read transfers from LMB to FPI
– Read-Modify-Write transfers of 8/16/32-bit in both directions
– Burst transactions of 2, 4 or 8 data beats from the FPI to the LMB
– Burst transactions of 2 or 4 data beats from the LMB to the FPI
• Address decoding and translation as required by TriCore™ 1.3 implementation
• FPI master interface supports full pipelining on FPI bus
• LMB master interface supports pipelining on LMB within the scope of the LMB
specification
• FPI master interface can act as default master on FPI bus
• Programmable support for split LMB to FPI read transactions
• Retry generation on both FPI and LMB buses
• Full support for abort, retry, error and FPI timeout conditions
• Flexible LMB/FPI clock ratio support including dynamic clock switching support
• LFI core clock may be shut down when no transactions are being issued to LFI from
either bus and the LFI has no transactions in progress, thus saving power.
Data Sheet
30
V1.1, 2008-12
TC1130
Functional Description
3.5
LMB External Bus Unit
The LMB External Bus Control Unit (EBU) of the TC1130 is the interface between
external resources, like memories and peripheral units, and the internal resources
connected to on-chip buses if enabled. The basic structure and external interconnections
of the EBU are shown in Figure 3-1.
32
4
24
AD[31:0]
BC[3:0]
A[23:0]
RD
PMI
RD/WR
ALE
4
TriCore
CS[3:0]
LMB
TM
MMU
CSCOMB
ADV
BAA
DMI
WAIT
LFI
MR/W
EBU_LMB
BFCLKI
BFCLKO
FPI
CKE
CAS
To Peripherals
RAS
SDCLKI
SDCLKO
P0.4/BREQ
Port 0
Control
P0.5/HOLD
P0.6/HLDA
Port 2
Control
P2.0/CSEMU
Port 1
Control
P1.15/RMW
MCB04941_mod
Figure 3-1
Data Sheet
EBU Structure and Interface
31
V1.1, 2008-12
TC1130
Functional Description
The EBU is used primarily for any Local Memory Bus (LMB) master accessing external
memories. The EBU controls all transactions required for this operation and in particular
handles the arbitration between the internal EBU master and the external EBU master.
The types of external devices/bus modes controlled by the EBU are:
•
•
•
•
•
•
Intel-style peripherals (separate RD and WR signals)
ROMs, EPROMs
Static RAMs
PC100 and PC133 SDRAMs (Burst Read/Write Capacity/Multi-Bank/Page support)
Specific types of Burst Mode Flash devices
Special support for external emulator/debug hardware
Features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Supports 64-bit Local Memory Bus (LMB)
Supports external bus frequency: internal LMB frequency = 1:1 or 1:2
Provides highly programmable access parameters
Supports Intel-style peripherals/devices
Supports PC100 and PC133 (runs in maximum 120 MHz) SDRAM (burst access,
multibanking, precharge, refresh)
Supports 16- and 32-bit SDRAM data bus and 64-,128-, and 256-Mbit devices
Supports Burst Flash devices
Supports Multiplexed access (address and data on the same bus) when PC100 and
PC133 SDRAM are not presented on the external bus
Supports data buffering: Code Prefetch Buffer, Read/Write Buffer
External master arbitration compatible to C166 and other TriCore™ devices
Provides 4 programmable address regions (1 dedicated for emulator)
Provides a CSGLB signal, bit programmable to combine one or more CS lines for
buffer control
Provides RMW signal reflecting read-modify-write action
Supports Little Endian byte ordering
Provides signal for controlling data flow of slow-memory buffer
Data Sheet
32
V1.1, 2008-12
TC1130
Functional Description
3.6
Direct Memory Access (DMA)
The Direct Memory Access Controller executes DMA transactions from a source
address location to a destination address location, without intervention of the CPU. One
DMA transaction is controlled by one DMA channel. Each DMA channel has assigned
its own channel register set. The total of 8 channels are provided by one DMA sub-block.
The DMA module is connected to 3 bus interfaces in TC1130, the Flexible Peripheral
Interconnect Bus (FPI), the DMA Bus and the Micro Link Bus. It can do transfers on each
of the buses as well as between the buses.
In addition, it bridges accesses from the Flexible Peripheral Interconnect Bus to the
peripherals on the DMA Bus, allowing easy access to these peripherals by CPU. Clock
control, address decoding, DMA request wiring, and DMA interrupt service request
control are implementation specific and managed outside the DMA controller kernel.
Features:
• 8 independent DMA channels
– Up to 8 selectable request inputs per DMA channel
– Programmable priority of DMA channels within a DMA sub-block (2 levels)
– Software and hardware DMA request generation
– Hardware requests by selected peripherals and external inputs
• Programmable priority of the DMA sub-block on the bus interfaces
• Buffer capability for move actions on the buses (min. 1 move per bus is buffered).
• Individually programmable operation modes for each DMA channel
– Single mode: stops and disables DMA channel after a predefined number of DMA
transfers
– Continuous mode: DMA channel remains enabled after a predefined number of
DMA transfers; DMA transaction can be repeated.
– Programmable address modification
• Full 32-bit addressing capability of each DMA channel
– 4-Gbyte address range
– Support of circular buffer addressing mode
• Programmable data width of a DMA transaction: 8-bit, 16-bit, or 32-bit
• Micro Link supported
• Register set for each DMA channel
– Source and destination address register
– Channel control and status register
– Transfer count register
• Flexible interrupt generation (the service request node logic for the MLI channels is
also implemented in the DMA module)
• All buses/interfaces connected to the DMA module must work at the same frequency
• Read/write requests of the FPI Bus Side to the Remote Peripherals are bridged to the
DMA Bus (only the DMA is master on the DMA bus)
Data Sheet
33
V1.1, 2008-12
TC1130
Functional Description
The basic structure and external interconnections of the DMA are shown in Figure 3-2.
DMA Controller
f DMA
Clock
Control
Bus
Interface 0
M/S
Arbiter/
Switch Control
Address
Decoder
To FPI Bus
4
MultiCAN
ASC0
DMA Sub-Block 0
2
ASC0
ASC1
2
ASC2
8
SSC0
2
SSC1
1
CCU60
CCU61
1
DMA
Request
Wiring
Matrix
4
8
MLI0
Request
Assignment
and
Priorisation
Unit 0
Bus
Interface 1
M/S
ASC2
SSC0
SSC1
IIC
Transaction
Control Engine
4
Bus
Interface 2
SMIF
MLI1
1
I2C
DMA Bus
2
Channel
00-07
Registers
Switch
ASC1
DMA Bus
2
MLI0
MLI1
Mem Check
1
USB
SCU
(Ext.Trg)
4
Interrupt
Control
4
SR [15:12]
DMA Interrupt Control Unit
SR [3:0]
TC1130_DMAImplementation
Figure 3-2
Data Sheet
DMA Controller Structure and Interconnections
34
V1.1, 2008-12
TC1130
Functional Description
3.7
Interrupt System
An interrupt request can be serviced by the CPU, which is called “Service Provider”.
Interrupt requests are referred to as “Service Requests” in this document.
Each peripheral in the TC1130 can generate service requests. Additionally, the Bus
Control Unit, the Debug Unit, the DMA Controller and even the CPU itself can generate
service requests to the Service Provider. As shown in Figure 3-3, each unit that can
generate service requests is connected to one or multiple Service Request Nodes
(SRN). Each SRN contains a Service Request Control Register mod_SRC, where “mod”
is the identifier of the unit requesting service. The SRNs are connected to the Interrupt
Control Unit (ICU) via the CPU Interrupt Arbitration Bus. The ICU arbitrates service
requests for the CPU and administers the Interrupt Arbitration Bus.
Units that can generate service requests are:
• Asynchronous/Synchronous Serial Interfaces (ASC0, ASC1 and ASC2) with 4 SRNs
each
• High-Speed Synchronous Serial Interfaces (SSC0 and SSC1) with 3 SRNs each
• Inter IC Interface (IIC) with 3 SRNs
• Universal Serial Bus (USB) with 8 SRNs
• Micro Link Interface MLI0 with 4 SRNs and MLI1 with 2 SRNs
• General Purpose Timer Unit (GPTU) with 8 SRNs
• Capture/Compare Unit (CCU60 and CCU61) with 4 SRNs each
• MultiCAN (CAN) with 16 SRNs
• Ethernet Controller with 9 SRNs
• External Interrupts with 4 SRNs
• Direct Memory Access Controller (DMA) with 4 SRNs
• DMA Bus with 1 SRN
• System Timer (STM) with 2 SRNs
• Bus Control Units (SBCU and LBCU) with 1 SRN each
• Central Processing Unit (CPU) with 4 SRNs
• Floating Point Unit (FPU) with 1 SRN
• Debug Unit (OCDS) with 1 SRN
The CPU can make service requests directly to itself (via the ICU). The CPU Service
Request Nodes are activated through software.
Data Sheet
35
V1.1, 2008-12
TC1130
Functional Description
CPU
Interrupt
Arbitration Bus
Service
Requestors
ASC0
ASC1
ASC2
SSC0
SSC1
MLI0
MLI1
MultiCAN
Service Req.
Nodes
4
4
4
3
3
4
2
16
4 SRNs
4 SRNs
4 SRNs
3 SRNs
3 SRNs
4 SRNs
2 SRNs
16 SRNs
Interrupt
Service
Providers
4
Service Req.
Nodes
4
4
USB
GPTU
ETHERNET
STM
FPU
OCDS
DMA BUS
8
9
2
1
1
1
8 SRNs
8 SRNs
9 SRNs
2 SRNs
1 SRN
1 SRN
1 SRN
Software
Interrupts
4
CPU Interrupt
Control Unit
3
ICU
Int.
Req.
PIPN
3
4
CPU
Int. Ack.
CCPN
2
Service Req.
Nodes
16
4
8
4
4 SRNs
8
3
4 SRN
3 SRNs
Service
Requestors
4
3
Ext. Int.
IIC
8
4
9
4
2
1
1
1
1
4
4 SRNs
4 SRNs
1 SRN
1 SRN
4 SRNs
4
4
1
1
4
CCU60
CCU61
LBCU
SBCU
DMA
1
Interrupt System
Figure 3-3
Data Sheet
Block Diagram of the TC1130 Interrupt System
36
V1.1, 2008-12
TC1130
Functional Description
3.8
Parallel Ports
The TC1130 has 72 digital input/output port lines, which are organized into four parallel
16-bit ports and one parallel 8-bit port, Port P0 to Port P4 with 3.3 V nominal voltage.
The digital parallel ports can be used as general purpose I/O lines or they can perform
input/output functions for the on-chip peripheral units. An overview on the port-toperipheral unit assignment is shown in Figure 3-4.
Alternate Functions
GPIO
GPIO
16
Alternate Functions
16
GPIO3 SSC0/ SSC1/ CCU61/
MLI1/ OCDS
GPTU/ ASC1/ ASC2/ GPIO0
SSC0/ SSC1/ CCU60/
MultiCAN/ MLI0/ EBU/
SCU/ External Interrupts
16
TC1130
8
GPIO4 USB/ MLI0/ SCU
SSC0/ SSC1/ MultiCAN/ GPIO1
Ethernet/ EBU/ SCU/ OCDS
Parallel Ports
16
ASC0/ ASC1/ ASC2/ GPIO2
SSC0/ SSC1/ IIC/
CCU60/EBU/ SCU
Figure 3-4
Data Sheet
MCA04951mod
Parallel Ports of the TC1130
37
V1.1, 2008-12
TC1130
Functional Description
3.9
Asynchronous/Synchronous Serial Interface (ASC)
Figure 3-5 shows a global view of the functional blocks of three Asynchronous/
Synchronous Serial interfaces (ASC0, ASC1 and ASC2).
Each ASC module (ASC0/ASC1/ASC2) communicates with the external world via one
pair of I/O lines. The RXD line is the receive data input signal (in synchronous mode also
output). TXD is the transmit output signal. Clock control, address decoding, and interrupt
service request control are managed outside the ASC module kernel.
The Asynchronous/Synchronous Serial interfaces provide serial communication
between the TC1130 and other microcontrollers, microprocessors or external
peripherals.
Each ASC supports full-duplex asynchronous communication and half-duplex
synchronous communication. In synchronous mode, data is transmitted or received
synchronous to a shift clock which is generated by the ASC internally. In asynchronous
mode, 8-bit or 9-bit data transfer, parity generation, and the number of stop bits can be
selected. Parity, framing, and overrun error detection are provided to increase the
reliability of data transfers. Transmission and reception of data is double-buffered. For
multiprocessor communication, a mechanism is included to distinguish address bytes
from data bytes. Testing is supported by a loop-back option. A 13-bit baud-rate generator
provides the ASC with a separate serial clock signal that can be accurately adjusted by
a prescaler implemented as a fractional divider.
Data Sheet
38
V1.1, 2008-12
TC1130
Functional Description
Clock
Control
fASC0
RXD_I0
Address
Decoder
Interrupt
Control
ASC0
Module
(Kernel)
RXD_I1
P2.0/
RXD0
RXD_O
P2.1/
TXD0
TXD_O
EIR
TBIR
TIR
RIR
to DMA
Clock
Control
fASC1
P2.8/
RXD1A
RXD_I0
Address
Decoder
Interrupt
Control
P2.9/
TXD1A
RXD_I1
ASC1
Module
(Kernel)
RXD_O
TXD_O
EIR
TBIR
TIR
RIR
Port
Control
P0.0/
RXD1B
P0.1/
TXD1B
to DMA
Clock
Control
fASC1
RXD_I0
Address
Decoder
Interrupt
Control
RXD_I1
ASC2
Module
(Kernel)
Data Sheet
P2.11/
TXD2A
RXD_O
TXD_O
EIR
TBIR
TIR
RIR
P0.2/
RXD2B
P0.3/
TXD2B
to DMA
Figure 3-5
P2.10/
RXD2A
MCB04485_mod
General Block Diagram of the ASC Interfaces
39
V1.1, 2008-12
TC1130
Functional Description
Features:
• Full-duplex asynchronous operating modes
– 8-bit or 9-bit data frames, LSB first
– Parity bit generation/checking
– One or two stop bits
– Baud rate from 4.6875 MBaud to 1.1 Baud (@ 75 MHz clock)
• Multiprocessor mode for automatic address/data byte detection
• Loop-back capability
• Half-duplex 8-bit synchronous operating mode
– Baud rate from 9.375 MBaud to 762.9 Baud (@ 75 MHz clock)
• Support for IrDA data transmission up to 115.2 kBaud maximum
• Double buffered transmitter/receiver
• Interrupt generation
– On a transmitter buffer empty condition
– On a transmit last bit of a frame condition
– On a receiver buffer full condition
– On an error condition (frame, parity, overrun error)
• FIFO
– 8-byte receive FIFO (RXFIFO)
– 8-byte transmit FIFO (TXFIFO)
– Independent control of RXFIFO and TXFIFO
– 9-bit FIFO data width
– Programmable Receive/Transmit Interrupt Trigger Level
– Receive and Transmit FIFO filling level indication
– Overrun error generation
– Underflow error generation
Data Sheet
40
V1.1, 2008-12
TC1130
Functional Description
3.10
High-Speed Synchronous Serial Interface (SSC)
Figure 3-6 shows a global view of the functional blocks of two High-Speed Synchronous
Serial interfaces (SSC0 and SSC1).
Each SSC supports full-duplex and half-duplex serial synchronous communication up to
37.5 MBaud (@ 75 MHz module clock) with receive and transmit FIFO support. The
serial clock signal can be generated by the SSC itself (master mode) or can be received
from an external master (slave mode). Data width, shift direction, clock polarity and
phase are programmable. This allows communication with SPI-compatible devices.
Transmission and reception of data is double-buffered. A shift clock generator provides
the SSC with a separate serial clock signal. Eight slave select inputs are available for
slave mode operation. Eight programmable slave select outputs (chip selects) are
supported in master mode.
Features:
• Master and slave mode operation
– Full-duplex or half-duplex operation
– Automatic pad control possible
• Flexible data format
– Programmable number of data bits: 2 to 16 bits
– Programmable shift direction: LSB or MSB shift first
– Programmable clock polarity: idle low or high state for the shift clock
– Programmable clock/data phase: data shift with leading or trailing edge of the shift
clock
• Baud rate generation minimum at 572.2 Baud (@ 75 MHz module clock)
• Interrupt generation
– On a transmitter empty condition
– On a receiver full condition
– On an error condition (receive, phase, baud rate, transmit error)
• Four-pin interface
• Flexible SSC pin configuration
• Up to eight slave select inputs in slave mode
• Up to eight programmable slave select outputs SLSO in master mode
– Automatic SLSO generation with programmable timing
– Programmable active level and enable control
• 4-stage receive FIFO (RXFIFO) and 4-stage transmit FIFO (TXFIFO)
– Independent control of RXFIFO and TXFIFO
– 2- to 16-bit FIFO data width
– Programmable receive/transmit interrupt trigger level
– Receive and transmit FIFO filling level indication
– Overrun error generation
– Underflow error generation
Data Sheet
41
V1.1, 2008-12
TC1130
Functional Description
fSSC0
Clock
Control
Master
fCLC0
Slave
Address
Decoder
Slave
SSC0
Module
(Kernel)
Master
MRSTA
MRSTB
MTSR
P2.2/MRST0
MTSRA
MTSRB
MRST
P2.3/MTSR0
Port 2
Control
SCLKA
SCLKB
SLCK
M/S Select
Enable 1)
P2.4/SCLK0
1)
P2.12/SLSO03
P2.14/SLSO04
Interrupt
Control
EIR
TIR
RIR
SLSI1
Slave
to DMA
Master
SLSI[7:2]
P1.15/SLSI0
1)
Port 1
Control
SLSO0
SLSO[2:1]
P1.11/SLSO01
P1.13/SLSO02
SLSO[4:3]
SLSO[7:5]
P0.6/SLSO00
Port 0
Control
P0.4/SLSI1
P0.7/SLSO10
Slave
fSSC1
Clock
Control
fCLC1
SLSI1
SLSI[7:2]
SLSO0
P3.7/SLSO05
1)
P3.9/SLSO06
Port 3
Control
SLSO[2:1]
Master
P3.11/SLSO07
P3.8/SLSO15
SLSO[4:3]
P3.10/SLSO16
SLSO[7:5]
P3.12/SLSO17
Address
Decoder
Port 1
Control
SSC1
Module
(Kernel)
P1.12/SLSO11
P1.14/SLSO12
P2.13/SLSO13
P2.15/SLSO14
Interrupt
Control
EIR
TIR
RIR
Master
Slave
to DMA
M/S Select1)
Enable1)
Slave
Master
MRSTA
MRSTB
MTSR
MTSRA
MTSRB
MRST
Data Sheet
Port 2
Control
SCLKA
SCLKB
SLCK
1)
Figure 3-6
P2.5/MRST1A
These lines are not connected
P3.13/MRST1B
P2.6/MTSR1A
P3.14/MTSR1B
P2.7SCLK1A
P3.15/SCLK1B
MCB04486_mod
General Block Diagram of the SSC Interfaces
42
V1.1, 2008-12
TC1130
Functional Description
3.11
Inter IC Serial Interface (IIC)
Figure 3-7 shows a global view of the functional blocks of the Inter IC Serial interface
(IIC).
The IIC module has four I/O lines, located at Port 2. The IIC module is further supplied
with clock control, interrupt control and address decoding logic. One DMA request can
be generated by IIC module.
Clock
Control
fIIC
SDA0
P2.12/SDA0
SCL0
Address
Decoder
IIC
Module
INT_P
Interrupt
Control
P2.13/SCL0
Port 2
Control
SDA1
SCL1
P2.14/SDA1
P2.15/SCL1
INT_E
INT_D
to DMA
Figure 3-7
General Block Diagram of the IIC Interface
The on-chip IIC bus module connects the platform buses to other external controllers
and/or peripherals via the two-line serial IIC interface. One line is responsible for clock
transfer and synchronization (SCL), the other is responsible for the data transfer (SDA).
The IIC bus module provides communication at data rates of up to 400 kbit/sec and
features 7-bit addressing as well as 10-bit addressing. This module is fully compatible to
the IIC bus protocol.
The module can operate in three different modes:
Master mode, where the IIC controls the bus transactions and provides the clock signal.
Slave mode, where an external master controls the bus transactions and provides the
clock signal.
Multimaster mode, where several masters can be connected to the bus, i.e. the IIC can
be master or slave.
The on-chip IIC bus module allows efficient communication via the common IIC bus. The
module unloads the CPU of low level tasks such as:
• (De)Serialization of bus data
• Generation of start and stop conditions
• Monitoring the bus lines in slave mode
Data Sheet
43
V1.1, 2008-12
TC1130
Functional Description
• Evaluation of the device address in slave mode
• Bus access arbitration in multimaster mode
Features:
•
•
•
•
•
•
Extended buffer allows up to 4 send/receive data bytes to be stored
Selectable baud rate generation
Support of standard 100 kBaud and extended 400 kBaud data rates
Operation in 7-bit addressing mode or 10-bit addressing mode
Flexible control via interrupt service routines or by polling
Dynamic access to up to 2 physical IIC buses
Data Sheet
44
V1.1, 2008-12
TC1130
Functional Description
3.12
Universal Serial Bus Interface (USB)
Figure 3-8 shows a global view of the functional blocks of the Universal Serial Bus
interface (USB).
The USB module is further supplied with clock control, interrupt control, address
decoding, and port control logic. One DMA request can be generated by USB module.
Clock
Control
f USB
USBCLKB
Address
Decoder
RCVIB
P4.1 /RCVI
VPIB
P4.2 /VPI
VMIB
VPOB
ISR0
ISR1
ISR2
ISR3
Interrupt
Control
P4.0 /USBCLK
Port 4
Control
P4.4 /VPO
VMOB
USB
Module
(Kernel)
P4.3 /VMI
P4.5 /VMO
USBOEB
P4.6 /USBOE
ISR4
ISR5
D+
ISR6
D-
ISR7
To DMA
Figure 3-8
General Block Diagram of the USB Interface
The USB handles all transactions between the serial USB bus and the internal (parallel)
bus of the microcontroller. The USB module includes several units which are required to
support data handling with the USB bus: the on-chip USB transceiver (optionally), the
flexible USB buffer block with a 32-bit wide RAM, the buffer control unit with sub modules
for USB and CPU memory access control, the UDC_IF device interface for USB protocol
handling, the microcontroller interface unit (MCU) with the USB specific special function
registers and the interrupt generation unit. A clock generation unit provides the clock
signal for the USB module for full speed and low speed USB operation.
Data Sheet
45
V1.1, 2008-12
TC1130
Functional Description
Features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
USB1.1 Device Standard Interface
On-chip transceiver
Differential I/O allow cable length up to 5m without additional hardware at target’s end.
Hot attach
USB1.1 full speed device
USB protocol handling in hardware
Clock and data recovery from USB
Bit stripping and bit stuffing functions
CRC5 checking, CRC16 generation and checking
Serial to parallel data conversion
Maintenance of data synchronization bits (DATA0/DATA1 Toggle Bits)
Supports multiple configurations, interfaces and alternate settings
11 endpoints with user configurable endpoint information
Flexible intermediate buffering of transmission data
Powerful data handling capability, FIFO-support
Back-to-back transfers fully supported by module automatism
Multi-packet transfer without CPU load
Handles data transfer with minimum CPU load
Auto increment and single address modes selectable for easy data access
Powerful interrupt generation
Meets suspend power consumption restrictions in power-down mode
Remote wakeup from USB bus activity
Explicit support of setup information
Enhanced status monitoring
Data Sheet
46
V1.1, 2008-12
TC1130
Functional Description
3.13
MultiCAN
Figure 3-9 shows a global view of the functional blocks of the MultiCAN module.
fCAN
Clock
Control
Address
Decoder
Message
Object
Buffer
128
Objects
CAN
Node 3
TXDC3
CAN
Node 2
TXDC2
INT_O15
RXDC3
RXDC2
TXDC1A
Linked
List
Control
CAN
Node 1
CAN
Node 0
INT_O
[3:0]
Port 0
Control
RXDC1A
TXDC1B
RXDC1B
TXDC0A
DMA
Interrupt
Control
P0.15 /
TXDCAN3
P0.14 /
RXDCAN3
MultiCAN Module Kernel
fCLC
INT_O
[15:4]
RXDC0A
TXDC0B
RXDC0B
Port 1
Control
CAN Control
P0.13 /
TXDCAN2
P0.12 /
RXDCAN2
P0.11 /
TXDCAN1A
P0.10 /
RXDCAN1A
P0.9 /
TXDCAN0A
P0.8 /
RXDCAN0A
P1.1 /
TXDCAN0B
P1.0 /
RXDCAN0B
P1.3 /
TXDCAN1B
P1.2 /
RXDCAN1B
MultiCAN_TC1130_impl
Figure 3-9
General Block Diagram of the MultiCAN Interface
The MultiCAN module contains 4 Full-CAN nodes operating independently or
exchanging data and remote frames via a gateway function. Transmission and reception
of CAN frames is handled in accordance to CAN specification V2.0 B (active). Each CAN
node can receive and transmit standard frames with 11-bit identifiers as well as extended
frames with 29-bit identifiers.
All CAN nodes share a common set of message objects, where each message object
may be individually allocated to one of the CAN nodes. Besides serving as a storage
container for incoming and outgoing frames, message objects may be combined to build
gateways between the CAN nodes or to setup a FIFO buffer.
The message objects are organized in double chained lists, where each CAN node has
its own list of message objects. A CAN node stores frames only into message objects
that are allocated to the list of the CAN node. It only transmits messages from objects of
this list.
A powerful, command driven list controller performs all list operations.
Data Sheet
47
V1.1, 2008-12
TC1130
Functional Description
The bit timings for the CAN nodes are derived from the peripheral clock (fCAN) and are
programmable up to a data rate of 1 MBaud. A pair of receive and transmit pins connects
each CAN node to a bus transceiver.
Features:
•
•
•
•
•
•
•
•
•
•
Compliant to ISO 11898
CAN functionality according to CAN specification V2.0 B (active)
Dedicated control registers are provided for each CAN node
A data transfer rate up to 1 MBaud is supported
Flexible and powerful message transfer control and error handling capabilities are
implemented
Advanced CAN bus bit timing analysis and baud rate detection can be performed for
each CAN node via the frame counter
Full-CAN functionality: A set of 128 message objects can be individually
– allocated (assigned) to any CAN node
– configured as transmit or receive object
– setup to handle frames with 11-bit or 29-bit identifier
– counted or assigned a timestamp via a frame counter
– configured to remote monitoring mode
Advanced Acceptance Filtering:
– Each message object provides an individual acceptance mask to filter incoming
frames.
– A message object can be configured to accept only standard or only extended
frames or to accept both standard and extended frames.
– Message objects can be grouped into 4 priority classes.
– The selection of the message to be transmitted first can be performed on the basis
of frame identifier, IDE bit and RTR bit according to CAN arbitration rules.
Advanced Message Object Functionality:
– Message objects can be combined to build FIFO message buffers of arbitrary size,
which is only limited by the total number of message objects.
– Message objects can be linked to form a gateway to automatically transfer frames
between two different CAN buses. A single gateway can link any two CAN nodes.
An arbitrary number of gateways may be defined.
Advanced Data Management:
– The Message objects are organized in double chained lists.
– List reorganizations may be performed at any time, even during full operation of the
CAN nodes.
– A powerful, command driven list controller manages the organization of the list
structure and ensures consistency of the list.
– Message FIFOs are based on the list structure and can easily be scaled in size
during CAN operation.
Data Sheet
48
V1.1, 2008-12
TC1130
Functional Description
– Static Allocation Commands offer compatibility with TwinCAN applications, which
are not list based.
• Advanced Interrupt Handling:
– Up to 16 interrupt output lines are available. Most interrupt requests can be
individually routed to one of the 16 interrupt output lines.
– Message postprocessing notifications can be flexibly aggregated into a dedicated
register field of 256 notification bits.
Data Sheet
49
V1.1, 2008-12
TC1130
Functional Description
3.14
Micro Link Serial Bus Interface (MLI)
Figure 3-10 shows a global view of the functional blocks of two Micro Link Serial Bus
interfaces (MLI0 and MLI1).
Clock
Control
f MLI0
TCLK
TREADYA
TVALIDA
Address
Decoder
TDATA
RCLKA
Port
0
Control
RREADYA
MLI0
Module
(Kernel)
DMA
INT_O
TCLK
[3:0]
TREADYB
INT_O
TVALIDB
TDATA
[7:4]
RCLKB
MLI
Interface
Port
4
Control
RREADYB
RVALIDB
f MLI1
TREADYA
Address
Decoder
INT_O
[1:0]
INT_O
DMA
[7:4]
P4.4/RCLK0B
P3.8 /TCLK1
TCLK
Interrupt
Control
P4.0/
TCLK0B
P4.1/
TREADY0B
P4.2/
TVALID0B
P4.3/
TDATA0B
P4.5/
RREADY0B
P4.6/
RVALID0B
P4.7/
RDATA0B
RDATAB
Clock
Control
P0.12/RCLK0A
P0.13/
RREADY0A
P0.14/
RVALID0A
P0.15/
RDATA0A
RVALIDA
RDATAA
Interrupt
Control
P0.8/
TCLK0A
P0.9/
TREADY0A
P0.10/
TVALID0A
P0.11/
TDATA0A
MLI1
Module
(Kernel)
TVALIDA
TDATA
RCLKA
RREADYA
RVALIDA
RDATAA
MLI
Interface
Port
3
Control
P3.9 /
TREADY1A
P3.10 /
TVALID1A
P3.11 /
TDATA1
P3.12/
RCLK1A
P3.13 /
RREADY1A
P3.14 /
RVALID1A
P3.15 /
RDATA1A
MLI_Interfaces
Figure 3-10 General Block Diagram of the MLI0 and MLI1 Interfaces
Data Sheet
50
V1.1, 2008-12
TC1130
Functional Description
The Micro Link Serial Bus Interface is dedicated to the serial communication between
the other Infineon 32-bit controllers with MLI. The communication is intended to be fast
due to an address translation system, and it is not necessary to have any special
program in the second controller.
Features:
•
•
•
•
•
•
•
•
•
Serial communication from the MLI transmitter to MLI receiver of another controller
Module supports connection of each MLI with up to four MLI from other controllers
Fully transparent read/write access supported (= remote programming)
Complete address range of target controller available
Special protocol to transfer data, address offset, or address offset and data
Error control using a parity bit
32-bit, 16-bit, and 8-bit data transfers
Address offset width: from 1- to 16-bit
Baud rate: fMLI / 2 (symmetric shift clock approach),
baud rate definition by the corresponding fractional divider
Data Sheet
51
V1.1, 2008-12
TC1130
Functional Description
3.15
General Purpose Timer Unit (GPTU)
Figure 3-11 shows a global view of the functional blocks of the General Purpose Timer
Unit (GPTU).
IN0
Clock
Control
fGPTU0
IN1
IN2
IN3
P0.0/GPTU_0
IN4
Address
Decoder
IN5
P0.1/GPTU_1
IN6
P0.2/GPTU_2
IN7
SR0
Interrupt
Control
GPTU
Module
Port 0
Control
OUT0
P0.3/GPTU_3
P0.4/GPTU_4
SR1
OUT1
SR2
OUT2
P0.5/GPTU_5
SR3
OUT3
P0.6/GPTU_6
SR4
OUT4
SR5
OUT5
SR6
OUT6
SR7
OUT7
P0.7/GPTU_7
Figure 3-11 General Block Diagram of the GPTU Interface
The GPTU consists of three 32-bit timers designed to solve such application tasks as
event timing, event counting, and event recording. The GPTU communicates with the
external world via eight I/O lines located at Port 0.
The three timers of GPTU module, T0, T1 and T2, can operate independently of each
other or can be combined:
General Features:
•
•
•
•
All timers are 32-bit precision timers with a maximum input frequency of fGPTU
Events generated in T0 or T1 can be used to trigger actions in T2
Timer overflow or underflow in T2 can be used to clock either T0 or T1
T0 and T1 can be concatenated to form one 64-bit timer
Features of T0 and T1:
• Each timer has a dedicated 32-bit reload register with automatic reload on overflow
• Timers can be split into individual 8-, 16-, or 24-bit timers with individual reload
registers
Data Sheet
52
V1.1, 2008-12
TC1130
Functional Description
• Overflow signals can be selected to generate service requests, pin output signals, and
T2 trigger events
• Two input pins can define a count option
Features of T2:
• Count up or down is selectable
• Operating modes:
– Timer
– Counter
– Quadrature counter (incremental/phase encoded counter interface)
• Options:
– External start/stop, one-shot operation, timer clear on external event
– Count direction control through software or an external event
– Two 32-bit reload/capture registers
• Reload modes:
– Reload on overflow or underflow
– Reload on external event: positive transition, negative transition, or both transitions
• Capture modes:
– Capture on external event: positive transition, negative transition, or both
transitions
– Capture and clear timer on external event: positive transition, negative transition, or
both transitions
• Can be split into two 16-bit counter/timers
• Timer count, reload, capture, and trigger functions can be assigned to input pins. T0
and T1 overflow events can also be assigned to these functions.
• Overflow and underflow signals can be used to trigger T0 and/or T1 and to toggle
output pins
• T2 events are freely assignable to the service request nodes
Data Sheet
53
V1.1, 2008-12
TC1130
Functional Description
3.16
Capture/Compare Unit 6 (CCU6)
Figure 3-12 shows a global view of the functional blocks of two Capture/Compare Units
(CCU60 and CCU61).
Both of the CCU6 modules are further supplied with clock control, interrupt control,
address decoding, and port control logic. One DMA request can be generated by each
CCU6 module.
Each CCU6 provides two independent timers (T12, T13), which can be used for PWM
generation, especially for AC-motor control. Additionally, special control modes for block
commutation and multi-phase machines are supported.
Timer 12 Features:
• Three capture/compare channels, each channel can be used either as capture or as
compare channel
• Generation of a three-phase PWM supported (six outputs, individual signals for
highside and lowside switches)
• 16-bit resolution, maximum count frequency = peripheral clock
• Dead-time control for each channel to avoid short-circuits in the power stage
• Concurrent update of the required T12/13 registers
• Center-aligned and edge-aligned PWM can be generated
• Single-shot mode supported
• Many interrupt request sources
• Hysteresis-like control mode
Timer 13 Features:
•
•
•
•
•
One independent compare channel with one output
16-bit resolution, maximum count frequency = peripheral clock
Can be synchronized to T12
Interrupt generation at period-match and compare-match
Single-shot mode supported
Additional Features:
•
•
•
•
•
•
•
Block commutation for Brushless DC-drives implemented
Position detection via Hall-sensor pattern
Automatic rotational speed measurement for block commutation
Integrated error handling
Fast emergency stop without CPU load via external signal (CTRAP)
Control modes for multi-channel AC-drives
Output levels can be selected and adapted to the power stage
Data Sheet
54
V1.1, 2008-12
TC1130
Functional Description
Clock
Control
/CTRAP
fCCU
P2.12 /CTRAP0
CCPOS0
P2.13 /CCPOS00
CCPOS1
P2.14 /CCPOS01
CCPOS2
Address
Decoder
P2.15 /CCPOS02
CC60
P2.6 /CC600
COUT60
CCU60
Module
(Kernel)
CC61
COUT61
P2.7 /COUT600
Port 2
Control
CC62
P2.8 /CC601
P2.9 /COUT601
P2.10 /CC602
COUT62
P2.11 /COUT602
To DMA
COUT63
T12HR
SRC0
SRC1
SRC2
SRC3
T13HR
/CTRAP
CCPOS0
CCPOS1
CCPOS2
CC60
Interrupt
Control
COUT60
CCU61
Module
(Kernel)
CC61
Port 3
COUT61 Control
CC62
SRC0
SRC1
SRC2
SRC3
P0.5 /
CCU60_T12HR
P0.6 /
CCU60_T13HR
P3.7 /CTRAP1
P3.8 /CCPOS10
P3.9 /CCPOS11
P3.10 /CCPOS12
P3.1 /CC610
P3.2 /COUT610
P3.3 /CC611
P3.4 /COUT611
P3.5 /CC612
COUT62
P3.6 /COUT612
COUT63
T12HR
To DMA
P2.5 /COUT603
T13HR
P3.0 /COUT613
P3.11 /
CCU61_T12HR
P3.12 /
CCU61_T13HR
TC1130_CCU6_imple
Figure 3-12 General Block Diagram of the CCU6 Interfaces
Data Sheet
55
V1.1, 2008-12
TC1130
Functional Description
3.17
Ethernet Controller
The MAC controller implements the IEEE 802.3 and operates either at 100 Mbit/sec or
10 Mbit/sec. Figure 3-13 shows a global view of the Ethernet Controller module with the
module specific interface connections.
Ethernet
Controller
P1.14 / MII_RxER
P1.13 / MII_RxD[3]
P1.12 / MII_RxD[2]
P1.11 / MII_RxD[1]
P1.10 / MII_RxD[0]
P1.9 / MII_COL
DMUR
RB
P1.8 / MII_CRS
Port
Control
P1.7 / MII_RxDV
P1.6 / MII_MDC
FPI
(M/S)
MAC
MII
P1.5 / MII_TxEN
P1.4 / MII_TxER
P1.3 / MII_TxD[3]
DMUT
TB
P1.2 / MII_TxD[2]
P1.1 / MII_TxD[1]
P1.0 / MII_TxD[0]
MII_TxCLK
MII_TxCLK
MII_TDIO
MCB04942mod
Figure 3-13 General Block Diagram of the Ethernet Controller
The Ethernet controller comprises the following functional blocks:
•
•
•
•
•
Media Access Controller (MAC)
Receive Buffer (RB)
Transmit Buffer (TB)
Data Management Unit in Receive Direction (DMUR)
Data Management Unit in Transmit Direction (DMUT)
Data Sheet
56
V1.1, 2008-12
TC1130
Functional Description
RB and TB provide on-chip data buffering whereas DMUR and DMUT perform data
transfer from/to the shared memory.
Two interfaces are provided by the Ethernet Controller module:
• MII interface for connection of Ethernet PHYs via 18 Input/Output lines
• Master/slave FPI bus interface for connection to the on-chip system bus for data
transfer as well as configuration
Features:
•
•
•
•
•
•
•
Media Independent Interface (MII) according to IEEE 802.3
Supports 10 or 100 Mbit/sec MII-based Physical devices
Supports Full Duplex Ethernet
Supports data transfer between Ethernet Controller and COM-DRAM
Supports data transfer between Ethernet Controller and SDRAM via EBU
256 x 32 bit Receive buffer and Transmit buffer each
Supports burst transfers up to 8 x 32 Bytes
Media Access Controller (MAC)
•
•
•
•
•
•
•
•
•
•
•
100/10 Mbit/sec operations
Full IEEE 802.3 compliance
Station management signaling
Large on-chip CAM (Content Addressable Memory)
Full duplex mode
80-byte transmit FIFO
16-byte receive FIFO
PAUSE Operation
Flexible MAC Control Support
Supports Long Packet mode and Short Packet mode
PAD generation
Media Independent Interface (MII)
•
•
•
•
•
•
•
•
•
Media independence
Multi-vendor point of interoperability
Supports connection of MAC layer and Physical (PHY) layer devices
Capable of supporting both 100 Mbit/sec and 10 Mbit/sec data rates
Data and delimiters are synchronous to clock references
Provides independent four bits wide transmit and receive data paths
Supports connection of PHY layer and Station Management (STA) devices
Provides a simple management interface
Capable of driving a limited length of shielded cable
Data Sheet
57
V1.1, 2008-12
TC1130
Functional Description
3.18
System Timer
The STM within the TC1130 is designed for global system timing applications requiring
both high precision and long range. The STM provides the following features:
•
•
•
•
•
•
•
Free-running 56-bit counter
All 56 bits can be read synchronously
Different 32-bit portions of the 56-bit counter can be read synchronously
Flexible interrupt generation on partial STM content compare match
Driven by clock fSTM after reset (default after reset is fSTM = fSYS = 150 MHz)
Counting starts automatically after a reset operation
STM is reset under following reset causes:
– Wake-up reset (PMG_CON.DSRW must be set)
– Software reset (RST_REQ.RRSTM must be set)
– Power-on reset
• STM (and the clock divider) is not reset at watchdog reset and hardware reset
(HDRST = 0)
The STM is an upward counter, running with the system clock frequency fSYS (after reset
fSTM = fSYS). It is enabled per default after reset, and immediately starts counting up.
Other than via reset, it is not possible to affect the contents of the timer during normal
operation of the application; it can only be read, but not written to. Depending on the
implementation of the clock control of the STM, the timer can optionally be disabled or
suspended for power-saving and debugging purposes via a clock control register.
The maximum clock period is 256/fSTM. At fSTM = 150 MHz (maximum), for example, the
STM counts 15.2 years before overflowing. Thus, it is capable of continuously timing the
entire expected product lifetime of a system without overflowing.
Data Sheet
58
V1.1, 2008-12
TC1130
Functional Description
STM Module
31
23
15
0
7
Compare Register CMP0
31
23
15
7
0
Compare Register CMP1
STMIR1
Interrupt
Control
Clock
Control
55
47
39
31
23
15
7
0
56-Bit System Timer
STMIR0
Enable /
Disable
00H
CAP
fSTM
00H
TIM6
TIM5
Address
Decoder
TIM4
TIM3
PORST
TIM2
TIM1
TIM0
MCA04795_mod
Figure 3-14 Block Diagram of the STM Module
Data Sheet
59
V1.1, 2008-12
TC1130
Functional Description
3.19
Watchdog Timer
The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and
recover from software or hardware failure. The WDT helps to abort an accidental
malfunction of the TC1130 in a user-specified time period. When enabled, the WDT will
cause the TC1130 system to be reset if the WDT is not serviced within a
user-programmable time period. The CPU must service the WDT within this time interval
to prevent the WDT from causing a TC1130 system reset. Hence, routine service of the
WDT confirms that the system is functioning properly.
In addition to this standard “Watchdog” function, the WDT incorporates the ENDINIT
feature and monitors its modifications. A system-wide line is connected to the ENDINIT
bit implemented in a WDT control register, serving as an additional write-protection for
critical registers (besides supervisor mode protection). Registers protected via this line
can be modified only when supervisor mode is active and bit ENDINIT = 0.
A further enhancement in the TC1130’s Watchdog Timer is its reset prewarning
operation. Instead of immediately resetting the device upon detection of an error, the
WDT first issues a Non-Maskable Interrupt (NMI) to the CPU before finally resetting the
device at a specified time period later. This gives the CPU a chance to save system state
to memory for later examination of the cause of the malfunction, thus providing an
important aid in debugging.
Features:
• 16-bit Watchdog counter
• Selectable input frequency: fSYS/256 or fSYS/16384
• 16-bit user-definable reload value for normal Watchdog operation, fixed reload value
for time-out and prewarning modes
• Incorporation of the ENDINIT bit and monitoring of its modifications
• Sophisticated password access mechanism with fixed and user-definable password
fields
• Proper access always requires two write accesses. The time between the two
accesses is monitored by the WDT.
• Access Error Detection: Invalid password (during first access) or invalid guard bits
(during second access) trigger the Watchdog reset generation.
• Overflow Error Detection: An overflow of the counter triggers the Watchdog reset
generation.
• Watchdog function can be disabled; access protection and ENDINIT monitor function
remain enabled.
• Double Reset Detection: If a Watchdog induced reset occurs twice without a proper
access to its control register in between, a severe system malfunction is assumed and
the TC1130 is held in reset until a power-on reset or a hardware reset occurs. This
prevents the device from being periodically reset if, for instance, connection to the
Data Sheet
60
V1.1, 2008-12
TC1130
Functional Description
external memory has been lost such that even system initialization could not be
performed.
• Important debugging support is provided through the reset prewarning operation by
first issuing an NMI to the CPU before finally resetting the device after a certain period
of time.
Data Sheet
61
V1.1, 2008-12
TC1130
Functional Description
3.20
System Control Unit
The System Control Unit (SCU) of the TC1130 handles the system control tasks. All of
these system functions are tightly coupled; thus, they are conveniently handled by one
unit, the SCU. The system tasks of the SCU are:
• Clock Control
– Clock generation
– Oscillator and PLL control
• Reset and Boot Control
– Generation of all internal reset signals
– Generation of external hardware and software reset signal
• Power Management Control
– Enabling of several power management modes
• Configuration input sampling
• Ethernet Interrupts
• FPU interrupts
• External Request Unit
• Parity Error Control
• Fault SRAM Fuse Box
• CSCOMB Control
• EBU Pull-Up Control
• NMI Control and Status
• DMA Request Signal Selection
Data Sheet
62
V1.1, 2008-12
TC1130
Functional Description
3.21
Boot Options
The TC1130 booting schemes provides a number of different boot options for the start
of code execution. Table 3-3 shows the boot options available in the TC1130.
Table 3-3
Boot Selections
BRKIN1) TM1) HWCFG Type of Boot
[2:0]
1
1
PC Start Value
(User Entry)
000
Bootstrap Loader
DFFF FFFCH2)
Serial boot from ASC to PMI scratch (D400 0000H)
pad, run loaded program
001
Bootstrap Loader
Serial boot from CAN to PMI scratch
pad, run loaded program
010
Bootstrap Loader
Serial boot from SSC to PMI scratch
pad, run loaded program
011
External memory, EBU as master
DFFF FFFCH2)
(A000 0000H)
100
External memory, EBU as slave
DFFF FFFCH2)
(A000 0000H)
101
Reserved (STOP)
----
110
PMI scratch pad
D400 0000H
111
Reserved (STOP)
DFFF FFFCH2)
1
0
000-111
Reserved (STOP)
DFFF FFFCH2)
0
1
000
Tristate chip
----
001
Go to external emulator space
DFFF FFFCH2)
(DE00 0000H)
010
Reserved (STOP)
----
011
OSC and PLL Bypass
----
100-111
Reserved (STOP)
DFFFFFFCH2)
000-111
Reserved (STOP)
DFFFFFFCH2)
0
0
1)
This input signal is active low.
2)
This is the BootROM entry address; the start address of user program in parentheses.
Data Sheet
63
V1.1, 2008-12
TC1130
Functional Description
3.22
Power Management System
The TC1130 power management system allows software to configure the various
processing units to adjust automatically in order to draw the minimum necessary power
for the application.
There are four power management modes:
•
•
•
•
Run Mode
Idle Mode
Sleep Mode
Deep Sleep Mode
Table 3-4 describes the features of the power management modes.
Table 3-4
Power Management Mode Summary
Mode
Description
Run
The system is fully operational. All clocks and peripherals are enabled,
as determined by software.
Idle
The CPU clock is disabled, waiting for a condition to return it to run mode.
Idle mode can be entered by software when the processor has no active
tasks to perform. All peripherals remain powered and clocked. Processor
memory is accessible to peripherals. A reset, Watchdog Timer event, a
falling edge on the NMI pin, or any enabled interrupt event will return the
system to run mode.
Sleep
The system clock continues to be distributed only to those peripherals
programmed to operate in sleep mode. The other peripheral modules will
be shut down by the suspend signal. Interrupts from operating
peripherals, the Watchdog Timer, a falling edge on the NMI pin, or a reset
event will return the system to run mode. Entering this state requires an
orderly shut-down controlled by the Power Management State Machine.
Deep Sleep
The system clock is shut off; only an external signal will restart the
system. Entering this state requires an orderly shut-down controlled by
the Power Management State Machine (PMSM).
Besides these explicit software-controlled power-saving modes, special attention has
been paid in the TC1130 to automatic power-saving in operating units that are currently
not required or idle. In this case, they are shut off automatically until their operation is
required again.
Data Sheet
64
V1.1, 2008-12
TC1130
Functional Description
3.23
On-Chip Debug Support
The On-Chip Debug Support of the TC1130 consists of the following building blocks:
•
•
•
•
•
•
•
•
•
OCDS L1 module of TriCore™
OCDS L2 interface of TriCore™
OCDS L1 module in the BCU of the FPI Bus
OCDS L1 facilities within the DMA
OCDS L2 interface of DMA
OCDS System Control Unit (OSCU)
Multi Core Break Switch (MCBS)
JTAG based Debug Interface (Cerberus JDI)
Suspend functionality of peripherals
Features:
• TriCore™ L1 OCDS:
– Hardware event generation unit
– Break by DEBUG instruction or break signal
– Full Single-Step support in hardware, possible also with software break
– Access to memory, SFRs, etc. on the fly
• DMA L1 OCDS:
– Output break request on errors
– Suspension of pre-selected channels
• Level 2 trace port with 16 pins that outputs either TriCore™, or DMA trace
• OCDS System Control Unit (Cerberus OSCU)
– Minimum number of pins required (no OCDS enable pin)
– Hardware allows hot attach of a debugger to a running system
– System is secure (can be locked from internal)
• Multi Core Break Switch (Cerberus MCBS):
– TriCore™, DMA, break pins, and BCUs as break sources
– TriCore™ as break targets; other parts can in addition be suspended
– Synchronous stop and restart of the system
– Break to Suspend converter
Figure 3-15 shows a basic block diagram of the building blocks.
Data Sheet
65
V1.1, 2008-12
TC1130
Functional Description
.
OCDS
L1
BCU
TriCoreTM
OCDS
L1
Watchdog
timer
TMS
TCK
TRST
JTAG
Controller
Cerberus
TDO
TDI
OSCU
JDI
Debug
I/F
DMA
FPI
BRKIN
BRKOUT
Periph.n
Break and Suspend Signals
OCDS
L2
Enable, Control and Reset
16
OCDS2[15:0]
DMA L2
Multiplexer
Periph.1
MCBS
Break
Switch
TC1130 OCDS Block Diagram
Figure 3-15 OCDS Support Basic Block Diagram
Data Sheet
66
V1.1, 2008-12
TC1130
Functional Description
3.24
Clock Generation Unit
The Clock Generation Unit (CGU) allows a flexible clock generation for TC1130. The
power consumption is indirectly proportional to the frequency, whereas the performance
of the microcontroller is directly proportional to the frequency. During user program
execution, the frequency can be programmed for an optimal ratio between performance
and power consumption. Therefore, the power consumption can be adapted to the actual
application state.
Features:
The Clock Generation Unit serves several purposes:
• PLL feature for multiplying clock source by different factors
• Direct Drive for direct clock input
• Comfortable state machine for secure switching between basic PLL, direct, or
prescaler operation
• Sleep and Power-down mode support
• USB Clock source and control
The Clock Generation Unit in the TC1130, shown in Figure 3-16, consists of an oscillator
circuit and one Phase-Locked Loop (PLL). The PLL can convert a low-frequency
external clock signal to a high-speed internal clock for maximum performance. The PLL
also has fail-safe logic that detects degenerate external clock behavior such as abnormal
frequency deviations or a total loss of the external clock. It can execute emergency
actions if it looses the lock on the external clock.
In general, the Clock Generation Unit (CGU) is controlled through the System Control
Unit (SCU) module of the TC1130.
XTAL1
Clock Generation Unit
CGU
Oscillator
Circuit
fOSC
Osc.
Run
Detect.
XTAL2
1:1/1:2
Divider
P
Divider
1
>1
Phase
Detect.
fVCO
VCO
MUX
0
fSYS
MUX
fCPU
K:1/K:2
Divider
Divider
f USB
MUX
N
Divider
PLL
P4.0/
USBCLK
Lock
Detector
OGC MOSC OSCR
Register OSC_CON
PDIV OSC
[2:0] DISC
PLL_
LOCK
NDIV
[6:0]
VCO_
SEL[1:0]
VCO_
KDIV SYS
BYPASS [3:0] FSL
Register PLL_CLC
PLL_
BYPASS
USBC
LDIV
USBC
LSEL
Register SCU_CON
System Control Unit
SCU
MCA04940mod
Figure 3-16 Clock Generation Unit Block Diagram
Data Sheet
67
V1.1, 2008-12
TC1130
Functional Description
The oscillator circuit, which is designed to work with an external crystal oscillator or an
external stable clock source, consists of an inverting amplifier with XTAL1 as input and
XTAL2 as output.
Figure 3-17 shows the recommended external oscillator circuitries for both operating
modes, i.e. external crystal mode and external input clock mode.
VDDOSC
VDDOSC3
XTAL1
4 - 25
MHz
VDDOSC
fOSC
External Clock Signal
XTAL1
TC1130
Oscillator
fOSC
TC1130
Oscillator
XTAL2
C1
VDDOSC3
XTAL2
C2
Fundamental
Mode Crystal
VSSOSC
VSSOSC
Figure 3-17 Oscillator Circuitries
When using an external clock signal, it must be connected to XTAL1 and XTAL2 is left
open (unconnected). When supplying the clock signal directly, not using a crystal and
the oscillator, the input frequency can be in the range of 0 - 40 MHz if the PLL is not used,
4 - 40 MHz in case the PLL is used.
When using a crystal, its frequency can be within the range of 4 MHz to 25 MHz. An
external oscillator load circuitry must be used, connected to both pins, XTAL1 and
XTAL2. It consists normally of the two load capacitances, C1 and C2. For some crystals,
a series damp resistor may be necessary. The exact values and related operating range
are dependant on the crystal and have to be determined and optimized together with the
crystal vendor using the negative resistance method. As starting point for the evaluation
and for non-productive systems, the following load capacitor values might be used.
Table 3-5
Load Capacitors Select
Fundamental Mode Crystal Frequency
(approx., MHz)
Load Capacitors
C1, C2 (pF)
4
33
8
18
12
12
16
10
Data Sheet
68
V1.1, 2008-12
TC1130
Functional Description
Table 3-5
Load Capacitors Select (cont’d)
Fundamental Mode Crystal Frequency
(approx., MHz)
Load Capacitors
C1, C2 (pF)
20
10
24
10
A block capacitor between VDDOSC3 and VSSOSC, VDDOSC and VSSOSC is
recommended, too.
Data Sheet
69
V1.1, 2008-12
TC1130
Functional Description
3.25
Power Supply
The TC1130 provides an ingenious power supply concept in order to improve the EMI
behavior as well as to minimize the crosstalk within on-chip modules.
Figure 3-18 shows the TC1130’s power supply concept, where certain logic modules
are individually supplied with power. This concept improves the EMI behavior by
reduction of the noise cross coupling.
V SS (1.5 V)
V DD
DMU
OSC
DMI
PMI
CPU &
Peripheral Logic
GPIO Ports
(P0-P4)
VDDOSC3 (3.3V) VDDOSC (1.5V)
VSS
VSS
VDDP (3.3 V)
VSS
EBU
Ports
MCB04953mod
Figure 3-18 TC1130 Power Supply Concept
Data Sheet
70
V1.1, 2008-12
TC1130
Functional Description
3.26
Power Sequencing
During power-up, reset pin PORST has to be held active until both power supply
voltages have reached at least their minimum values.
During the power-up time (rising of the supply voltages from 0 to their regular operating
values), it must be ensured that the core VDD power supply reaches its operating value
first, and then followed by the GPIO VDDP power supply. During the rising time of the
core voltage, it must be ensured that 0< VDD-VDDP <0.5 V.
During power-down, the core power supply VDD and GPIO power supply VDDP must be
switched off completely until all capacitances are discharged to zero before the next
power-up.
Note: The state of the pins are undefined when only the port voltage VDDP is switched
on.
Data Sheet
71
V1.1, 2008-12
TC1130
Functional Description
3.27
Identification Register Values
Table 3-6
TC1130 Identification Registers
Short Name
Address
Value
SCU_ID
F000 0008H
002C C001H
MANID
F000 0070H
0000 1820H
CHIPID
F000 0074H
0000 8C01H
RTID
F000 0078H
0000 0000H
SBCU_ID
F000 0108H
0000 6A0AH
STM_ID
F000 0208H
0000 C005H
CBS_JDPID
F000 0308H
0000 6307H
GPTU_ID
F000 0608H
0001 C002H
CCU60_ID
F000 2008H
0042 C004H
CCU61_ID
F000 2108H
0042 C004H
DMA_ID
F000 3C08H
001A C011H
CAN_ID
F000 4008H
002B C022H
USB_ID
F00E 2808H
0000 4A00H
SSC0_ID
F010 0108H
0000 4530H
SSC1_ID
F010 0208H
0000 4530H
ASC0_ID
F010 0308H
0000 44E2H
ASC1_ID
F010 0408H
0000 44E2H
ASC2_ID
F010 0508H
0000 44E2H
IIC_ID
F010 0608H
0000 4604H
MLI0_ID
F010 C008H
0025 C004H
MLI1_ID
F010 C108H
0025 C004H
MCHK_ID
F010 C208H
001B C001H
CPS_ID
F7E0 FF08H
0015 C006H
MMU_ID
F7E1 8008H
0009 C002H
CPU_ID
F7E1 FE18H
000A C005H
EBU_ID
F800 0008H
0014 C004H
DMU_ID
F800 0408H
002D C001H
DMI_ID
F87F FC08H
0008 C004H
PMI_ID
F87F FD08H
000B C004H
Data Sheet
72
V1.1, 2008-12
TC1130
Functional Description
Table 3-6
TC1130 Identification Registers (cont’d)
Short Name
Address
Value
LBCU_ID
F87F FE08H
000F C005H
LFI_ID
F87F FF08H
000C C005H
Data Sheet
73
V1.1, 2008-12
TC1130
Electrical Parameters
4
Electrical Parameters
4.1
General Parameters
4.1.1
Parameter Interpretation
The parameters listed in this section represent partly the characteristics of the TC1130
and partly its requirements on the system. To aid interpreting the parameters easily
when evaluating them for design purposes, they are indicated by the abbreviations in the
“Symbol” column:
• CC
These parameters indicate Controller Characteristics, which are distinctive features of
the TC1130 and must be considered for system design.
• SR
These parameters indicate System Requirements, which must be provided by the
microcontroller system in which the TC1130 is included.
Data Sheet
74
V1.1, 2008-12
TC1130
Electrical Parameters
4.1.2
Absolute Maximum Rating
Parameter
Symbol
Limit Values
Unit Notes
min.
max.
TA
TST
TJ
VDD
-40
85
°C
under bias
-65
150
°C
–
-40
125
°C
under bias
-0.5
1.7
V
–
Voltage at 3.3 V power supply
pins with respect to VSS2)
VDDP
-0.5
4.0
V
–
Voltage on any pin with respect
to VSS2)
VIN
-0.5
4.0
V
–
Input current on any pin during
overload condition
IIN
-10
10
mA
–
Absolute sum of all input currents ΣIIN
during overload condition
–
|100|
mA
–
fSYS
fFPI
–
150
MHz –
–
100
MHz –
Ambient temperature
Storage temperature
Junction temperature
Voltage at 1.5 V power supply
pins with respect to VSS1)
CPU & LMB Bus Frequency
FPI Bus Frequency
1)
Applicable for VDD and VDDOSC.
2)
Applicable for VDDP and VDDOSC3. The maximum voltage difference must not exceed 4.0 V in any case (i.e.
Supply Voltage = 4.0 V and Input Voltage = -0.5 V is not allowed).
Data Sheet
75
V1.1, 2008-12
TC1130
Electrical Parameters
4.1.3
Operating Condition
The following operating conditions must be complied with in order to ensure correct
operation of the TC1130. All parameters specified in the following table refer to these
operating conditions, unless otherwise indicated.
Parameter
Digital supply voltage
Digital ground voltage
Digital core supply current
Ambient temperature under
bias
CPU clock
Overload current
Short circuit current
Symbol
min.
max.
Unit Notes
Conditions
VDD
VDDP
VSS
IDD
TA
1.43
1.58
V
–
3.14
3.47
V
–
V
–
525
mA
–
-40
+85
°C
–
fSYS
IOV
–1)
150
MHz –
-1
1
mA
-3
3
-1
1
-3
3
|50|
ISC
Limit Values
0
–
2)3)
duty cycle ≤ 25%
mA
4)
duty cycle ≤ 25%
Absolute sum of overload +
short circuit currents
Σ|IOV| +
|ISC|
–
Inactive device pin current
(VDD = VDDP = 0)
IID
-1
1
mA
–
External load capacitance
CL
–
50
pF
–
ESD strength
–
2000
–
V
Human Body
Model (HBM)
mA
3)
duty cycle ≤ 25%
|100|
1)
The TC1130 uses a static design, so the minimum operation frequency is 0 MHz. However, due to test time
restriction no lower frequency boundary is tested.
2)
Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range (i.e. VOV > VDDP + 0.5 V or VOV < VSS - 0.5 V). The absolute sum of input
overload currents on all digital I/O pins may not exceed 50 mA. The supply voltage must remain within the
specified limits.
3)
Not subject to production test, verified by design/characterization.
4)
Applicable for digital inputs.
Data Sheet
76
V1.1, 2008-12
TC1130
Electrical Parameters
4.2
DC Parameters
4.2.1
Input/Output Characteristics
Table 4-1
Input/Output DC-Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
min.
Unit Test Condition
max.
GPIO pins, Dedicated pins and EBU pins
VIL
VIH
Input low voltage
Input high voltage
Output high voltage
Pull-up current 1)
Pull-down current 2)
Pin Capacitance
4)
-0.3
0.8
V
LvTTL
SR
2.0
VDDP +
0.3
V
LvTTL
0.4
V
IOL = 2mA
–
V
IOH = -2mA
149
μA
−
7.2
μA
–
156
μA
–
15.7
μA
–
±350
nA
VIN = 0V
VIN = 0V
VIN = VDDP
VIN = VDDP
0 < VIN < VDDP
–
10
pF
VOL CC –
VOH CC 2.4
|IPUA| CC −
Output low voltage
Input leakage current
SR
3)
|IPUC| CC
|IPDA| CC
|IPDC| CC
IOZ1 CC
CIO CC
f = 1 MHz
TA = 25 °C
1)
The current is applicable to the pins, for which a pull-up has been specified. Refer to Table 2-1. IPUx refers to
the pull-up current for type x in absolute values.
2)
The current is applicable to the pins, for which a pull-down has been specified. Refer to Table 2-1. IPDx refers
to the pull-down current for type x in absolute values.
3)
Excluded following pins: NMI, TRST, TCK, TDI, TMS, MII_TXCLK, MII_RXCLK, MII_MDIO, ALE,
P2.1,HWCFG0, HWCFG1, HWCFG2, BRKIN, PORST, HDRST.
4)
Not subject to production test, verified by design/characterization.
Data Sheet
77
V1.1, 2008-12
TC1130
Electrical Parameters
4.2.2
Table 4-2
Oscillator Characteristics
Oscillator Pins Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
min.
Unit Test Condition
max.
Oscillator Pins
VILX SR -0.3
Input high voltage at XTAL1 VIHX SR –
0.6
Quartz oscillation peak-peak VPPOSC
Input low voltage at XTAL1
–
V
1)
3
V
1)
–
V
1)
0.1
V
2)
VDDC +
V
2)
μA
–
SR
amplitude at oscillator Input
VILX SR -0.3
Input high voltage at XTAL1 VIHX SR 1.4
Input low voltage at XTAL1
0.3V
Oscillator input current
IOSCIN
1)
Quartz mode: using a quartz crystal
2)
Bypass mode: using an external clock
Data Sheet
–
78
25
V1.1, 2008-12
TC1130
Electrical Parameters
4.2.3
USB Characteristics
4.2.3.1
DC Electrical Characteristics
Table 4-3
USB Electrical Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Conditions
Input Level
Differential Input
Level
VDI
0.2
–
–
V
|V(D+) - V(D-)|
Differential Common
Mode Range
VDCM
0.8
–
2.5
V
Range of Sensitivity
Single Ended
Receiver Threshold
VSE
low <
0.8
–
high >
2.0
V
–
VSOL
VSOH
–
–
< 0.3
V
with 1.5 kΩ to 3.6 V
2.8
3.3
3.6
V
with 15 kΩ to ground
VHIZ
-10
–
10
μA
0 < Vin < 3.3 V
Output Levels
Static Output Low
Static Output High
Leakage Current
Hi_Z State Data Line
Leakage
4.2.3.2
Table 4-4
Full Speed Electrical Characteristics
Full Speed Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
min.
Unit
Test Conditions
typ.
max.
4
–
20
ns
Capacitive load 50 pF
90
100
110
%
Capacitive load 50 pF
1.3
–
2.0
V
Capacitive load 50 pF
Driver Characteristics
Rise/Fall Time
Rise/Fall Time
Matching
tRF
tRFM
Crossover Voltage of VCV
Differential Signals
Data Sheet
79
V1.1, 2008-12
TC1130
Electrical Parameters
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Conditions
Driver Output
Impedance
RDO
28
–
44
Ω
Steady State Driver
Termination
Impedance
RT
1.425
1.5
1.575
kΩ
–
VDDP
VDDP
1.5kΩ
RS
D+
22 Ω
USB
VDDP
Interface
RS
D22 Ω
Figure 4-1
Data Sheet
USB Interface
80
V1.1, 2008-12
TC1130
Electrical Parameters
4.2.4
IIC Characteristics
Each IIC Pin is an open drain output pin with different characteristics than other pins. The
related characteristics are given in the following table.
Table 4-5
IIC Pin Characteristics (Operating Conditions Apply)
Parameter
Output low voltage
Symbol
VOL
CC
Limit Values
min.
max.
–
0.4
Unit
Test
Conditions
V
3 mA sink
current
6 mA sink
current
0.6
Input high voltage1)
VIH
SR
0.7VDDP
VDDP+0.5 V
–
Input low voltage1)
VIL
SR
-0.5
0.3VDDP
–
1)
V
Not subject to production test, verified by design/characterization.
Note: No 5 V IIC interface is supported with these pads. Only voltages lower than 3.63 V
must be applied to these pads.
Note: IIC pins have no pull-up and pull-down devices.
Data Sheet
81
V1.1, 2008-12
TC1130
Electrical Parameters
4.2.5
Table 4-6
Power Supply Current
Power Supply Currents (Operating Conditions apply)
Parameter
Active mode supply
current
Idle mode supply current
Deep sleep mode supply
current
Symbol
IDD
IID
IDS
Limit Values
Unit
Test Conditions
typ. 1)
max.
314
679
mA
Sum of IDDS 2)
153
345
mA
156
322
mA
74
154
mA
66
130
mA
6
15
mA
2
19
mA
2
19
mA
3.6
58
μA
IDD at VDD 3)
IDD at VDDP
Sum of IDDS2)4)
IDD at VDD3)4)
IDD at VDDP4)
Sum of IDDS2)5)
IDD at VDD3)5)
IDD at VDDP5)
1)
Typical values are measured at 25°C, CPU clock at 150 MHz, and nominal supply voltage that is 3.3 V for
VDDP, VDDOSC3 and 1.5 V for VDD, VDDOSC. These currents are measured using a typical application pattern.
The power consumption of modules can increase or decrease using other application programs.
2)
These power supply currents are defined as the sum of all currents at the VDD power supply lines:
VDD + VDDP + VDDOSC3 + VDDOSC
3)
This measurement includes the TriCoreTM and Logic power supply lines.
4)
CPU is in idle state, input clocks to all peripherals are enabled.
5)
Clock generation is disabled at the source.
Data Sheet
82
V1.1, 2008-12
TC1130
Electrical Parameters
4.3
AC Parameters
4.3.1
Power, Pad and Reset Timing
Parameter
Symbol
Min. VDDP voltage to ensure defined pad VDDPPA
CC
states1)
Oscillator start-up time2)
Minimum PORST active time after
power supplies are stable at operating
levels
Limit Values
Unit
min.
max.
0.6
–
V
30
ms
–
ms
tOSCS CC –
tPOA CC 50
HDRST pulse width
tHD
CC
1024
cycles3)
Ports inactive after any reset active2)
tPI
CC
–
fSYS
30
ns
1)
This parameter is valid under assumption that PORST signal is constantly at low level during the power-up/
power-down of the VDDP.
2)
Not subject to production test, verified by design/characterization.
3)
Any HDRST activation is internally prolonged to 1024 FPI bus clock cycles.
Data Sheet
83
V1.1, 2008-12
TC1130
Electrical Parameters
VDDPPA
VDDPPA
VDDP
VDD
VDDPR
toscs
OSC
tPOA
tPOA
PORST
thd
thd
HDRST
Padstate
undefined
2)
1)
2)
Pads
t pi
1) as programmed
1)
2)
Padstate
undefined
2) Tri-state, pull device active
reset_beh
Figure 4-2
Data Sheet
Power and Reset Timing
84
V1.1, 2008-12
TC1130
Electrical Parameters
4.3.2
PLL Parameters
When PLL operation is configured (PLL_CLC.LOCK = 1), the on-chip phase locked loop
is enabled and provides the master clock. The PLL multiplies the input frequency by the
factor F (fMC = fOSC × F) which results from the input divider, the multiplication factor (N
Factor), and the output divider (F = NDIV+1 / (PDIV+1 × KDIV+1)). The PLL circuit
synchronizes the master clock to the input clock. This synchronization is done smoothly,
i.e. the master clock frequency does not change abruptly.
Due to this adaptation to the input clock, the frequency of fMC is constantly adjusted so
it is locked to fOSC. The slight variation causes a jitter of fMC which also affects the
duration of individual TCMs.
The timing listed in the AC Characteristics refers to TCPs. Because fCPU is derived from
fMC, the timing must be calculated using the minimum TCP possible under the respective
circumstances.
The actual minimum value for TCP depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency in order to correspond to the applied input
frequency (crystal or oscillator), the relative deviation for periods of more than one TCP
is lower than for one single TCP (see formula and Figure 4-3).
This is especially important for bus cycles using waitstates and for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baud rates, etc.) the deviation caused by the PLL
jitter is negligible.
The value of the accumulated PLL jitter depends on the number of consecutive VCO
output cycles within the respective timeframe. The VCO output clock is divided by the
output prescaler (K = KDIV+1) to generate the master clock signal fMC. Therefore, the
number of VCO cycles can be represented as K × N, where N is the number of
consecutive fMC cycles (TCM).
For a period of N × TCM, the accumulated PLL jitter is defined by the corresponding
deviation DN:
DN [ns] = ±(1.5 + 6.32 × N / fMC); fMC in [MHz], N = number of consecutive TCMs.
So, for a period of 3 TCMs @ 20 MHz and K = 12: D3 = ±(1.5 + 6.32 × 3 / 20) = 2.448 ns.
This formula is applicable for K × N < 95. For longer periods, the K×N=95 value can be
used. This steady value can be approximated by: DNmax [ns] = ±(1.5 + 600 / (K × fMC)).
Data Sheet
85
V1.1, 2008-12
TC1130
Electrical Parameters
Acc. jitter DN
ns
K=15 K=12 K=10 K=8
K=6
K=5
±8
±7
±6
M
Hz
±5
10
±4
±3
±2
z
MH
20
Hz
40 M
±1
0
5
1
15
10
20
25
N
mcb04413_xc.vsd
Figure 4-3
Approximated Accumulated PLL Jitter
Note: The bold lines indicate the minimum accumulated jitter which can be achieved by
selecting the maximum possible output prescaler factor K.
Different frequency bands can be selected for the VCO, so the operation of the PLL can
be adjusted to a wide range of input and output frequencies:
Table 4-7
VCO Bands for PLL Operation
PLL_CLC.VCOSEL
VCO Frequency Range
Base Frequency Range 1)
00
400 ... 500 MHz
250 ... 320 MHz
01
500 ... 600 MHz
300 ... 400 MHz
10
600 ... 700 MHz
350 ... 480 MHz
11
Reserved
2)
1)
Base Frequency Range is the free running operation frequency of the PLL, when no input clock is available.
2)
This option cannot be used.
Data Sheet
86
V1.1, 2008-12
TC1130
Electrical Parameters
4.3.3
AC Characteristics
(Operating Conditions apply)
2.4V
2.0V
2.0V
test points
0.8V
0.8V
0.4V
AC inputs during testing are driven at 2.4V for a logic “1” and 0.4V for a logic “0”.
Timing measurements are made at VIHmin for a logic “1” and VILmax for a logic “0”.
Figure 4-4
Data Sheet
Input/Output Waveforms for AC Tests
- for GPIO, Dedicated and EBU pins
87
V1.1, 2008-12
TC1130
Electrical Parameters
4.3.4
Input Clock Timing
(Operating Conditions apply)
Parameter
Symbol
Limits
min
Oscillator clock frequency
with PLL
Input clock frequency driving at
XTAL1
with PLL
max
25
MHz
40
MHz
55
%
SR
Input Clock Duty Cycle (t1 /t2)
Input Clock
at XTAL1
fOSC SR 4
fOSCDD
Unit
SR 45
VIHX
0.5 VDD
VILX
t1
t2
tOSCDD
Figure 4-5
Data Sheet
Input Clock Timing
88
V1.1, 2008-12
TC1130
Electrical Parameters
4.3.5
Port Timing
(Operating Conditions apply; CL=50pF)
Parameter
Symbol
Limits
min
Port data valid from TRCLK
1)
up to 120 MHz2)
t1
CC
−
Unit
max
13
ns
1)
Port data is output with respect to the FPI clock. The TRCLK is used as a reference here since the FPI clock
is not available as an external pin and TRCLK is same frequency as CPU clock. Port lines maintain their states
for at least 2 CPU clocks.
2)
120 MHz is verified by design/characterization.
TRCLK
FPI_CLK
t1
Figure 4-6
Data Sheet
New State
Old State
Port Lines
Port Timing
89
V1.1, 2008-12
TC1130
Electrical Parameters
4.3.6
Timing for JTAG Signals
(Operating Conditions apply; CL=50pF)
Parameter
Symbol
Limits
min
tTCK SR
t1 SR
t2 SR
t3 SR
t4 SR
TCK clock period
TCK high time
TCK low time
TCK clock rise time
TCK clock fall time
Unit
max
50
−
ns
10
−
ns
29
−
ns
−
0.4
ns
−
0.4
ns
0.9 VDD
0.5 VDD
0.1 VDD
TCK
t1
t2
t4
t3
tTCK
Figure 4-7
Data Sheet
TCK Clock Timing
90
V1.1, 2008-12
TC1130
Electrical Parameters
Parameter
Symbol
Limits
min
t1
t2
t1
t2
t3
t4
t5
TMS setup to TCK
TMS hold to TCK
TDI setup to TCK
TDI hold to TCK
TDO valid output from TCK
TDO high impedance to valid output from TCK
TDO valid output to high impedance from TCK
Unit
max
SR 7.85
−
ns
SR 3.0
−
ns
SR 10.9
−
ns
SR 3.0
−
ns
CC −
10.7
ns
CC −
23.0
ns
CC −
26.0
ns
TCK
t1
t2
t1
t2
TMS
TDI
t4
t3
t5
TDO
Figure 4-8
Data Sheet
JTAG Timing
91
V1.1, 2008-12
TC1130
Electrical Parameters
4.3.7
Timing for OCDS Trace and Breakpoint Signals
(Operating Conditions apply; CL(TRCLK) = 25 pF, CL = 50 pF)
Parameter
Symbol
Limits
min
t1
t1
t1
t1
BRK_OUT valid from TRCLK
OCDS2_STATUS[4:0] valid from TRCLK
OCDS2_INDIR_PC[7:0] valid from TRCLK
OCDS2_BRKPT[2:0] valid from TRCLK
Unit
max
CC −
5.2
ns
CC 0
5
ns
CC 0
5
ns
CC 0
5
ns
TRCLK
t1
CPU
Trace Signals
Note:
Figure 4-9
Data Sheet
t1
Old State
New State
CPU Trace Signals include BRK_IN, BRK_OUT,
OCDS2_INDIR_PC[7:0] and OCDS_BRKPT[2:0].
OCDS2_STATUS[4:0],
OCDS Trace Signals Timing
92
V1.1, 2008-12
TC1130
Electrical Parameters
4.3.8
EBU Timings
4.3.8.1
SDCLKO Output Clock Timing
(Operating Conditions apply; CL = 50 pF)
Parameter
Limits1)
Symbol
min
SDCLKO period
SDCLKO high time
SDCLKO low time
SDCLKO rise time
SDCLKO fall time
t1
t2
t3
t4
t5
max
Limits2)
min
Unit
max
CC
10
–
8.3
–
ns
CC
3
−
2.5
−
ns
CC
3
−
2.5
−
ns
CC
−
2.5
−
2.5
ns
CC
−
2.5
−
2.5
ns
1)
The parameters are applicable for PC100 SDRAM access and the maximum SDCLKO is up to 100 MHz.
2)
The parameters are applicable for PC133 SDRAM access and the maximum SDCLKO is up to 120 MHz.
4.3.8.2
BFCLKO Output Clock Timing
(Operating Conditions apply; CL = 50 pF)
Parameter
Clock period
BFCLKO high time
BFCLKO low time
BFCLKO rise time
BFCLKO fall time
Limit 1)
Symbol
t1
t2
t3
t4
t5
Unit
min
max
min
max
CC
20
–
16.7
–
ns
CC
6.6
–
7.5
–
ns
CC
6.6
–
7.5
–
ns
CC
–
3.5
–
3.5
ns
CC
–
2.5
–
2.5
ns
1)
The CPU runs at 150 MHz and the Burst Flash runs at divided by 3 clock.
2)
The CPU runs at 120 MHz and the Burst Flash runs at divided by 2 clock.
Data Sheet
Limit 2)
93
V1.1, 2008-12
TC1130
Electrical Parameters
BFCLKO /
SDCLKO
0.5 VDD
t2
t3
t5
t1
Figure 4-10 EBU Clock Output Timing
4.3.8.3
Timing for SDRAM Access Signals
(Operating Conditions apply; CL = 50 pF1))
Parameter
Limits2)
Symbol
Limits3)
Unit
min max min max
t1
t1
t2
t3
t4
t5
CC
10
–
8.3
–
ns
CC
−
8.0
−
6.8
ns
CC
0
−
0.8
−
ns
CC
−
8.0
−
6.8
ns
CC
1.0
−
0.8
−
ns
CC
−
8.0
−
6.8
ns
CSx, RAS, CAS, RD/WR, BC(3:0) output
hold time from SDCLKO
t6
CC
1.0
−
0.8
−
ns
AD(31:0) output valid time from SDCLKO
t7
t8
t9
t10
CC
−
8.0
−
6.8
ns
CC
1.0
−
0.8
−
ns
SR
4.0
−
2.9
−
ns
SR
3.0
−
3.0
−
ns
SDCLKO period
CKE output valid time from SDCLKO
CKE output hold time from SDCLKO
Address output valid time from SDCLKO
Address output hold time from SDCLKO
CSx, RAS, CAS, RD/WR, BC(3:0) output
valid time from SDCLKO
AD(31:0) output hold time from SDCLKO
AD(31:0) input setup time to SDCLKO
AD(31:0) input hold time from SDCLKO
1) If application conditions other than 50 pf capacitive load are used, then the proper correlation factor should be
used for your specific application condition. For design team, the load should be set according to the system
requirement.
2) The parameters are applicable for PC100 SDRAM access and the maximum SDCLKO is up to 100 MHz.
3) The parameters are applicable for PC133 SDRAM access and the maximum SDCLKO is up to 120 MHz.
Data Sheet
94
V1.1, 2008-12
TC1130
Electrical Parameters
Write Access
SDCLKO
t1
CKE
t2
t3
Address
t4
ROW
Column
t5
CSx
t5
t6
t6
RAS
t5
t6
CAS
t5
t6
RD/WR
t5
BC[3:0]
t6
t7
t8
AD[31:0]
D(0)
D(n)
Read Access
SDCLKO
CKE
Address
t1
t3
t4
ROW
t5
CSx
RAS
Column
t5
t6
t6
t5
t6
CAS
RD/WR
BC[3:0]
t5
t6
t10
t9
AD[31:0]
D(0)
D(n)
SDRAM_Timing
Figure 4-11 SDRAM Access Timing
Data Sheet
95
V1.1, 2008-12
TC1130
Electrical Parameters
4.3.8.4
Timing for Burst Flash Access Signals
(Operating Conditions apply; CL = 50 pF)
Parameter
Symbol
Limits
min
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
Address output valid time from BFCLKO
Address output hold time from BFCLKO
CSx output valid time from BFCLKO
RD output valid time from BFCLKO
ADV output valid time from BFCLKO
ADV output hold time from BFCLKO
BAA output valid time from BFCLKO
BAA output hold time from BFCLKO
AD(31:0) input setup time to BFCLKO
AD(31:0) input hold time from BFCLKO
WAIT input setup time to BFCLKO
WAIT input hold time from BFCLKO
Data Sheet
96
Unit
max
CC
−
11.0
ns
CC
10.0
−
ns
CC
−
9.0
ns
CC
−
10.0
ns
CC
−
10.0
ns
CC
3.0
−
ns
CC
−
10.0
ns
CC
3.0
−
ns
SR
5.0
−
ns
SR
3.0
−
ns
SR
5.0
−
ns
SR
3.0
−
ns
V1.1, 2008-12
TC1130
Electrical Parameters
Address
Phase(s)
Command
Command Burst
Delay
Phase(s) Phase(s)
Phase(s)
Burst
Phase(s)
Recovery New Addr.
Phase
Phase(s)
BFCLKO
t2
t1
Address
Address
CSx
t3
ADV
t5
RD
BAA
D[31:0]
t6
t4
t8
t7
D(0)
t9
t10
D(n-1)
t11
t12
WAIT
BF_Timing
Figure 4-12 Burst Flash Access Timing
Note: Output delays are always referenced to BFCLKO. The reference clock for input
characteristics depends on bit BFCON.FDBKEN.
BFCON.FDBKEN = 0: BFCLKO is the input reference clock.
BFCON.FDBKEN = 1: BFCLKI is the input reference clock (EBULMB clock
feedback enabled).
Data Sheet
97
V1.1, 2008-12
TC1130
Electrical Parameters
4.3.8.5
Timing for Demultiplexed Access Signals
(Operating Conditions apply; CL = 50 pF) 1)
Parameter
Symbol
Limits
min
Unit
max
CSx, RD/WR, RD, MR/W, BC(3:0) output valid time
from output clock
t1
CC
−
9
ns
CSx, RD/WR, RD, MR/W, BC(3:0) output hold time
from output clock
t2
CC
0.0
−
ns
Address output valid time from output clock
t3
t4
t7
t8
t9
t10
t11
t12
t13
t14
t16
CC
−
9
ns
CC
0.0
−
ns
SR
12
−
ns
SR
3
−
ns
CC
−
9
ns
CC
0.0
−
ns
SR
1.3
−
ns
SR
3
−
ns
CC
−
8
ns
CC
1.3
−
ns
CC
0
−
ns
Address output hold time from output clock
WAIT input setup time to output clock
WAIT input hold time from output clock
AD(31:0) output valid time from output clock
AD(31:0) output hold time from output clock
AD(31:0) input setup time to output clock
AD(31:0) input hold time from output clock
RMW output valid time from output clock
RMW output hold time from output clock
AD(31:0) output hold time from RD/WR
1) The purpose for characterization of Asynchronous access is to provide the performance of all of the signals to
user. User can decide whether an extra cycle is needed or not based on above parameters to generate signals
with correct timing sequence. It is user’s responsibility to program the correct phase length according to the
memory/peripheral device specification and EBU specification.
Data Sheet
98
V1.1, 2008-12
TC1130
Electrical Parameters
Write Access
Address
Phase(s)
Command
Delay
Phase(s)
(ext.)
Command Delay
Phase(s) (int.)
Command
Phase(s)
Data Hold
Phase(s)
Recovery
Phase
SDCLKO
t 15
t3
Address
t4
Address
t2
t1
CSx
t1
RD/WR
t2
t16
t1
MR/W
t5
t6
CMDELAY
t7
WAIT
t1
t8
t1
BC[3:0]
t2
t2
t9
t10
AD[31:0]
DataOut
Read Access
Address
Phase(s)
Command
Delay
Phase(s)
(ext.)
Command Delay
Phase(s) (int.)
Recovery
Phase
Command
Phase(s)
SDCLKO/
SDCLKI
t15
t3
Address
CSx
t4
Address
t2
t1
t2
t1
RD
t2
MR/W
t5
t6
CMDELAY
t7
WAIT
t1
t8
t1
BC[3:0]
t2
t 11
AD[31:0]
RMW
t 12
DataIn
t 14
t 13
Demux_Timing
Figure 4-13 Demultiplexed Asynchronous Device Access Timing
Data Sheet
99
V1.1, 2008-12
TC1130
Electrical Parameters
4.3.8.6
Timing for Multiplexed Access Signals
(Operating Conditions apply; CL = 50 pF)1)
Parameter
Symbol
Limits
min
Unit
max
ALE, CSx, RD/WR, RD, MR/W, BC(3:0) output valid t1
time from output clock
CC
−
9
ns
ALE, CSx, RD/WR, RD, MR/W, BC(3:0) output hold t2
time from output clock
CC
0.0
−
ns
CC
−
9
ns
CC
0.0
−
ns
SR
1.4
−
ns
SR
3
−
ns
SR
12
−
ns
SR
3
−
ns
CC
−
8
ns
CC
1.3
−
ns
CC
8.5
−
ns
CC
0
−
ns
AD(31:0) output valid time from output clock
AD(31:0) output hold time from output clock
AD(31:0) input setup time to output clock
AD(31:0) input hold time from output clock
WAIT input setup time to output clock
WAIT input hold time from output clock
RMW output valid time from output clock
RMW output hold time from output clock
ALE width
AD(31:0) output hold time from RD/WR
t3
t4
t5
t6
t9
t10
t11
t12
t13
t14
1) The purpose for characterization of Asynchronous access is to provide the performance of all of the signals to
user. User can decide whether an extra cycle is needed or not based on above parameters to generate signals
with correct timing sequence. It is user’s responsibility to program the correct phase length according to the
memory/peripheral device specification and EBU Specification.
Data Sheet
100
V1.1, 2008-12
TC1130
Electrical Parameters
Write Access
Address
Phase(s)
Address Hold
Phase(s)
Command Command
Delay
Delay
Phase(s) Phase(s)
(int.)
(ext.)
Command
Phase(s)
Data Hold
Phase(s)
Recovery
Phase(s)
SDCLKO
t13
t3
AD[31:0]
t4
t3
Data
Address
t4
t2
t1
CSx
t1
RD/WR
t2
t 14
t1
MR/W
t7
t8
CMDELAY
t9
WAIT
t1
t 10
t1
BC[3:0]
t2
t2
Read Access
Address
Phase(s)
SDCLKO/
SDCLKI
Address Hold
Phase(s)
Command
Delay
Phase(s)
(int.)
CSx
Command
Phase(s)
Recovery
Phase(s)
t13
t3
AD[31:0]
Command
Delay
Phase(s)
(ext.)
t5
t4
Address
t6
Data
t2
t1
t1
RD
t2
1
t2
MR/W
t7
t8
CMDELAY
t9
WAIT
t1
t1
BC[3:0]
RMW
t 10
t2
t 12
t 11
Mux_Timing
Figure 4-14 Write Access in Multiplexed Access
Data Sheet
101
V1.1, 2008-12
TC1130
Electrical Parameters
4.3.9
Peripheral Timings
4.3.9.1
Timing for Ethernet Signals
(Operating Conditions apply; CL = 50 pF)
Parameter
Symbol
Limits
min
ETXCLK period (10 Mbit/sec Ethernet)
ETXCLK high time (10 Mbit/sec Ethernet)
ETXCLK low time (10 Mbit/sec Ethernet)
ETXCLK period (100 Mbit/sec Ethernet)
ETXCLK high time (100 Mbit/sec Ethernet)
ETXCLK low time (100 Mbit/sec Ethernet)
ERXCLK period (10 Mbit/sec Ethernet)
ERXCLK high time (10 Mbit/sec Ethernet)
ERXCLK low time (10 Mbit/sec Ethernet)
ERXCLK period (100 Mbit/sec Ethernet)
ERXCLK high time (100 Mbit/sec Ethernet)
ERXCLK low time (100 Mbit/sec Ethernet)
ERXD(3:0) input setup to ERXCLK
ERXD(3:0) input hold from ERXCLK
ERXDV input setup to ERXCLK
ERXDV input hold from ERXCLK
ERXER input setup to ERXCLK
ERXER input hold from ERXCLK
ETXD(3:0) output valid from ETXCLK
ETXEN output valid from ETXCLK
ETXER output valid from ETXCLK
EMDC clock period
EMDC high time
EMDC low time
EMDIO input setup to EMDC (sourced by STA)
Data Sheet
102
t1
t2
t3
t1
t2
t3
t1
t2
t3
t1
t2
t3
t4
t5
t4
t5
t4
t5
t6
t6
t6
t7
t8
t9
t10
Unit
max
SR 400.0
−
ns
SR 140
260
ns
SR 140
260
ns
SR 40.0
−
ns
SR 14
26
ns
SR 14
26
ns
SR 400.0
−
ns
SR 140
260
ns
SR 140
260
ns
SR 40.0
−
ns
SR 14
26
ns
SR 14
26
ns
SR 10.0
−
ns
SR −
10.0
ns
SR 10.0
−
ns
SR −
10.0
ns
SR 10.0
−
ns
SR −
10.0
ns
CC −
25.0
ns
CC −
25.0
ns
CC −
25.0
ns
CC 400.0
−
ns
CC 160
−
ns
CC 160
−
ns
SR 10.0
−
ns
V1.1, 2008-12
TC1130
Electrical Parameters
Parameter
Symbol
Limits
min
t11 SR −
t12 CC −
EMDIO input hold from EMDC (sourced by STA)
EMDIO output valid from EMDC (sourced by PHY)
Unit
max
10.0
ns
300.0
ns
Note: Any other parameters which are not stated here, please refer to ANSI/IEEE Std
802.3, Section 22.3.
t1
ETXCLK
ERXCLK
t2
t3
t4
ERXD(3:0)
ERXDV
ERXER
t5
valid data
t6
ETXD(3:0)
ETXEN
ETXER
valid data
t7
EMDC
t8
t9
t10
EMDIO
(sourced by
STA)
t11
valid data
t12
EMDIO
(sourced by
PHY)
valid data
Figure 4-15 Ethernet Timing
Data Sheet
103
V1.1, 2008-12
TC1130
Electrical Parameters
4.3.9.2
SSC Master Mode Timing
(Operating Conditions apply; CL = 50 pF)
Parameter
Symbol
SCLK clock period
MTSR/SLSOx delay from SCLK
MRST setup to SCLK
MRST hold from SCLK
1)
t0
t1
t2
t3
Limit Values
Unit
min.
max.
CC
2*TSSC 1)
–
ns
CC
0
8
ns
SR
10
–
ns
SR
5
–
ns
TSSCmin = TSYS = 1/fSYS. When fSYS = 120MHz, t0 = 16.7ns
t0
SCLK1)2)
t1
t1
MTSR1)
t2
t3
Data
valid
MRST1)
t1
SLSOx2)
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
2) The transition at SLSOx is based on the following setup: SSOTC.TRAIL = 0
and the first SCLK high pulse is in the first one of a transmission.
SSC_Tmg1
Figure 4-16 SSC Master Mode Timing
Data Sheet
104
V1.1, 2008-12
TC1130
Electrical Parameters
4.3.9.3
MLI Interface Timing
(Operating Conditions apply; CL = 50 pF)
Parameter
Symbol
Limit Values
min.
max.
2*TMLI 1)
–
ns
CC 0
8
ns
SR 4
–
ns
SR 4
–
ns
CC 0
8
ns
t0
TCLK/RCLK clock period
Unit
CC/SR
t5
t6
t7
t8
MLI outputs delay from TCLK
MLI inputs setup to RCLK
MLI inputs hold to RCLK
RREADY output delay from TCLK
1)
TMLImin = TSYS = 1/fSYS. When fSYS = 120MHz, t0 = 16.7ns
t0
0.9 VDDP
0.1 VDDP
TCLKx
t5
t5
TDATAx
TVALIDx
TREADYx
t0
RCLKx
t6
t7
RDATAx
RVALIDx
t8
t8
RREADYx
MLI_Tmg1
Figure 4-17 MLI Interface Timing
Note: The generation of RREADYx is in the input clock domain of the receiver. The
reception of TREADYx is asynchronous to TCLKx.
Data Sheet
105
V1.1, 2008-12
TC1130
Electrical Parameters
4.3.9.4
Timing for USB Transceiver Signals
(Operating Conditions apply; CL = 50 pF)
Parameter
Symbol
Limits
min
tFR CC 4
tFF CC 4
Full speed mode rise time
Full speed mode fall time
D+
D-
90%
Unit
max
20
ns
20
ns
90%
10%
10%
tF
tR
rise_fall_USB.emf
Figure 4-18 AC Testing: Input, Output Waveforms
Data Sheet
106
V1.1, 2008-12
TC1130
Electrical Parameters
4.4
Package Outline
Plastic Package, P-LBGA-208-2 (SMD)
(Low Profile Ball Grid Array Package)
Figure 4-19 P-LBGA-208-2 Package
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
SMD = Surface Mounted Device
Data Sheet
107
V1.1, 2008-12
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG