Ultra-Low Power, 2-Channel, Capacitance Converter for Proximity Sensing AD7150 FEATURES GENERAL DESCRIPTION Ultra-low power 2.7 V to 3.6 V, 100 μA Response time: 10 ms Adaptive environmental compensation 2 independent capacitance input channels Sensor capacitance (CSENS) 0 pF up to 13 pF Sensitivity to 1 fF EMC tested 2 modes of operation Standalone with fixed settings Interfaced to a microcontroller for user-defined settings 2 proximity detection output flags 2-wire serial interface (I2C compatible) Operating temperature −40°C to +85°C 10-lead MSOP package The AD7150 delivers a complete signal processing solution for capacitive proximity sensors, featuring an ultra-low power converter with fast response time. The AD7151 is a singlechannel, lower power alternative to the AD7150. The AD7150 uses Analog Devices, Inc., capacitance-to-digital converter (CDC) technology, which combines features important for interfacing to real sensors, such as high input sensitivity and high tolerance of both input parasitic ground capacitance and leakage current. The integrated adaptive threshold algorithm compensates for any variations in the sensor capacitance due to environmental factors like humidity and temperature or due to changes in the dielectric material over time. By default, the AD7150 operates in standalone mode using the fixed power-up settings and indicates detection on two digital outputs. Alternatively, the AD7150 can be interfaced to a microcontroller via the serial interface, the internal registers can be programmed with user-defined settings, and the data and status can be read from the part. APPLICATIONS Proximity sensing Contactless switching Position detection Level detection The AD7150 operates with a 2.7 V to 3.6 V power supply. It is specified over the temperature range of −40°C to +85°C. FUNCTIONAL BLOCK DIAGRAM VDD CIN1 CSENS1 DIGITAL FILTER Σ-Δ CDC SERIAL INTERFACE SCL SDA EXC1 MUX AD7150 THRESHOLD OUT1 THRESHOLD OUT2 CIN2 EXC2 EXCITATION GND 06517-001 CSENS2 Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. AD7150 TABLE OF CONTENTS Features .............................................................................................. 1 Fixed Threshold Registers ......................................................... 16 Applications....................................................................................... 1 Sensitivity Registers ................................................................... 16 General Description ......................................................................... 1 Timeout Registers....................................................................... 17 Functional Block Diagram .............................................................. 1 Setup Registers............................................................................ 18 Revision History ............................................................................... 2 Configuration Register .............................................................. 19 Specifications..................................................................................... 3 Power-Down Timer Register .................................................... 20 Timing Specifications .................................................................. 4 CAPDAC Registers .................................................................... 20 Absolute Maximum Ratings............................................................ 5 Serial Number Register.............................................................. 20 ESD Caution.................................................................................. 5 Chip ID Register......................................................................... 20 Pin Configuration and Function Descriptions............................. 6 Serial Interface ................................................................................ 21 Typical Performance Characteristics ............................................. 7 Read Operation........................................................................... 21 Architecture and Main Features ................................................... 10 Write Operation.......................................................................... 21 Capacitance-to-Digital Converter............................................ 10 AD7150 Reset ............................................................................. 22 CAPDAC ..................................................................................... 10 General Call ................................................................................ 22 Comparator and Threshold Modes.......................................... 11 Hardware Design Considerations ................................................ 23 Adaptive Threshold.................................................................... 11 Overview ..................................................................................... 23 Data Average ............................................................................... 11 Parasitic Capacitance to Ground.............................................. 23 Sensitivity..................................................................................... 12 Parasitic Resistance to Ground................................................. 23 Hysteresis..................................................................................... 12 Parasitic Parallel Resistance ...................................................... 23 Timeout........................................................................................ 12 Parasitic Serial Resistance ......................................................... 24 AutoCAPDAC Adjustment ....................................................... 13 Input Overvoltage Protection ................................................... 24 Power-Down Timer ................................................................... 13 Input EMC Protection ............................................................... 24 Power Supply Monitor ............................................................... 13 Power Supply Decoupling and Filtering.................................. 24 Register Descriptions ..................................................................... 14 Application Examples ................................................................ 25 Status Register ............................................................................. 15 Outline Dimensions ....................................................................... 26 Data Registers ............................................................................. 16 Ordering Guide .......................................................................... 26 Average Registers........................................................................ 16 REVISION HISTORY 11/07—Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD7150 SPECIFICATIONS VDD = 2.7 V to 3.6 V; GND = 0 V; –40°C to +85°C, unless otherwise noted. Table 1. Parameter CAPACITIVE INPUT Conversion Input Range CIN to EXC 2 Min Typ 3.2 1.6 0.8 0.4 4 2 1 0.5 2.0 1.6 1.4 1.0 Resolution 3 Allowed Capacitance CIN to GND3 Allowed Resistance CIN to GND3 Allowed Serial Resistance3 Gain Error Gain Deviation over Temperature3 Gain Matching Between Ranges3 Offset Error3 Offset Deviation over Temperature3 Integral Nonlinearity (INL)3 Channel-to-Channel Isolation3 Power Supply Rejection3 CAPDAC2 Full Range Resolution (LSB)3 Differential Nonlinearity (DNL)3 AutoDAC Increment/Decrement3 EXCITATION Voltage Frequency Allowed Capacitance EXC to GND3 Allowed Resistance EXC to GND3 LOGIC OUTPUTS (OUT1, OUT2) Output Low Voltage (VOL) Output High Voltage (VOH) SERIAL INTERFACE INPUTS (SCL, SDA) Input High Voltage (VIH) Input Low Voltage (VIL) Input Leakage Current Input Pin Capacitance OPEN-DRAIN OUTPUT (SDA) Output Low Voltage (VOL) Output High Leakage Current (IOH) POWER SUPPLY MONITOR VDD Threshold Voltage Max 100 10 125 +20 −20 0.5 −2 +2 50 5 0.1 60 4 10 12.5 200 0.25 75 25 30.9 ±VDD/2 32 32.8 300 1 0.4 VDD – 0.6 1.5 Unit 1 Test Conditions/Comments pF pF pF pF fF fF fF fF pF MΩ kΩ % % % fF fF % dB fF/V 4 pF input range 2 pF input range 1 pF input range 0.5 pF input range 4 pF input range 2 pF input range 1 pF input range 0.5 pF input range pF fF LSB % of CIN Range V kHz pF MΩ V V 0.8 ±5 V V μA pF 0.4 V 0.1 5 μA 2.45 2.65 V ±0.1 6 Rev. 0 | Page 3 of 28 CIN and EXC pins disconnected CIN and EXC pins disconnected ISINK = −4 mA ISOURCE = 4 mA ISINK = −6.0 mA VOUT = VDD AD7150 Parameter POWER REQUIREMENTS VDD-to-GND Voltage IDD Current 4 IDD Current Power-Down Mode4 Min Typ Max Unit 1 Test Conditions/Comments 3.6 120 5 10 V μA μA μA VDD = 3.3 V, nominal 100 1 3 2.7 Temperature ≤ 25°C Temperature = 85°C 1 Capacitance units: one picofarad (1 pF) = 1 × 10−12 farad (F); one femtofarad (1 fF) = 10−15 farad (F). The CAPDAC can be used to shift (offset) the input range. The total capacitance of the sensor can therefore be up to the sum of the CAPDAC value and the conversion input range. With the autoCAPDAC feature, the CAPDAC is adjusted automatically when the CDC input value is lower than 25% or higher than 75% of the CDC nominal input range. 3 Specification is not production tested but is supported by characterization data at initial product release. 4 Digital inputs equal to VDD or GND. 2 TIMING SPECIFICATIONS VDD = 2.7 V to 3.6 V; GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = VDD; –40°C to +85°C, unless otherwise noted. Table 2. Parameter CONVERTER Conversion Time Wake-Up Time from Power-Down Mode 1, 2 Power-Up Time1, 3 Reset Time1, 4 SERIAL INTERFACE 5, 6 SCL Frequency SCL High Pulse Width, tHIGH SCL Low Pulse Width, tLOW SCL, SDA Rise Time, tR SCL, SDA Fall Time, tF Hold Time (Start Condition), tHD;STA Setup Time (Start Condition), tSU;STA Data Setup Time, tSU;DAT Setup Time (Stop Condition), tSU;STO Data Hold Time (Master), tHD;DAT Bus-Free Time (Between Stop and Start Condition), tBUF Min Typ Max Unit Test Conditions/Comments 10 ms ms ms ms Both channels, 5 ms per channel. 400 kHz μs μs μs μs μs μs μs μs ns μs 0.15 2 2 See Figure 2. 0 0.6 1.3 0.3 0.3 0.6 0.6 0.1 0.6 10 1.3 After this period, the first clock is generated. Relevant for repeated start condition. 1 Specification is not production tested but is supported by characterization data at initial product release. Wake-up time is the maximum delay between the last SCL edge writing the configuration register and the start of conversion. 3 Power-up time is the maximum delay between the VDD crossing the minimum level (2.7 V) and either the start of conversion or when ready to receive a serial interface command. 4 Reset time is the maximum delay between the last SCL edge writing the reset command and either the start of conversion or when ready to receive a serial interface command. 5 Sample tested during initial release to ensure compliance. 6 All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Output load = 10 pF. 2 tLOW tR tF tHD;STA SCL tHD;STA tHD;DAT tHIGH tSU;STA tSU;DAT tSU;STO tBUF P S S Figure 2. Serial Interface Timing Diagram Rev. 0 | Page 4 of 28 P 06517-002 SDA AD7150 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Positive Supply Voltage VDD to GND Voltage on Any Input or Output to GND ESD Rating HBM (ESD Association Human Body Model, S5.1) ESD Rating FICDM (Field-Inducted Charged Device Model) Operating Temperature Range Storage Temperature Range Maximum Junction Temperature MSOP Package θJA, Thermal Impedance-to-Air θJC, Thermal Impedance-to-Case Reflow Soldering (Pb-Free) Peak Temperature Time at Peak Temperature Rating −0.3 V to +3.9 V –0.3 V to VDD + 0.3 V 4 kV 1 kV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION –40°C to +85°C –65°C to +150°C 150°C 206°C/W 44°C/W 260(+0/−5)°C 10 sec to 40 sec Rev. 0 | Page 5 of 28 AD7150 GND 1 10 SDA VDD 2 AD7150 9 SCL TOP VIEW (Not to Scale) 8 OUT2 7 OUT1 6 EXC1 CIN2 3 CIN1 4 EXC2 5 06517-003 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 Mnemonic GND VDD 3 CIN2 4 CIN1 5 EXC2 6 EXC1 7 8 9 OUT1 OUT2 SCL 10 SDA Description Ground Pin. Power Supply Voltage. This pin should be decoupled to GND using a low impedance capacitor, for example, 0.1 μF X7R multilayer ceramic. CDC Capacitive Input Channel 2. The measured capacitance (sensor) is connected between the EXC2 pin and the CIN2 pin. If not used, this pin can be left open circuit or connected to GND. CDC Capacitive Input Channel 1. The measured capacitance (sensor) is connected between the EXC1 pin and the CIN1 pin. If not used, this pin can be left open circuit or connected to GND. CDC Excitation Output Channel 2. The measured capacitance is connected between the EXC2 pin and the CIN2 pin. If not used, this pin should be left as an open circuit. CDC Excitation Output Channel 1. The measured capacitance is connected between the EXC1 pin and the CIN1 pin. If not used, this pin should be left as an open circuit. Logic Output Channel 1. A high level on this output indicates proximity detected on CIN1. Logic Output Channel 2. A high level on this output indicates proximity detected on CIN2. Serial Interface Clock Input. Connects to the master clock line. Requires a pull-up resistor if not provided elsewhere in the system. Serial Interface Bidirectional Data. Connects to the master data line. Requires a pull-up resistor if not provided elsewhere in the system. Rev. 0 | Page 6 of 28 AD7150 300 2 200 1 OFFSET ERROR (fF) 100 –1 0 0 50 100 150 200 250 300 CAPACITANCE CIN TO GND (pF) –2 06517-004 –100 0 0 50 100 150 200 250 300 CAPACITANCE EXC TO GND (pF) Figure 4. Capacitance Input Offset Error vs. Capacitance CIN to GND, VDD = 3.3 V, EXC Pin Open Circuit 06517-007 OFFSET ERROR (fF) TYPICAL PERFORMANCE CHARACTERISTICS Figure 7. Capacitance Input Offset Error vs. Capacitance EXC to GND, VDD = 3.3 V, CIN Pin Open Circuit 2 0.10 0 GAIN ERROR (%FS) GAIN ERROR (%FS) 0.05 –2 –4 0 –0.05 0 50 100 150 200 250 300 CAPACITANCE CIN TO GND (pF) –0.10 06517-005 –8 0 50 100 150 200 250 300 CAPACITANCE EXC TO GND (pF) Figure 5. Capacitance Input Gain Error vs. Capacitance CIN to GND, VDD = 3.3 V, CIN to EXC = 2 pF 06517-008 –6 Figure 8. Capacitance Input Gain Error vs. Capacitance EXC to GND, VDD = 3.3 V, CIN to EXC = 2 pF 2 0.10 0 GAIN ERROR (%FS) GAIN ERROR (%FS) 0.05 –2 –4 0 –0.05 0 50 100 150 200 250 300 CAPACITANCE CIN TO GND (pF) Figure 6 .Capacitance Input Gain Error vs. Capacitance CIN to GND, VDD = 3.3 V, CIN to EXC = 10 pF –0.10 0 50 100 150 200 250 300 CAPACITANCE EXC TO GND (pF) Figure 9. Capacitance Input Gain Error vs. Capacitance EXC to GND, VDD = 3.3 V, CIN to EXC = 10 pF Rev. 0 | Page 7 of 28 06517-009 –8 06517-006 –6 500 0.50 250 0.25 GAIN ERROR (%FS) 0 –250 –0.25 1 10 1000 100 –0.50 06517-010 –500 0 RESISTANCE CIN TO GND (MΩ) 0 2 4 6 8 10 RESISTANCE EXC TO GND (MΩ) Figure 10. Capacitance Input Offset Error vs. Resistance CIN to GND, VDD = 3.3 V, EXC Pin Open Circuit 06517-013 OFFSET ERROR (fF) AD7150 Figure 13. Capacitance Input Gain Error vs. Resistance EXC to GND, VDD = 3.3 V, CIN to EXC = 2 pF 10 2 0 GAIN ERROR (%FS) GAIN ERROR (%FS) 5 0 –2 –4 –5 1 10 1000 100 –8 06517-011 RESISTANCE CIN TO GND (MΩ) 100 150 200 250 Figure 14. Capacitance Input Gain Error vs. Serial Resistance, VDD = 3.3 V, CIN to EXC = 2 pF 10 10 5 5 GAIN ERROR (%FS) OFFSET ERROR (fF) 50 SERIAL RESISTANCE (kΩ) Figure 11. Capacitance Input Gain Error vs. Resistance CIN to GND, VDD = 3.3 V, CIN to EXC = 2 pF 0 0 –5 0 2 4 6 RESISTANCE EXC TO GND (MΩ) 8 10 06517-012 –5 –10 0 Figure 12. Capacitance Input Offset Error vs. Resistance EXC to GND, VDD = 3.3 V, CIN Pin Open Circuit –10 1 10 100 1000 PARALLEL RESISTANCE (MΩ) Figure 15. Capacitance Input Gain Error vs. Parallel Resistance, VDD = 3.3 V, CIN to EXC = 2 pF Rev. 0 | Page 8 of 28 06517-015 –10 06517-014 –6 AD7150 4 0 –25 0 25 50 75 100 TEMPERATURE (°C) 0 –1 –2 2.7 0.1 –20 GAIN (dB) GAIN ERROR (%FS) 0 0 –0.1 –40 –60 0 25 50 75 100 –80 06517-017 –25 TEMPERATURE (°C) 0 1 2 3 4 5 INPUT SIGNAL FREQUENCY (kHz) Figure 17. Capacitance Input Gain Error vs. Temperature, VDD = 3.3 V, CIN to EXC = 2 pF Figure 20. Capacitance Channel Frequency Response 0.50 1 0.25 CAPDAC DNL (LSB) 2 0 –1 0 –0.25 –25 0 25 50 75 TEMPERATURE (°C) 100 06517-018 EXC FREQUENCY ERROR (%) 3.6 Figure 19. EXC Frequency Error vs. VDD 0.2 –2 –50 3.3 VDD (V) Figure 16. Capacitance Input Offset Error vs. Temperature, VDD = 3.3 V, CIN and EXC Pins Open Circuit –0.2 –50 3.0 06517-020 –4 –50 06517-016 –2 1 Figure 18. EXC Frequency Error vs. Temperature, VDD = 3.3 V –0.50 0 16 32 48 CAPDAC CODE Figure 21. CAPDAC Differential Nonlinearity (DNL), VDD = 3.3 V Rev. 0 | Page 9 of 28 64 06517-021 OFFSET ERROR (fF) 2 06517-019 EXC FREQUENCY ERROR (%) 2 AD7150 ARCHITECTURE AND MAIN FEATURES 3.3V VDD AD7150 CIN1 CLOCK GENERATOR POWER-DOWN TIMER POWER SUPPLY MONITOR Σ-Δ CDC DIGITAL FILTER SERIAL INTERFACE CAPDAC THRESHOLD SCL CX1 SDA PROGRAMMING INTERFACE EXC1 MUX CX2 EXC2 OUT1 DIGITAL OUTPUTS EXCITATION OUT2 THRESHOLD 06517-030 CIN2 GND Figure 22. AD7150 Block Diagram The AD7150 core is a high performance capacitance-to-digital converter (CDC) that allows the part to be interfaced directly to a capacitive sensor. CAPACITANCE TO DIGITAL CONVERTER (CDC) CLOCK GENERATOR The comparators compare the CDC result with thresholds, either fixed or dynamically adjusted by the on-chip adaptive threshold algorithm engine. Thus, the outputs indicate a defined change in the input sensor capacitance. CAPACITANCE-TO-DIGITAL CONVERTER Figure 23 shows the CDC simplified functional diagram. The converter consists of a second-order sigma delta (Σ-Δ), charge balancing modulator and a third-order digital filter. The measured capacitance CX is connected between an excitation source and the Σ-Δ modulator input. The excitation signal is applied on the CX during the conversion, and the modulator continuously samples the charge going through the CX. The digital filter processes the modulator output, which is a stream of 0s and 1s containing the information in 0 and 1 density. The data is processed by the adaptive threshold engine and output comparators; the data can be also read through the serial interface. The AD7150 is designed for floating capacitive sensors. Therefore, both CX plates have to be isolated from ground or any other fixed potential node in the system. The AD7150 features slew rate limiting on the excitation voltage output, which decreases the energy of higher harmonics on the excitation signal and dramatically improves the system electromagnetic compatibility (EMC). Σ-Δ MODULATOR 0x000 TO 0xFFF DATA DIGITAL FILTER CX 0pF TO 4pF EXCITATION 06517-031 EXC Figure 23. CDC Simplified Block Diagram CAPDAC The AD7150 CDC core maximum full-scale input range is 4 pF. However, the part can accept a higher capacitance on the input, and the offset (nonchanging component) capacitance of up to 10 pF can be balanced by a programmable on-chip CAPDAC. CAPDAC 10pF CIN 0x000 TO 0xFFF DATA 0pF TO 4pF CX 10pF TO 14pF EXC 06517-032 The AD7150 also integrates an excitation source and CAPDAC for the capacitive inputs, an input multiplexer, a complete clock generator, a power-down timer, a power supply monitor, control logic, and an I2C®-compatible serial interface for configuring the part and accessing the internal CDC data and status, if required in the system (see Figure 22). CIN Figure 24. Using CAPDAC The CAPDAC can be understood as a negative capacitance connected internally to the CIN pin. The CAPDAC has a 6-bit resolution and a monotonic transfer function. Figure 24 shows how to use the CAPDAC to shift the CDC 4 pF input range to measure capacitance between 10 pF and 14 pF. Rev. 0 | Page 10 of 28 AD7150 INPUT OUTSIDE THRESHOLD WINDOW COMPARATOR AND THRESHOLD MODES POSITIVE THRESHOLD The AD7150 comparators and their thresholds can be programmed to operate in several different modes. In an adaptive mode, the threshold is dynamically adjusted and the comparator output indicates fast changes and ignores slow changes in the input (sensor) capacitance. Alternatively, the threshold can be programmed as a constant (fixed) value, and the output then indicates any change in the input capacitance that crosses the defined fixed threshold. INPUT CAPACITANCE NEGATIVE THRESHOLD OUTPUT TIME Figure 28. Out-Window (Adaptive) Threshold Mode The AD7150 logic output (active high) indicates either a positive or a negative change in the input capacitance, in both adaptive and fixed threshold modes (see Figure 25 and Figure 26). POSITIVE CHANGE POSITIVE THRESHOLD INPUT CAPACITANCE OUTPUT ACTIVE ADAPTIVE THRESHOLD In an adaptive mode, the thresholds are dynamically adjusted, ensuring indication of fast changes (for example, an object moving close to a capacitive proximity sensor) and eliminating slow changes in the input (sensor) capacitance, usually caused by environment changes such as humidity or temperature or changes in the sensor dielectric material over time (see Figure 29). FAST CHANGE 06517-033 OUTPUT TIME SLOW CHANGE INPUT CAPACITANCE THRESHOLD Figure 25. Positive Threshold Mode Indicates Positive Change in Input Capacitance OUTPUT TIME INPUT CAPACITANCE 06517-037 OUTPUT ACTIVE NEGATIVE CHANGE Figure 29. Adaptive Threshold Indicates Fast Changes and Eliminates Slow Changes in Input Capacitance NEGATIVE THRESHOLD DATA AVERAGE OUTPUT ACTIVE The adaptive threshold algorithm is based on an average calculated from previous CDC output data. The response of the average to an input capacitance step change (more exactly, response to the change in the CDC output data) is an exponential settling curve, which can be characterized by the following equation: TIME Figure 26. Negative Threshold Mode Indicates Negative Change in Input Capacitance Additionally, for the adaptive mode only, the comparators can work as window comparators, indicating input either inside or outside a selected sensitivity band (see Figure 27 and Figure 28). INPUT INSIDE THRESHOLD WINDOW INPUT CAPACITANCE NEGATIVE THRESHOLD OUTPUT TIME Figure 27. In-Window (Adaptive) Threshold Mode 06517-035 OUTPUT ACTIVE Average ( N ) = Average (0) + Change (1 − e N / TimeConst ) where: Average(N) is the value of average N complete CDC conversion cycles after a step change on the input. Average(0) is the value before the step change. TimeConst can be selected in the range between 2 and 65,536, in steps of power of 2, by programming the ThrSettling bits in the setup registers. See Figure 30 and the Register Descriptions section. INPUT CAPACITANCE (CDC DATA) CHANGE DATA AVERAGE RESPONSE TIME Figure 30. Data Average Response to Data Step Change Rev. 0 | Page 11 of 28 06517-038 06517-034 OUTPUT POSITIVE THRESHOLD 06517-036 OUTPUT ACTIVE AD7150 SENSITIVITY In adaptive threshold mode, the output comparator threshold is set as a defined distance (sensitivity) above the data average, below the data average, or both, depending on the selected threshold mode of operation (see Figure 31). The sensitivity value is programmable in the range 0 to 255 LSBs of the 12-bit CDC converter (see the Register Descriptions section). The timeout can be set independently for approaching (for change in data toward the threshold) and for receding (for change in data away from the threshold). See Figure 34, Figure 35, and the Register Descriptions section. DATA AVERAGE + SENSITIVITY LARGE CHANGE IN DATA DATA AVERAGE DATA AVERAGE – SENSITIVITY DATA POSITIVE THRESHOLD SENSITIVITY TIME TIMEOUT Figure 33. Threshold Timeout After a Large Change in CDC Data OUTPUT ACTIVE 06517-039 TIME TIMEOUT APPROACHING INPUT CAPACITANCE Figure 31. Threshold Sensitivity THRESHOLD HYSTERESIS DATA AVERAGE In adaptive threshold mode, the comparator features hysteresis. The hysteresis is fixed to one-fourth of the threshold sensitivity and can be programmed on or off. The comparator does not have hysteresis in the fixed threshold mode. OUTPUT ACTIVE OUTPUT TIME DATA 06517-042 NEGATIVE THRESHOLD 06517-041 SENSITIVITY DATA AVERAGE Figure 34. Approaching Timeout in Negative Threshold Mode Shortens False Output Trigger POSITIVE THRESHOLD HYSTERSIS TIMEOUT RECEDING DATA AVERAGE LARGE CHANGE TIME INPUT CAPACITANCE Figure 32. Threshold Hysteresis THRESHOLD TIMEOUT OUTPUT ACTIVE In the case of a large, long change in the capacitive input, when the data average adapting to a new condition may take too long, a timeout can be set. The timeout becomes active (counting) when the CDC data goes outside the band of data average ± sensitivity. When the timeout elapses (a defined number of CDC conversions is counted), the data average (and thus the thresholds), is forced to follow the new CDC data value immediately (see Figure 33). Rev. 0 | Page 12 of 28 OUTPUT TIME Figure 35. Positive Timeout in Negative Threshold Mode Shortens Period of Missing Output Trigger 06517-043 OUTPUT 06517-040 OUTPUT ACTIVE AD7150 AUTOCAPDAC ADJUSTMENT POWER SUPPLY MONITOR In adaptive threshold mode, the part can dynamically adjust the CAPDAC to keep the CDC in an optimal operating capacitive range. When the AutoDAC function is enabled, the CAPDAC value is automatically incremented when the data average exceeds three-fourths of the CDC full range, and the CAPDAC value is decremented when the data average goes below onefourth of the CDC full range. The AutoDAC increment or decrement step depends on the selected CDC capacitive input range. See the Setup Registers section. When the AD7150 VDD power supply voltage drops below a defined level needed for correct CDC operation, the on-chip power supply monitor stops the adaptive threshold logic and holds it in reset. After the VDD reaches the required level, the threshold logic is released, and the data average is reset to the value of the first conversion finished at the correct power supply voltage. POWER-DOWN TIMER In power sensitive applications, the AD7150 can be set to automatically enter power-down mode after a programmed period of time in which the outputs have not been activated. The AD7150 can be then returned to a normal operational mode either via the serial interface or by the power supply off/on sequence. This feature prevents the adaptive threshold from being set incorrectly after a very slow rise of the VDD voltage or from being corrupted by accidental drops in the VDD voltage. The other AD7150 functions continue working below the power supply monitor threshold, down to approximately 1.0V..1.8V, the exact level depending on the manufacturing process variation. In the region of the low VDD voltage, the part is still accessible via the serial interface and continues conversion. However, the conversion results may be incorrect and, therefore, the data should not be considered valid if the part operates below the power supply monitor threshold. The status of the power supply monitor can be determined by reading the PwrDown bit in the AD7150 status register. Rev. 0 | Page 13 of 28 AD7150 REGISTER DESCRIPTIONS Table 5. Register Summary Register Pointer (Dec) (Hex) R/W Bit 7 Bit 6 Bit 5 PwrDown DacStep2 OUT2 0 1 0 Bit 4 Bit 3 Default Value OUT1 DacStep1 Status 0 0x00 R Ch1 Data High 1 0x01 R 0x00 Ch1 Data Low 2 0x02 R 0x00 Ch2 Data High 3 0x03 R 0x00 Ch2 Data Low 4 0x04 R 0x00 Ch1 Average High 5 0x05 R 0x00 Ch1 Average Low 6 0x06 R 0x00 Ch2 Average High 7 0x07 R 0x00 Ch2 Average Low 8 0x08 R 0x00 Ch1 Sensitivity Ch1 Threshold High 9 0x09 R/W Ch1 Timeout Ch1 Threshold Low 10 0x0A R/W Ch1 Setup 11 0x0B R/W Ch2 Sensitivity Ch2 Threshold High 12 0x0C R/W Ch2 Timeout Ch2 Threshold Low 13 0x0D R/W Ch2 Setup 14 0x0E R/W Configuration 15 0x0F R/W Power-Down Timer 16 0x10 R/W Ch1 CAPDAC 17 0x11 R/W Ch2 CAPDAC 18 0x12 R/W Serial Number 3 19 0x13 R Serial Number – Byte 3 (MSB) Serial Number 2 20 0x14 R Serial Number – Byte 2 Serial Number 1 21 0x15 R Serial Number – Byte 1 Serial Number 0 22 0x16 R Serial Number – Byte 0 (LSB) Chip ID 23 0x17 R Chip Identification Code 1 0 Bit 2 Bit 1 Bit 0 C1/C2 RDY2 RDY1 0 1 1 Ch1 Sensitivity (in adaptive threshold mode)/Threshold High Byte (in fixed threshold mode) 0x08 Ch1 Timeout (in adaptive threshold mode)/Threshold Low Byte (in fixed threshold mode) 0x86 RngH1 RngL1 – ThrSettling1 (4-bit value) Hyst1 0 0 0 0 0x0B Ch2 Sensitivity (in adaptive threshold mode)/Threshold High Byte (in fixed threshold mode) 0x08 Ch2 Timeout (in adaptive threshold mode)/Threshold Low Byte (in fixed threshold mode) 0x86 RngH2 RngL2 – ThrSettling2 (4-bit value) Hyst2 0 ThrFixed 0 – 0 DacEn1 1 DacEn2 1 0 ThrMD1 0 – 0 DacAuto1 1 DacAuto2 1 0 ThrMD0 0 0 0x0B EnCh1 EnCh2 MD2 MD1 1 1 0 0 Power-Down Timeout (6-bit value) 0x00 DacValue1 (6-bit value) 0x00 DacValue2 (6-bit value) 0x00 Rev. 0 | Page 14 of 28 MD0 1 AD7150 STATUS REGISTER Address Pointer 0x00 8 Bits, Read-Only, Default Value 0x53 Before Conversion, 0x54 After Conversion The status register indicates the status of the part. The register can be read via the 2-wire serial interface to query the status of the outputs, check the CDC finished conversion, and check whether the CAPDAC has been changed by the autoCAPDAC function. Table 6. Status Register Bit Map Bit Mnemonic Default Bit 7 PwrDown 0 Bit 6 DacStep2 1 Bit 5 OUT2 0 Bit 4 DacStep1 1 Bit 3 OUT1 0 Bit 2 C1/C2 0 Bit 1 RDY2 1 Bit 0 RDY1 1 Table 7. Status Register Bit Descriptions Bit 7 Mnemonic PwrDown 6 DacStep2 5 OUT2 4 DacStep1 3 OUT1 2 C1/C2 1 RDY2 0 RDY1 Description PwrDown = 1 indicates that the part is in a power-down mode or that the part VDD is below the power supply monitor threshold voltage. DacStep2 = 0 indicates that the Ch2 CAPDAC value was changed after the last CDC conversion as part of the AutoDac function. The bit value is updated after each finished CDC conversion on this channel. OUT2 = 1 indicates that the Ch2 data (CIN2 capacitance) crossed the threshold, according to the selected comparator mode of operation. The bit value is updated after each finished CDC conversion on this channel. DacStep1 = 0 indicates that the Ch1 CAPDAC value was changed during the last conversion as part of the AutoDac function. The bit value is updated after each finished CDC conversion on this channel. OUT1 = 1 indicates that the Ch1 data (CIN1 capacitance) crossed the threshold, according to the selected comparator mode of operation. The bit value is updated after each finished CDC conversion on this channel. The C1/C2 = 0 indicates that the last finished CDC conversion was on Channel 1. The C1/C2 = 1 indicates that the last finished CDC conversion was on Channel 2. RDY2 = 0 indicates a finished CDC conversion on Ch2. The bit is reset back to 1 when the Ch2 data register is read via the serial interface or after the part reset or power-up. RDY1= 0 indicates a finished CDC conversion on Ch1. The bit is reset back to 1 when the Ch1 data register is read via serial interface or after the part reset or power-up. Rev. 0 | Page 15 of 28 AD7150 DATA REGISTERS AVERAGE REGISTERS Ch1 Address Pointer 0x01, 0x02 Ch2 Address Pointer 0x03,0x04 16 Bits, Read-Only, Default Value 0x0000 Ch1 Address Pointer 0x05, 0x06 Ch2 Address Pointer 0x07,0x08 16 Bits, Read-Only, Default Value 0x0000 Data from the last complete capacitance-to-digital conversion reflects the capacitance on the input. Only the 12 MSBs (most significant bits) of the data registers are used for the CDC result. The 4 LSBs (least significant bits) are always 0, as shown in Figure 36. These registers show the average calculated from the previous CDC data. The 12-bit CDC result corresponds to the 12 MSBs of the average register. DATA LOW LSB 06517-044 12-BIT CDC RESULT 0 Figure 36. CDC Data Register The nominal AD7150 CDC transfer function (an ideal transfer function excluding offset and/or gain error) maps the input capacitance between zero scale and full scale to output data codes between 0x3000 and 0xCFF0 only (see Table 8). Table 8. AD7150 Capacitance-to-Data Mapping Data 0x0000 0x3000 0x8000 0xCFF0 0xFFF0 Input Capacitance Not valid, underrange Zero-scale (0 pF) Mid-scale (+1 pF) Full-scale (+2 pF) Not valid, overrange Ch1 Address Pointer 0x09, 0x0A Ch2 Address Pointer 0x0C,0x0D 16 Bits, Read/Write, Factory Preset 0x0886 A constant threshold for the output comparator in the fixed threshold mode can be set using these registers. The 12-bit CDC result corresponds to the 12 MSBs of the threshold register. The fixed threshold registers share the address pointer and location on-chip with the sensitivity and timeout registers. The fixed threshold registers are not accessible in the adaptive threshold mode. SENSITIVITY REGISTERS The input capacitance can be calculated from the output data using the following equation: C (pF) = FIXED THRESHOLD REGISTERS Ch1 Address Pointer 0x09 Ch2 Address Pointer 0x0C 8 Bits, Read/Write, Factory Preset 0x08 Sensitivity registers set the distance of the positive threshold above the data average, and the distance of the negative threshold below the data average, in the adaptive threshold mode. Data − 12288 × Input _ Range 40944 where Input_Range = 4 pF, 2 pF, 1 pF, or 0.5 pF. DATA The following is the same equation written with hexadecimal numbers: POSITIVE THRESHOLD SENSITIVITY Data − 0x3000 C (pF) = × Input _ Range 0x9FF 0 DATA AVERAGE SENSITIVITY A data register is updated after a finished conversion on the capacitive channel, with one exception: when the serial interface read operation from the data register is in progress, the data register is not updated and the new capacitance conversion result is lost. The stop condition on the serial interface is considered to be the end of the read operation. Therefore, to prevent incorrect data reading through the serial interface, the two bytes of a data register should be read sequentially using the register address pointer auto-increment feature of the serial interface. NEGATIVE THRESHOLD OUTPUT ACTIVE TIME Figure 37. Threshold Sensitivity The sensitivity is an 8-bit value and is mapped to the lower eight bits of the 12-bit CDC data, that is, it corresponds to the 16-bit data register as shown in Figure 38. SENSITIVITY BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 DATA HIGH DATA LOW BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 12-BIT CDC RESULT Figure 38. Relation Between Sensitivity Register and CDC Data Register Rev. 0 | Page 16 of 28 06517-046 DATA HIGH BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 06517-045 MSB The settling time of the average can be set by programming the ThrSettling bits in the setup registers. The average register is overwritten directly with the CDC output data, that is, the history is forgotten if the timeout is enabled and elapses. AD7150 When either the approaching or receding timeout elapses (that is, after the defined number of CDC conversions is counted), the data average (and thus the thresholds) is forced to follow the new CDC data value immediately. TIMEOUT REGISTERS Ch1 Address Pointer 0x0A Ch2 Address Pointer 0x0D 8 Bits, Read/Write, Factory Preset 0x86 When the timeout register equals 0, timeouts are disabled. Bits [7:4] TimeOutApr 0x08 Bits [3:0] TimeOutRec 0x06 DATA AVERAGE + SENSITIVITY DATA AVERAGE THRESHOLD These registers set timeouts for the adaptive threshold mode. The approaching timeout starts when the CDC data crosses the data average ± sensitivity band toward the threshold, according to the selected positive, negative, or window threshold mode. The approaching timeout elapses after the number of conversion cycles equals 2TimeOutApr, where TimeOutApr is the value of the four most significant bits of the timeout register. The receding timeout starts when the CDC data crosses the data average ± sensitivity band away from the threshold, according to the selected positive or negative threshold mode. The receding timeout is not used in the window threshold mode. The receding timeout elapses after the number of conversion cycles equals 2TimeOutRec, where TimeOutRec is the value of the four least significant bits of the timeout register. LARGE CHANGE IN DATA TOWARDS THRESHOLD TIMEOUT APPROACHING TIME 06517-047 Bit Mnemonic Default Figure 39. Threshold Timeout Approaching After a Large Change in CDC Data Toward Threshold TIMEOUT RECEDING DATA AVERAGE + SENSITIVITY DATA AVERAGE TIME THRESHOLD LARGE CHANGE IN DATA AWAY FROM THE THRESHOLD Figure 40. Threshold Timeout Receding After a Large Change in CDC Data Away from Threshold Rev. 0 | Page 17 of 28 06517-048 Table 9. Timeout Register Bit Map AD7150 SETUP REGISTERS Ch1 Address Pointer 0x0B Ch2 Address Pointer 0x0E 8 Bits, Read/Write, Factory Preset 0x0B Table 10. Setup Registers Bit Map Bit Mnemonic Default Bit 7 RngH Bit 6 RngL Bit 5 – Bit 4 Hyst 0 0 0 0 Bit 3 Bit 2 Bit 1 ThrSettling (4-Bit Value) Bit 0 0x0B Table 11. Setup Registers Bit Descriptions Mnemonic RngH RngL 5 4 – Hyst 3 2 1 0 ThrSettling Description Range bits set the CDC input range and determine the step for the AutoDAC function. RngH RngL Capacitive Input Range (pF) AutoDAC Step (CAPDAC LSB) 0 0 2 4 0 1 0.5 1 1 0 1 2 1 1 4 8 This bit should be 0 for the specified operation. Hyst = 1 disables hysteresis in adaptive threshold mode. This bit has no effect in fixed threshold mode; hysteresis is always disabled in the fixed threshold mode. Determines the settling time constant of the data average and thus the settling time of the adaptive thresholds. The response of the average to an input capacitance step change (that is, response to the change in the CDC output data) is an exponential settling curve characterized by the following equation: Average ( N ) = Average ( 0) + Change (1 − e N / TimeConst ) where: Average(N) is the value of average N complete CDC conversion cycles after a step change on the input. Average(0) is the value before the step change. TimeConst can be selected in the range between 2 and 65,536 conversion cycle multiples, in steps of power of 2, by programming the ThrSettling bits. TimeConst = 2 (ThrSettlin g + 1) See Figure 41. INPUT CAPACITANCE (CDC DATA) CHANGE DATA AVERAGE RESPONSE TIME Figure 41. Data Average Response to Data Step Change Rev. 0 | Page 18 of 28 06517-049 Bit 7 6 AD7150 CONFIGURATION REGISTER Address Pointer 0x0F 8 Bits, Read/Write, Factory Preset 0x19 Table 12. Configuration Register Bit Map Bit Mnemonic Default Bit 7 ThrFixed 0 Bit 6 ThrMD1 0 Bit 5 ThrMD0 0 Bit 4 EnCh1 1 Bit 3 EnCh2 1 Bit 2 MD2 0 Bit 1 MD1 0 Bit 0 MD0 1 Table 13.Configuration Register Bit Descriptions Bit 7 Mnemonic ThrFixed 6 5 ThrMD1 ThrMD0 4 3 2 1 0 EnCh1 EnCh2 MD2 MD1 MD0 Description ThrFixed = 1 sets the fixed threshold mode. The outputs reflect comparison of data and a fixed (constant) value of the threshold registers. ThrFixed = 0 sets the adaptive threshold mode. The outputs reflect comparison of data to the adaptive thresholds. The adaptive threshold is set dynamically, based on the history of the previous data. These bits set the output comparators mode. Output Active When ThrMD1 ThrMD0 Threshold Mode Adaptive Threshold Mode Fixed Threshold Mode 0 0 Negative data < average – sensitivity Data < Threshold 0 1 Positive data > average + sensitivity Data > Threshold 1 0 In-Window data > average – sensitivity ‒ AND data < average + sensitivity 1 1 Out-Window data < average – sensitivity – OR data > average + sensitivity Enables conversion on Channel 1. Enables conversion on Channel 2. Converter mode of operation setup. MD2 MD1 MD0 Mode Description 0 0 0 Idle Part is fully powered up but performing no conversion. 0 0 1 Continuous Part is repeatedly performing conversions on the enabled Conversion channel(s). If two channels are enabled, the part is sequentially switching between them. 0 1 0 Single Conversion Part performs a single conversion on the enabled channel. If two channels are enabled, the part performs two conversions, one on each channel. After finishing the conversion(s), the part goes to the idle mode. 0 1 1 Power-Down Powers down the on-chip circuits, except the digital interface. 1 X X Reserved Do not use these modes. Rev. 0 | Page 19 of 28 AD7150 POWER-DOWN TIMER REGISTER Address Pointer 0x10 8 Bits, Read/Write, Factory Preset 0x00 Table 14. Power-Down Timer Register Bit Map Bit Mnemonic Default Bit 7 – 0 Bit 6 – 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Power-Down Timeout (6-Bit Value) 0x00 Bit 0 Table 15.Power-Down Timer Register Bit Descriptions Bit [7:6] [5:0] Mnemonic – Power-Down Timeout Description These bits must be 0 for proper operation. Defines period duration of the power-down timeout. If the output comparator outputs have not been activated during the programmed period, the part enters power-down mode automatically. The part can be then returned to a normal operational mode either via the serial interface or by the power supply off/on sequence. The period is programmable in steps of four hours. For example, setting the value to 0x06 sets the duration to 24 hours. The maximum value of 0x3F corresponds to approximately 10.5 days. The value of 0x00 disables the power-down timeout, and the part does not enter power-down mode automatically. CAPDAC REGISTERS Ch1 Address Pointer 0x11 Ch2 Address Pointer 0x12 8 Bits, Read/Write, Factory Preset 0x00 Table 16. CAPDAC Registers Bit Map Bit Mnemonic Default Bit 7 DacEn 1 Bit 6 DacAuto 1 Bit 5 Bit 4 Bit 3 Bit 2 DacValue (6-Bit Value) 0x00 Bit 1 Bit 0 Table 17. CAPDAC Registers Bit Descriptions Bit 7 6 Mnemonic DacEn DacAuto Description DacEn = 1 enables capacitive DAC. DacAuto = 1 enables the AutoDAC function in the adaptive threshold mode. When the AutoDAC function is enabled, the part dynamically adjusts the CAPDAC to keep the CDC in an optimal operating capacitive range. The CAPDAC value is automatically incremented when the data average exceeds ¾ of the CDC full range, and the CAPDAC value is decremented when the data average goes below ¼ of the CDC full range. The AutoDAC increment or decrement step depends on the selected CDC capacitive input range. Bit has no effect in fixed threshold mode; the AutoDAC function is always disabled in the fixed threshold mode. [5:0] DacValue CAPDAC value, Code 0x00 ≈ 0 pF, Code 0x3F ≈ CAPDAC full range. SERIAL NUMBER REGISTER CHIP ID REGISTER Address Pointer 0x13, 0x14, 0x15, 0x16 32 Bits, Read-Only, 0xXXXX Address Pointer 0x17 8 Bits, Read-Only, 0xXX This register holds a serial number, unique for each individual part. This register holds the chip identification code, used in factory manufacturing and testing. Rev. 0 | Page 20 of 28 AD7150 SERIAL INTERFACE The AD7150 supports an I2C-compatible, 2-wire serial interface. The two wires on the serial bus (interface) are called SCL (clock) and SDA (data). These two wires carry all addressing, control, and data information one bit at a time over the bus to all connected peripheral devices. The SDA wire carries the data, while the SCL wire synchronizes the sender and receiver during the data transfer. The devices on the bus are classified as either master or slave devices. A device that initiates a data transfer message is called a master, while a device that responds to this message is called a slave. In continuous conversion mode, the address pointers’ autoincrementer should be used for reading a conversion result. This means that the two data bytes should be read using one multibyte read transaction rather than two separate single byte transactions. The single byte data read transaction may result in the data bytes from two different results being mixed. The same applies for four data bytes if both capacitive channels are enabled. To control the AD7150 device on the bus, the following protocol must be followed. First, the master initiates a data transfer by establishing a start condition, defined by a high-tolow transition on SDA while SCL remains high. This indicates that the start byte follows. This 8-bit start byte is made up of a 7-bit address plus an R/W bit indicator. If an incorrect address pointer location is accessed or if the user allows the auto-incrementer to exceed the required register address, the following applies: All peripherals connected to the bus respond to the start condition and shift in the next eight bits (7-bit address + R/W bit). The bits arrive MSB first. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as the acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. An exception to this is the general call address, which is described in the General Call section. In the idle condition, the device monitors the SDA and SCL lines waiting for the start condition and the correct address byte. The R/W bit determines the direction of the data transfer. A Logic 0 LSB in the start byte means that the master writes information to the addressed peripheral. In this case, the AD7150 becomes a slave receiver. A Logic 1 LSB in the start byte means that the master reads information from the addressed peripheral. In this case, the AD7150 becomes a slave transmitter. In all instances, the AD7150 acts as a standard slave device on the serial bus. The start byte address for the AD7150 is 0x90 for a write and 0x91 for a read. READ OPERATION When a read is selected in the start byte, the register that is currently addressed by the address pointer is transmitted to the SDA line by the AD7150. This is then clocked out by the master device, and the AD7150 awaits an acknowledge from the master. If an acknowledge is received from the master, the address autoincrementer automatically increments the address pointer register and outputs the next addressed register content to the SDA line for transmission to the master. If no acknowledge is received, the AD7150 returns to the idle state and the address pointer is not incremented. The address pointers’ auto-incrementer allows block data to be written to or read from the starting address and subsequent incremental addresses. The user can also access any unique register (address) on a oneto-one basis without having to update all the registers. The address pointer register contents cannot be read. • In read mode, the AD7150 continues to output various internal register contents until the master device issues a no acknowledge, start, or stop condition. The address pointers’ auto-incrementer contents are reset to point to the status register at the 0x00 address when a stop condition is received at the end of a read operation. This allows the status register to be read (polled) continually without having to constantly write to the address pointer. • In write mode, the data for the invalid address is not loaded into the AD7150 registers, but an acknowledge is issued by the AD7150. WRITE OPERATION When a write is selected, the byte following the start byte is always the register address pointer (subaddress) byte, which points to one of the internal registers on the AD7150. The address pointer byte is automatically loaded into the address pointer register and acknowledged by the AD7150. After the address pointer byte acknowledge, a stop condition, a repeated start condition, or another data byte can follow from the master. A stop condition is defined by a low-to-high transition on SDA while SCL remains high. If a stop condition is encountered by the AD7150, it returns to its idle condition and the address pointer is reset to 0x00. If a data byte is transmitted after the register address pointer byte, the AD7150 loads this byte into the register that is currently addressed by the address pointer register and sends an acknowledge, and the address pointer auto-incrementer automatically increments the address pointer register to the next internal register address. Thus, subsequent transmitted data bytes are loaded into sequentially incremented addresses. Rev. 0 | Page 21 of 28 AD7150 If a repeated start condition is encountered after the address pointer byte, all peripherals connected to the bus respond exactly as outlined previously for a start condition; that is, a repeated start condition is treated the same as a start condition. When a master device issues a stop condition, it relinquishes control of the bus, allowing another master device to take control of the bus. Therefore, a master wanting to retain control of the bus issues successive start conditions known as repeated start conditions. GENERAL CALL When a master issues a slave address consisting of seven 0s with the eighth bit (R/W bit) set to 0, this is known as the general call address. The general call address is for addressing every device connected to the serial bus. The AD7150 acknowledges this address and reads in the following data byte. If the second byte is 0x06, the AD7150 is reset, completely uploading all default values. The AD7150 does not respond to the serial bus commands (do not acknowledge) during the default values upload for approximately 2 ms. AD7150 RESET To reset the AD7150 without having to reset the entire serial bus, an explicit reset command is provided. This uses a particular address pointer word as a command word to reset the part and upload all default settings. The AD7150 does not respond to the serial bus commands (do not acknowledge) during the default values upload for approximately 2 ms. The AD7150 does not acknowledge any other general call commands. The reset command address word is 0xBF. SCLOCK S 1–7 8 9 1–7 8 9 START ADDR R/W ACK SUBADDRESS ACK 1–7 DATA 8 9 P ACK STOP 06517-050 SDATA Figure 42. Bus Data Transfer S SLAVE ADDR A(S) SUB ADDR A(S) DATA LSB = 0 READ SEQUENCE S SLAVE ADDR S = START BIT P = STOP BIT A(S) A(S) DATA A(S) P LSB = 1 SUB ADDR A(S) S SLAVE ADDR A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER A(S) DATA A(M) A(S) = NO ACKNOWLEDGE BY SLAVE A(M) = NO ACKNOWLEDGE BY MASTER Figure 43. Write and Read Sequences Rev. 0 | Page 22 of 28 DATA A(M) P 06517-051 WRITE SEQUENCE AD7150 HARDWARE DESIGN CONSIDERATIONS OVERVIEW PARASITIC RESISTANCE TO GROUND The AD7150 is an interface to capacitive sensors. On the input side, the sensor (CX) can be connected directly between the AD7150 EXC and CIN pins. The way it is connected and the electrical parameters of the sensor connection, such as parasitic resistance or capacitance, can affect the system performance. Therefore, any circuit with additional components in the capacitive front end, such as overvoltage protection, has to be carefully designed considering the AD7150 specified limits and information provided in this section. On the output side, the AD7150 can work as a standalone device, using the power-up default register settings and flagging the result on digital outputs. Alternatively, the AD7150 can be interfaced to a microcontroller via the 2-wire serial interface, offering flexibility by overwriting the AD7150 register values from the host with a user-specific setup. CIN CDC CIN CDC DATA CX RGND2 06517-053 EXC Figure 45. Parasitic Resistance to Ground The AD7150 CDC result is affected by a leakage current from CX to ground; therefore, CX should be isolated from the ground. The equivalent resistance between CX and ground should be maximized (see Figure 45). See Figure 10 to Figure 13. PARASITIC CAPACITANCE TO GROUND CGND1 RGND1 PARASITIC PARALLEL RESISTANCE DATA CIN CDC DATA CX EXC 06517-052 CGND2 RP EXC Figure 44. Parasitic Capacitance to Ground 06517-054 CX Figure 46. Parasitic Parallel Resistance The CDC architecture used in the AD7150 measures the capacitance, CX, connected between the EXC pin and the CIN pin. In theory, any capacitance CGND to ground should not affect the CDC result (see Figure 44). The practical implementation of the circuitry in the chip implies certain limits, and the result is gradually affected by capacitance to ground (see Table 1 for information about the allowed capacitance to GND for CIN and information about excitation). The AD7150 CDC measures the charge transfer between the EXC and CIN pins. Any resistance connected in parallel to the measured capacitance CX (see Figure 46), such as the parasitic resistance of the sensor, also transfers charge. Therefore, the parallel resistor is seen as an additional capacitance in the output data. The equivalent parallel capacitance (or error caused by the parallel resistance) can be approximately calculated as CP = See Figure 4 to Figure 9. 1 R P × f EXC × 4 where RP is the parallel resistance and fEXC is the excitation frequency. See Figure 15. Rev. 0 | Page 23 of 28 AD7150 INPUT EMC PROTECTION 39kΩ CX RS1 CIN 82kΩ 68pF CIN 22pF DATA CDC 10kΩ CDC EXC 47pF CX 06517-057 PARASITIC SERIAL RESISTANCE GND 06517-055 Figure 49. AD7150 CIN EMC Protection EXC Figure 47. Parasitic Serial Resistance The AD7150 CDC result is affected by a resistance in series with the measured capacitance. The total serial resistance (RS1 + RS2 in Figure 47) should be on the order of hundreds of Ω. See Figure 14. INPUT OVERVOLTAGE PROTECTION CDC RS1 Some applications may require an additional input filter for improving electromagnetic compatibility (EMC). Any input filter must be carefully designed, considering the balance between the system capacitance performance and system electromagnetic immunity. Figure 49 shows one of the possible input circuit configurations significantly improving the system immunity against high frequency noise and slightly affecting the AD7150 performance in terms of additional gain and offset error. POWER SUPPLY DECOUPLING AND FILTERING 1kΩ CIN 0.1µF CX VDD 10µF 1kΩ RS2 1kΩ SDA EXC GND 06517-056 CDC GND Figure 48. AD7150 CIN Overvoltage Protection The AD7150 capacitive input has an internal ESD protection. However, some applications may require an additional overvoltage protection, depending on the application-specific requirements. Any additional circuit in the capacitive front end must be carefully designed, especially with respect to the limits recommended for maximum capacitance to ground, maximum serial resistance, maximum leakage, and so on. SCL 06517-058 RS2 Figure 50. AD7150 VDD Decoupling and Filtering The AD7150 has good dc and low frequency power supply rejection but may be sensitive to higher frequency ripple and noise, specifically around the excitation frequency and its harmonics. Figure 50 shows a possible circuit configuration for improving the system immunity against ripple and noise coupled to the AD7150 via the power supply. If the serial interface is connected to the other circuits in the system, it is better to connect the pull-up resistors on the other side of the VDD filter than to connect to the AD7150. If the AD7150 is used in standalone mode and the serial interface is not used, it is better to connect the pull-up resistors directly to the AD7150 VDD. Rev. 0 | Page 24 of 28 AD7150 APPLICATION EXAMPLES 0.1µF VDD CIN1 1kΩ 1kΩ AD7150 SDA SCL CSENS1 EXC1 3V BATTERY OUT1 CIN2 OUT2 CSENS2 1kΩ 1kΩ LED1 LED2 06517-059 EXC2 GND Figure 51. AD7150 Standalone Operation Application Diagram 3.3V 0.1µF VDD CIN1 1kΩ 1kΩ AD7150 CSENS1 EXC1 SDA SDA SCL SCL HOST MICROCONTROLLER CIN2 OUT1 IRQ1 OUT2 IRQ2 06517-060 CSENS2 EXC2 GND Figure 52. AD7150 Interfaced to a Host Microcontroller 0.1µF 1kΩ 3.3V 10µF 1µF VSUPPLY ADP1720-3.3 1µF VDD 82kΩ 68pF CSENS1 CIN1 82kΩ 68pF CSENS2 1kΩ R1 R2 SDA 10kΩ EXC1 10kΩ OUT1 SCL 47pF 39kΩ 1kΩ AD7150 22pF OUT1 CIN2 Q1 OUT2 22pF OUT2 EXC2 47pF Q2 06517-061 39kΩ GND Figure 53. AD7150 Standalone Operation with EMC Protection Rev. 0 | Page 25 of 28 AD7150 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 6 5 5.15 4.90 4.65 PIN 1 0.50 BSC 0.95 0.85 0.75 0.15 0.05 1.10 MAX 0.33 0.17 SEATING PLANE 0.23 0.08 8° 0° 0.80 0.60 0.40 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 54. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model AD7150BRMZ 1 AD7150BRMZ-REEL1 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] Z = RoHS Compliant Part. Rev. 0 | Page 26 of 28 Package Option RM-10 RM-10 Branding C4Z C4Z AD7150 NOTES Rev. 0 | Page 27 of 28 AD7150 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06517-0-11/07(0) Rev. 0 | Page 28 of 28