Revised February 2005 74VHCT00A Quad 2-Input NAND Gate General Description Features The VHCT00A is an advanced high-speed CMOS 2-Input NAND Gate fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The internal circuit is composed of 3 stages, including buffer output, which provide high noise immunity and stable output. ■ High speed: tPD Protection circuits ensure that 0V to 7V can be applied to the input pins without regard to the supply voltage and to the output pins with VCC 0V. These circuits prevent device destruction due to mismatched supply and input/ output voltages. This device can be used to interface 3V to 5V systems and two supply systems such as battery backup. 5.0 ns (typ) at TA ■ High noise immunity: VIH 2.0V, VIL 25qC 0.8V ■ Power down protection is provided on all inputs and outputs ■ Low noise: VOLP 0.8V (max) ■ Low power dissipation: ICC 2 PA (max) at TA 25qC ■ Pin and function compatible with 74HCT00 Ordering Code: Order Number Package Package Description Number 74VHCT00AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHCT00ASJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHCT00AMTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHCT00AMTCX_NL (Note 1) MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHCT00AN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 74VHCT00AN_NL (Note 1) N14A Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Use this number to order device. © 2005 Fairchild Semiconductor Corporation DS500023 www.fairchildsemi.com 74VHCT00A Quad 2-Input NAND Gate July 1997 74VHCT00A Logic Symbol Connection Diagram Pin Descriptions Truth Table Pin Names Description An, Bn Inputs On Outputs www.fairchildsemi.com 2 A B O L L H L H H H L H H H L Recommended Operating Conditions (Note 6) 0.5V to 7.0V 0.5V to 7.0V Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) 0.5V to VCC 0.5V 0.5V to 7.0V 20 mA (Note 3) (Note 4) Input Diode Current (IIK) Supply Voltage (VCC) 4.5V to 5.5V Input Voltage (VIN) 0V to 5.5V Output Voltage (VOUT) Output Diode Current (IOK) (Note 3) 0V to VCC (Note 4) 0V to 5.5V 40qC to 85qC Operating Temperature (TOPR) r20 mA r25 mA r50 mA 65qC to 150qC (Note 5) DC Output Current (IOUT) DC VCC/GND Current (ICC) Storage Temperature (TSTG) Input Rise and Fall Time (tr, tf) VCC Lead Temperature (TL) 260qC (Soldering, 10 seconds) 5.0V r 0.5V 0 ns/V a 20 ns/V Note 2: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. Note 3: HIGH or LOW state. IOUT absolute maximum rating must be observed. Note 4: VCC 0V. Note 5: VOUT GND, V OUT ! VCC (Outputs Active) Note 6: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH VIL VOH HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage VOL LOW Level Output Voltage IIN Input Leakage Current ICC Quiescent Supply Current ICCT Maximum ICC/ Input IOFF VCC (V) Parameter 25qC TA Min Typ 40qC to 85qC TA Max Min 4.5 2.0 2.0 5.5 2.0 2.0 Max 0.8 0.8 5.5 0.8 0.8 4.5 4.40 3.94 4.50 4.5 0.0 V 4.40 V 3.80 V 0.1 Conditions V 4.5 4.5 Units 0.1 V VIN VIH or VIL VIN VIH 50 PA IOH 8 mA IOL 50 PA IOL 8 mA 4.5 0.36 0.44 V 0 5.5 r0.1 r1.0 PA VIN 5.5V or GND 5.5 2.0 20.0 PA VIN VCC or GND VIN 3.4V Output Leakage Current 5.5 1.35 1.50 mA 0.0 0.5 5.0 PA or VIL IOH Other Inputs VOUT VCC or GND 5.5V (Power Down State) Noise Characteristics Symbol Parameter TA 25qC VCC (V) Typ Limit Units Conditions VOLP (Note 7) Quiet Output Maximum Dynamic VOL 5.0 0.4 0.8 V CL 50 pF VOLV (Note 7) Quiet Output Minimum Dynamic VOL 5.0 0.4 0.8 V CL 50 pF VIHD (Note 7) Minimum HIGH Level Dynamic Input Voltage 5.0 2.0 V CL 50 pF VILD (Note 7) Maximum LOW Level Dynamic Input Voltage 5.0 0.8 V CL 50 pF Note 7: Parameter guaranteed by design. 3 www.fairchildsemi.com 74VHCT00A Absolute Maximum Ratings(Note 2) 74VHCT00A AC Electrical Characteristics Symbol tPLH Parameter Propagation Delay tPHL VCC (V) 5.0 r 0.5 25qC TA Min TA 40qC to 85qC Typ Max Min Max 5.0 6.9 1.0 8.0 5.5 7.9 1.0 9.0 10 CIN Input Capacitance 4 CPD Power Dissipation Capacitance 17 10 Units ns Conditions CL 15 pF CL 50 pF pF VCC pF (Note 8) Open Note 8: CPD is defined as the value of the internal equivalent capacitance, which is calculated from the operating current consumption without load. Average operating current can be obtained from the equation: ICC (opr.) CPD * VCC * fIN I CC/4 (per gate) www.fairchildsemi.com 4 74VHCT00A Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A 5 www.fairchildsemi.com 74VHCT00A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D www.fairchildsemi.com 6 74VHCT00A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 7 www.fairchildsemi.com 74VHCT00A Quad 2-Input NAND Gate Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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