ETC 74VHCT08N

Revised March 1999
74VHCT08A
Quad 2-Input AND Gate
General Description
The VHCT08A is an advanced high speed CMOS 2 Input
AND Gate fabricated with silicon gate CMOS technology. It
achieves the high-speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation.
The internal circuit is composed of 4 stages including buffer
output, which provide high noise immunity and stable output.
Protection circuits ensure that 0V to 7V can be applied to
the input pins without regard to the supply voltage and to
the output pins with VCC = 0V. These circuits prevent
device destruction due to mismatched supply and input/
output voltages. This device can be used to interface 3V to
5V systems and two supply systems such as battery
backup.
Features
■ High speed: tPD = 5.0 ns (typ) at TA = 25°C
■ High noise immunity: VIH = 2.0V, VIL = 0.8V
■ Power down protection is provided on all inputs and
outputs
■ Low noise: VOLP = 0.8V (max)
■ Low power dissipation:
ICC = 2 µA (max) @ TA = 25°C
■ Pin and function compatible with 74HCT08
Ordering Code:
Order Number
Package Number
74VHCT08AM
74VHCT08ASJ
74VHCT08AMTC
74VHCT08AN
M14A
M14D
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code
Connection Diagram
Logic Symbol
IEEE/IEC
Pin Descriptions
Pin Names
Truth Table
Description
A
B
O
An, Bn
Inputs
L
L
L
On
Outputs
L
H
L
H
L
L
H
H
H
© 1999 Fairchild Semiconductor Corporation
DS500025.prf
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74VHCT08A Quad 2-Input AND Gate
July 1997
74VHCT08A
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC)
−0.5V to +7.0V
DC Input Voltage (VIN)
−0.5V to +7.0V
Recommended Operating
Conditions (Note 5)
DC Output Voltage (VOUT)
(Note 2)
−0.5V to VCC + 0.5V
(Note 3)
Supply Voltage (VCC)
4.5V to 5.5V
Input Voltage (VIN)
0V to +5.5V
Output Voltage (VOUT)
−0.5V to 7.0V
(Note 2)
0V to VCC
Input Diode Current (IIK)
−20 mA
(Note 3)
0V to 5.5V
Output Diode Current (IOK) (Note 4)
±20 mA
Operating Temperature (TOPR)
DC Output Current (IOUT)
±25 mA
Input Rise and Fall Time (tr, tf)
±50 mA
DC VCC/GND Current (ICC)
VCC = 5.0V ± 0.5V
−65°C to +150°C
Storage Temperature (TSTG)
0 ns/V ∼ 20 ns/V
Note 1: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications.
Lead Temperature (TL)
(Soldering, 10 seconds)
−40°C to +85°C
260°C
Note 2: HIGH or LOW state. IOUT absolute maximum rating must be
observed.
Note 3: VCC = 0V.
Note 4: VOUT < GND, VOUT > VCC (Outputs Active).
Note 5: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
VIH
VIL
VOH
VCC
(V)
Parameter
TA = 25°C
Min
Typ
TA = −40°C to +85°C
Max
Min
HIGH Level
4.5
2.0
2.0
Input Voltage
5.5
2.0
2.0
Max
4.5
0.8
0.8
Input Voltage
5.5
0.8
0.8
HIGH Level
4.5
4.40
4.5
3.94
VOL
LOW Level Output Voltage
4.5
IIN
Input Leakage Current
4.50
Conditions
V
LOW Level
Output Voltage
Units
V
4.40
V
3.80
V
VIN = VIH
or VIL
IOH = −50 µA
IOL = 50 µA
IOH = −8 mA
4.5
0.36
0.44
V
VIN = VIH
or VIL
0 − 5.5
±0.1
±1.0
µA
VIN = 5.5V or GND
5.5
2.0
20.0
µA
VIN = VCC or GND
0.0
0.1
0.1
V
IOL = 8 mA
ICC
Quiescent Supply Current
ICCT
Maximum ICC/ Input
5.5
1.35
1.50
mA
V IN = 3.4V
Other Inputs = V CC or GND
IOFF
Output Leakage Current
0.0
0.5
5.0
µA
VOUT = 5.5V
(Power Down State)
Noise Characteristics
Symbol
Parameter
TA = 25°C
VCC
(V)
Typ
Limit
Units
Conditions
VOLP
(Note 6)
Quiet Output Maximum Dynamic VOL
5.0
0.4
0.8
V
CL = 50 pF
VOLV
(Note 6)
Quiet Output Minimum Dynamic VOL
5.0
−0.4
−0.8
V
CL = 50 pF
VIHD
(Note 6)
Minimum HIGH Level Dynamic Input Voltage
5.0
2.0
V
CL = 50 pF
VILD
(Note 6)
Maximum LOW Level Dynamic Input Voltage
5.0
0.8
V
CL = 50 pF
Note 6: Parameter guaranteed by design.
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2
Symbol
tPLH
Parameter
Propagation Delay
tPHL
VCC
(V)
TA = 25°C
Min
TA = −40°C to +85°C
Typ
Max
Min
Max
5.0
5.0
6.9
1.0
8.0
±0.5
1.0
9.0
5.5
7.9
CIN
Input Capacitance
4
10
CPD
Power Dissipation Capacitance
18
10
Units
Conditions
ns
CL = 15 pF
pF
VCC = Open
pF
(Note 7)
CL = 50 pF
Note 7: CPD is defined as the value of the internal equivalent capacitance, which is calculated from the operating current consumption without load. Average
operating current can be obtained from the equation: ICC (opr.) = CPD * VCC * fIN + ICC/4 (per gate)
3
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74VHCT08A
AC Electrical Characteristics
74VHCT08A
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
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4
74VHCT08A
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
5
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74VHCT08A Quad 2-Input AND Gate
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
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to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
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user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.