Version 1.2 , May 2004 Datasheet DS-CoreControl-TDA21302 TDA21302 Authors: Edward Chang Published by Infineon Technologies AG http://www.infineon.com/DCDC Power Management & Supply N e v e r s t o p t h i n k i n g. CoreControl TM Page 1 of 25 DS-CoreControl-TDA21302 Contents: Features………………………………………………………………………………………………………......3 Application……………………………………………………………………………………………………...…3 Pinout Drawing and Description………………………………………………………………………………..3 General Description……………………………………………………………………………………………...5 Block Diagram…………………………………………………………………………………………………….5 Reference Schematic……………………………………………………………………………………………6 Absolute Maximum Rating .................................................................................................................... 7 Thermal Characteristic.......................................................................................................................... 7 Electrical Characteristic ........................................................................................................................ 7 Operating Condition.............................................................................................................................. 9 VRD10,x VID Table ............................................................................................................................ 10 Application Information ....................................................................................................................... 11 Voltage Control………………………………………………………………………………………..11 Current Balance……………………………………………………………………………………….12 Load Droop…………………………………………………………………………………………….12 Fault Detection………………………………………………………………………………………...12 Phase Setting and Converter Start Up……………………………………………………………...13 Current Sensing Setting………………………………………………………………………………13 DAC Offset Voltage & Droop Tuning………………………………………………………………..14 Protection and SS Function………………………………………………………………………….15 Design Procedure Suggestion ............................................................................................................ 16 Design Example.................................................................................................................................. 17 Layout Guide ...................................................................................................................................... 20 Outline Diemension……………………………………………………………………………………………..22 CoreControl TM Page 2 of 25 DS-CoreControl-TDA21302 Multi-Phase PWM Controller for CPU Core Power Supply P-DSO-32 Features : • • • • • • • • Multi-Phase PWM Conversion with Automatically Phase Selection VRD10.X Compliant Active Droop Compensation For Fast Load Response Smooth VCORE Voltage Transition during the VID On The Fly Power Stage Thermal Balance By Sync FET Rds(on) Current Sense Technique Hiccup Mode Over Current Protection Programmable Switching Frequency ( 50KHz ~ 400KHz per Phase ), Under Voltage Lockout, and Soft-Start High Output Ripple Frequency times numbers of working Channels Application : • • • Intel Processor Voltage Regulator : VRM10.X Low Output Voltage High Output Current DC-DC Converters Voltage Regulator Modules Type Package Marking Ordering Code TDA21302 P-DSO-32 21302 Q67042-S4229 Pinout Drawing and Description : CoreControl TM Page 3 of 25 DS-CoreControl-TDA21302 CoreControl TM Page 4 of 25 DS-CoreControl-TDA21302 Number Name Description 1 OVP 2 PGOOD 3 VID4 Voltage Identification DAC Input. Internally pull up to 3V. 4 VID3 Voltage Identification DAC Input. Internally pull up to 3V. 5 VID2 Voltage Identification DAC Input. Internally pull up to 3V. 6 VID1 Voltage Identification DAC Input. Internally pull up to 3V. 7 VID0 Voltage Identification DAC Input. Internally pull up to 3V. 8 VID125 Voltage Identification DAC Input. Internally pull up to 3V. 9 VOSS Connect a resistor to GND to set the initial offset voltage. 10 ADJ Connect a resistor to GND to set the Droop Voltage. 11 SS Soft-Start. Connect with a capacitor to GND to set the Soft-Start Interval. Pulling down this pin Over voltage trip output Open drain power good signal output pin below 1V shall shut the converter down. Internal error amplifier inverting input pin 12 FB 13 COMP 14 VDIF Output pin of the differential converter output voltage sense 15 ISN4 Differential current sense negative input pin connects to the drain pin of channel 4 Sync FET 16 ISN3 Differential current sense negative input pin connects to the drain pin of channel 3 Sync FET 17 ISN2 Differential current sense positive input pin connects to the drain pin of channel 2 Sync FET 18 ISN1 Differential current sense positive input pin connects to the drain pin of channel 1 Sync FET 19 VSEN The positive input pin of the differential converter output voltage sense amplifier 20 SGND The negative input pin of the differential converter output voltage sense amplifier 21 GND Ground pin of the IC 22 PWM3 23 ISP3 Differential current sense positive input pin connects to the source pin of channel 3 Sync FET 24 ISP1 Differential current sense positive input pin connects to the source pin of channel 1 Sync FET 25 PWM1 Channel 1 PWM output pin 26 PWM2 Channel 2 PWM output pin 27 ISP2 Differential current sense positive input pin connects to the source pin of channel 2 Sync FET 28 ISP4 Differential current sense positive input pin connects to the source pin of channel 4 Sync FET 29 PWM4 30 VCC IC power supply pin connects to 5V 31 DVD Connect the external voltage divider to program the controller under voltage lockout based on Output of the error amplifier and input of the PWM comparator Channel 3 PWM output pin. Connect to high level for 2 phase operation. Channel 4 PWM output pin. Connect to high level for 2 or 3 phase operation. the input voltage of the power stage voltage 32 RT CoreControl TM Connect a resistor to GND to set the channel switching frequency Page 5 of 25 DS-CoreControl-TDA21302 General Description TDA21302 is a multi-phase DC-DC buck converter controller integrated all control functions for the next generation GHz CPU voltage regulator. TDA21302 automatically controls 2 to 4 interleaved buck switching power stage operation. The multi-phase architecture is able to provide high output current with lower power dissipation on the switching devices and minimizing the input ripple current and output ripple voltage. The equivalent high operation frequency optimizes the voltage regulator design for better transient response and thermal performance. TDA21302 utilizes the Sync FET Rds(on) in every channel as the current sense element. The differential current sense in every channel results precious channel current information to the controller for good droop adjustment, channel current balance, channel switching devices thermal balance and over current protection. Block Diagram PGOOD VCC OVP DVD RT Power On VID0 VID1 VID2 VID3 VID4 OVP & Step Setting Control PG Setting + & Sawtooth INH I + + + + + + + I OCP Setting I I + + Offset VOSS Oscillatior Reset VID DAC INH + Setting + I + + + I PWM Logic PWM1 PWM CMP INH PWM Logic PWM2 PWM CMP INH PWM Logic PWM3 PWM CMP INH PWM Logic PWM4 PWM CMP I + ISN1 I ISP1 + + ISN2 I I ISP2 + + ISN3 I I ISP3 + ISN4 I ISP4 + I SGND VSEN I + + I + Soft I Start VDIF FB CoreControl TM COMP SS Current Correction SUM/M ADJ Page 6 of 25 DS-CoreControl-TDA21302 Reference Schmatic CoreControl TM Page 7 of 25 DS-CoreControl-TDA21302 Absolute Maximum Ratings At Tj = 25 °C, unless otherwise specified Value Parameter Symbol Min. Max. VCC -0.3 7 -0.3 Vcc+0.3 V °C Voltage supplied to ‘VCC’ pin; DC Input, Output or I/O Pin Junction temperature TJ 0 125 Storage temperature TS -65 150 ESD Rating; Human Body Model ESD Rating; Machine M Model Unit 2 KV 200 V IEC climatic category; DIN EN 60068-1 55/150/56 - Thermal Characteristic Values Parameter Symbol Min. Typ. Max. Thermal resistance, junction-soldering point Unit K/W Thermal resistance, junction-ambient 50 Electrical Characteristic At Vcc=5V, Tj = 25 °C, unless otherwise specified Values Parameter Symbol Conditions Min. Typ. Max. Unit Supply Characteristic Bias supply current ICC PWM1,2,3,4 Open 12 16 mA 4,0 4,2 4,5 V 0,2 0,5 1,9 2 Power On Reset Characteristic POR Threshold VCCRTH Hysteresis VCCHYS VDVD Threshold VDVDTP Low to High Enable VDVD Hysteresis VDVDHYS VVCC falling threshold VCC rising threshold 2,1 0,1 Oscillator CoreControl TM Page 8 of 25 DS-CoreControl-TDA21302 Oscillator Frequency fOSC RRT = 12 KΩ 170 200 230 KHz Accuracy Oscillator Frequency fOSC_ADJ 50 400 Adjustable Range Ramp Amplitude Ramp Valley ∆VOSC V 0,7 1,0 V Every Phase 62 66 75 % RRT = 12 KΩ 0,55 0,6 0,65 V VDAC ≥ 1V -1 +1 % VDAC < 1V -10 +10 mV 0,4 V VRV Maximum Duty Cycle RT Pin Voltage 1,9 RRT = 12 KΩ VRT Reference and DAC DACOUT Voltage ∆VDAC Accuracy DAC (VID0~VID125) Input Low DAC (VID0~VID125) RRT = 12 KΩ VRV 0,8 V IBIAS_DAC 60 120 180 uV 0,95 1,0 1,05 V Input High DAC ( VID0~VID125) Bias Current VOSS Pin Voltage VVOSS RVOSS = 100 KΩ Error Amplifier Open Loop Gain Gain Bandwidth Slew Rate GBW SR COMP = 10 pF 85 dB 10 MHz 3 V/uS Differential Sense Amplifier Input Impedance ZIMP 16 KΩ Gain Bandwidth GBW 10 MHz 3 V/uS Slew Rate SR COMP = 10 pF Differential Current Sense GM Amplifier ISP1, 2, 3, 4 Full IISPFSS 60 uA Scale Source Current ISP1, 2, 3, 4 Current IISPOCP for OCP CoreControl TM 100 Page 9 of 25 DS-CoreControl-TDA21302 uA At Vcc=5V, Tj = 25 °C, unless otherwise specified Protection SS Current Iss Vss = 1V 8 13 18 uA 130 140 150 % 2,2 3,28 4,0 V Over Voltage Trip ( VSENSE / DACOUT ) ∆VOVT OVP Voltage VOVP IOVP = 10mA VPG VSENSE Rising VPGL IPG = 4mA Power Good Power Good Rising Threshold 92 % ( VSENSE / DACOUT ) Power Good Low 0,2 V Voltage Operating Conditions At Tj = 25 °C, unless otherwise specified Values Parameter Voltage supplied to Symbol Conditions Min. Typ. Max. Unit VVCC 4,5 Ambient temperature TA Junction temperature TJ 5,0 5,5 V 0 70 °C 0 125 °C ‘VCC’ pins CoreControl TM Page 10 of 25 DS-CoreControl-TDA21302 VRD10,X VID Table Pin Names Pin Names VID125 VID4 VID3 VID2 VID1 VID0 Vcore VID125 VID4 VID3 VID2 VID1 VID0 Vcore 0 0 1 0 1 0 0,8375 0 1 1 0 1 0 1,2125 1 0 1 0 0 1 0,8500 1 1 1 0 0 1 1,2250 0 0 1 0 0 1 0,8625 0 1 1 0 0 1 1,2375 1 0 1 0 0 0 0,8750 1 1 1 0 0 0 1,2500 0 0 1 0 0 0 0,8875 0 1 1 0 0 0 1,2625 1 0 0 1 1 1 0,9000 1 1 0 1 1 1 1,2750 0 0 0 1 1 1 0,9125 0 1 0 1 1 1 1,2875 1 0 0 1 1 0 0,9250 1 1 0 1 1 0 1,3000 0 0 0 1 1 0 0,9375 0 1 0 1 1 0 1,3125 1 0 0 1 0 1 0,9500 1 1 0 1 0 1 1,3250 0 0 0 1 0 1 0,9625 0 1 0 1 0 1 1,3375 1 0 0 1 0 0 0,9750 1 1 0 1 0 0 1,3500 0 0 0 1 0 0 0,9875 0 1 0 1 0 0 1,3625 1 0 0 0 1 1 1,0000 1 1 0 0 1 1 1,3750 0 0 0 0 1 1 1,0125 0 1 0 0 1 1 1,3875 1 0 0 0 1 0 1,0250 1 1 0 0 1 0 1,4000 0 0 0 0 1 0 1,0375 0 1 0 0 1 0 1,4125 1 0 0 0 0 1 1,0500 1 1 0 0 0 1 1,4250 0 0 0 0 0 1 1,0625 0 1 0 0 0 1 1,4375 1 0 0 0 0 0 1,0750 1 1 0 0 0 0 1,4500 0 0 0 0 0 0 1,0875 0 1 0 0 0 0 1,4625 1 1 1 1 1 1 OFF 1 0 1 1 1 1 1,4750 0 1 1 1 1 1 OFF 0 0 1 1 1 1 1,4875 1 1 1 1 1 0 1,1000 1 0 1 1 1 0 1,5000 0 1 1 1 1 0 1,1125 0 0 1 1 1 0 1,5125 1 1 1 1 0 1 1,1250 1 0 1 1 0 1 1,5250 0 1 1 1 0 1 1,1375 0 0 1 1 0 1 1,5375 1 1 1 1 0 0 1,1500 1 0 1 1 0 0 1,5500 0 1 1 1 0 0 1,1625 0 0 1 1 0 0 1,5625 1 1 1 0 1 1 1,1750 1 0 1 0 1 1 1,5750 0 1 1 0 1 1 1,1875 0 0 1 0 1 1 1,5875 1 1 1 0 1 0 1,2000 1 0 1 0 1 0 1,6000 Note : “ 1 “ is open and “ 0 “ is connecting to ground. CoreControl TM Page 11 of 25 DS-CoreControl-TDA21302 Application Information : TDA21302 is a multi-phase DC/DC controller that precisely regulates CPU core voltage and balances the current of different power channels. The converter consisting of TDA21302 and its companion drivers, TDA21106 and TDA21102, provides high quality CPU power and all the protection functions to meet the requirement of the latest VRMs. Voltage Control The TDA21302 senses the CPU VCORE by an precise instrumental amplifier to minimize the voltage drop on the PCB trace at heavy load condition. VSEN & SGND are the differential input pins for VCORE and their output, VDIF, is the input of the PGOOD & OVP sense. The internal highly accurate VID DAC provides the reference voltage for VRD10,X compliance. Control loop consists of error amplifier, pulse width modulator, external driver ICs and power components. Like conventional voltage mode controller, the output voltage is locked at the VREF of the error amplifier and the error signal is used as the control signal Vc of the pulse width modulator. The PWM signals of different channels are generated by comparison of EA output and split-phase saw-tooth wave. Power stage transforms VIN to output by PWM signal on-time ratio. PGOOD VCC OVP DVD Power On VID0 VID1 VID2 VID3 VID4 VID125 Reset VID DAC OVP Setting & Step + INH I PG Setting + I Offset VOSS Setting + PWM Comparator I SGND + I VSEN I + Soft Start VDIF CoreControl TM FB COMP Page 12 of 25 SS ADJ DS-CoreControl-TDA21302 Current Balance TDA21302 senses the current of the Sync FET in each phase when it is conducting for channel balance and droop tuning. The differential sensing GM amplifier converts the voltage on the sense components which can be sense resistors or the Rds(on) of the Sync FET to current signal into internal balance circuit. The current balance circuit sums and averages the current signals and then generates the balancing signals injected to pulse signal modulator. If some of the channel current is higher than average, the balancing signal shall decrease the pulse width to keep the current balance. RT INH Oscillatior & + + Sawtooth + + + + + + COMP Current Correction SUM/M + I + I + I + I PWM Logic PWM1 PWM CMP INH PWM Logic PWM2 PWM CMP INH PWM Logic PWM3 PWM CMP INH PWM Logic PWM4 PWM CMP + ISN1 I ISP1 + ISN2 I ISP2 + ISN3 I ISP3 + ISN4 I ISP4 Load Droop The sensed channel current signals regulated the reference of DAC to form a output voltage droop proportional to the load current. The droop or so-called “ Active Voltage Positioning “ can reduce the output voltage ripple during the load transient and the size of the LC filters. Fault Detection The chip detects VCORE for over voltage and power good detection. The “ hiccup mode “ operation of over-current protection is adopted to reduce the short circuit current. The inrush current at the start up is suppressed by the soft start circuit through clamping the pulse width and output voltage. CoreControl TM Page 13 of 25 DS-CoreControl-TDA21302 Phase Setting and Converter Start Up The TDA21302 interfaces with companion MOSFET drivers, TDA21106 ( Single Channel ) and TDA21102 ( Dual Channel ), for correct converter initialization. The tri-state PWM output pins sense the interface voltage at IC POR period ( both VCC and DVD trip ). The channel is enabled if the voltage at the pin is 1,2V less than VCC. Please tie the PWM outputs to VCC and the current sense pins to GND or leave them floating if the channel is unused. For 3 Phase application, connect PWM4 high. Current Sensing Setting TDA21302 senses the current of the Sync FET in each phase when it is conducting for channel balance and droop tuning. The differential sensing GM amplifier converts the voltage on the sense components which can be sense resistors or the Rds(on) of the Sync FET to current signal into internal balance circuit. IX1 Current IBP Balance IX1 Droop 2IX1 Sample OCP IX1 & Hold ISP1 RSP1 IL1 ISN1 RSN1 IBP RDS(on)1 Differential Current GM Amplifier Basic Theory V + = IBP × RSN1 , V − = (IBP+IX1) × RSP1 − IL1_VALLEY × RDS(on)1 ∵ V + = V − and RSN1 = RSP1 ⇒ ∴ IX1 = IL1_VALLEY × RDS(on)1 RSP1 IPEAK IAVG ∆I= ∆I VO × TOFF L Ivalley IL × RS by local feedback. RSP = RSN to cancel the voltage drop caused by RSP GM amplifier input bias current. IX is sampled and held just before low side MOSFET turns off. The sensing circuit gets IX= Therefore, CoreControl TM Page 14 of 25 DS-CoreControl-TDA21302 IL (S/H) × RS VO × TOFF VIN - VO , IL (S/H)=IL (AVG) , TOFF = × 3,3uS for FOSC = 300 KHz RSP 2L VIN VIN - VO × 3,3uS VO × VIN × RS ∴ IX (S/H)= IL (AVG) RSP 2L IX (S/H)= DAC Offset Voltage & Droop Setting 1V Rf1 × The DAC offset voltage is set by compensation network & external resistor at VOSS pin by RVOSS. 4 The S/H current signals from power channel are injected to ADJ pin to establish the droop voltage. VADJ = RADJ X ∑2IX. The DAC output voltage decreased by VADJ to generate the VCORE load droop. CoreControl TM Page 15 of 25 DS-CoreControl-TDA21302 Protection and SS Function For OVP, the TDA21302 detects the VCORE by VDIF pin voltage that is the output of the differential amplifier. This is to eliminate the delay caused by the compensation network for faster and more accurate detection. The trip point of OVP is 140% of the normal VCORE voltage level. The PWM outputs are pulled low to turn on the Sync FET and to turn off the control FET while OVP is detected. The OVP latch can only be reset by either VCC or DVD. The PGOOD trip point is set at the 92% of the normal VCORE voltage level. The open drain PGOOD pin shall be pulled low while VCORE is lower than this point. During the VID on the fly condition, there is nothing able to change the status of the PGOOD. Soft-start circuit generates a ramp by charging an external capacitor with a 13uA constant current source after the POR of IC is active. The pulse width of PWM signal and VCORE are clamped by rising ramp to reduce the inrush current and protect the power devices. Over-current protection trip point is internally set at around 100uA for each channel. OCP is triggered if one channel S/H current signal. Controller forces PWM output latched at high impedance to turn off both control and Sync FETs in the power stage and initial the hiccup mode protection. The SS pin voltage is pulled low with a 13uA current after it is less than 90% VCC. The converter restarts after SS pin voltage is lower than 0,2V. Three times of OCP disable the converter and only release the latch by POR acts. CH1 : VADJ CH2 : Short Circuit Current CH3 : VCORE CH4 : VSS CoreControl TM Page 16 of 25 DS-CoreControl-TDA21302 Design Process Suggestion : Voltage Loop Setting • • • Pole and Zero of output filter : Output inductor value, the capacitance and ESR value of the output capacitors Compensation Network : Error amplifier compensation & sawtooth wave amplitude. Kelvin sense for VCORE Current Loop Setting • • GM amplifier S/H current setting : Current sensing components ( Rds(on) ), the value of the resistors connecting to ISPx & ISNx. Do keep ISPx current < 60uA at full load condition for better load line linearity. Over current protection trip point : This has been set internally and please keep ISPx < 100uA at OCP condition for better accuracy. VRM Load Line Setting • • • Droop amplitude : External ADJ pin resistor. No load offset : Additional resistor in compensation network. DAC offset voltage seeting : VOSS pin & compensation network resistor. PCB Layout • • Kelvin sense for current sense GM amplifier input. Refer to layout guide for other item. CoreControl TM Page 17 of 25 DS-CoreControl-TDA21302 Design Example : Given Apply for four phase converter VIN = 12V VCORE = 1,35V ILOAD = 100A VDROOP = 100 mV at full load OCP set at 35A for each channel ( S/H ) Rds(on) = 3 mΩ for Sync FET at 25°C ( 2 X IPU06N03LA in parallel ) LOUT = 0,6uH COUT = 17,600 uH with 1 mΩ ESR 1. Compensation Setting • Modulator Gain, Pole and Zero : From the following formula ; Modulator Gain = VIN = VRAMP 12V 3 1,9V × 2 = 4,2 ( 12,46 dB ) Where VRAMP : ramp amplitude of the sawtooth waveform LC Filter Pole = ESR Zero = • 1 2π × LC = 1,549 KHz and 1 = 9,0429 KHz 2π × ESR × COUT EA Compensation Network : Select RF1 = 2,4 KΩ , RF2 = 24 KΩ , CC2 = 6,6 nF, CC1 = 33 pF and Use type 2 compensation scheme shown in Figure 5. CoreControl TM Page 18 of 25 DS-CoreControl-TDA21302 Error VDAC Amplifier RF2+(1/SCC2) RF1 VDIF RF2 FB 1 ) C2RF2 C RZ = CC1 + CC2 SCC1(S + ) RF2CC1CC2 (S + CC2 COMP CC1 From the following formulas : FZ = 1 = 1 KHz , FP = 2π × RF2 × CC1 1 CC1 × CC2 = 200 KHz 2π × RF2 × CC1+CC2 RF2 Middle Band Gain = RF1 = 10 ( 20 dB ) The asymptotic bode plot of EA compensation and PWM loop gain is shown as below. CoreControl TM Page 19 of 25 DS-CoreControl-TDA21302 2. Droop & DAC Offset Setting For each channel the load current is 100A / 4 = 25A and the ripple current, ∆IL , is given as 3,33uS × 1,35V 1,35V × 1− 0,6uH 12V = 6,65 A ∆I The load current, IL, at S/H is 25A - 2 = 21,675 A. Using the following formula to select the appropriate IX(MAX) for the S/H of GM amplifier : IX(MAX) = RDS(ON) × 21,675A RSP The suggested IX is in the range of 50 uA ± 5uA, select RSP = RSN = 1,5 KΩ, then IX(MAX) would be 43,35 uA. VDROOP = 100 mV = 43,35 uA X 2 X 4 X RADJ, therefore RADJ = 287 Ω. The RDS(ON) of MOSFET varies with temperature rise. When the Sync FETs are working at 100°C junction temperature, the RDS(ON) of MOSFET at 100°C is given as 7,3 mΩ. So the RADJ at 100°C is given as : RADJ_100°C X ( RDS(ON)_25°C / RDS(ON)_100°C ) = 236 Ω 3. Over Current Protection Setting OCP trip point is internally set at around 100 uA of IX for each channel. As above selected RSP = RSN = 1,5 KΩ, the OCP trip point is found using : Ix(OCP) = RDS(ON) × IL(TRIP) 3mΩ × IL(TRIP) = = 100uA RSP 1,5KΩ 4. Soft-start Capacitor Selection CSS = 100 nF is the suitable value for most application. ISS × tSS VSS ISS = 13 uA , VSS = 2V , tSS = 10 mS CSS = 65 nF ISS × tSS = VSS × CSS ⇒ CSS = CoreControl TM Page 20 of 25 DS-CoreControl-TDA21302 Layout Guide : Place the high-power switching components first, and separate them from the sensitive nodes. 1. Most Critical Path : The current sense circuit is the most sensitive part of the converter. The current sense resistor tied to ISP1,2,3,4 and ISN1,2,3,4 should be located not more than 0,5 inch from the IC and away from the noise switching nodes. The PCB trace of sense nodes should be parallel and as short as possible. Kelvin connection of the sense component, additional current sense resistor or the RDS(ON) of MOSFETs, ensures the accurate and stable current sensing signals. DPAK or D2PAK IPAK 2. Switching Ripple Path : • • • • • • The best connection of the input capacitors is to place at the drain of the high side MOSFET and the source of the low side MOSFET. Low side MOSFET to the output capacitor. The return path of input and output capacitor. Separate the power and signal GND. The PHASE node, the conjunction of the high / low side MOSFETs and inductor, is the nosiy node. Keep them away from the sensitive small-signal node. Reducing the parasitic impedance and inductance is done by minimizing the length of the traces, offering enough copper area and avoiding the vias. CoreControl TM Page 21 of 25 DS-CoreControl-TDA21302 3. MOSFET drivers : • • • • • Both of the decoupling capacitors for VCC and PVCC should be placed as close to the driver IC as possible. The bootstrap capacitor should be placed close to the BOOT pin. The traces of GATEHS and PHASE should be routed in parallel and to keep it short and wide. The width of the trances should be no less than 40mils. High current loops from the input capacitor, high side MOSFET, output inductors and output capacitors back to the input capacitor negative terminal should be kept the distance minimized. The conjunction of high side MOSFET, low side MOSFET and output inductor should be kept as close as possible. 4. Other Path : • • The components from the compensation network, high frequency bypass capacitors and the setting resistors should be placed near controller IC and away from the noisy power path. The thermal compensation thermistor should be placed at the hottest point which is normally the MOSFETs located at the inner part of the power stage. CoreControl TM Page 22 of 25 DS-CoreControl-TDA21302 Outline Dimension : CoreControl TM Page 23 of 25 DS-CoreControl-TDA21302 Revision History Datasheet DS-CoreControl-TDA21302 Actual Release: V1.2 Date: 10.04.2004 Page of Page of actual Rel. prev. Rel. Previous Release: V1.1 Date: 10.01.04 Subjects changed since last release 17 17 CC1 = 6,6 nF, CC2 = 33 pF => CC2 = 6,6 nF, CC1 = 33 pF 10 10 VID table correction VID4 1Æ 0 from 1,0375V to 1,0875v For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see the address list on the last page or our webpage at http://www.infineon.com/DCDC OptiMOS and OptiMOS II are trademarks of Infineon Technologies AG. We listen to Your Comments Any information within this dokument that you feel is wrong, unclear or missing at all? Your feedback will help us to continously improve the quality of this dokument. Please send your proposal (including a reference to this dokument) to: [email protected] Edition 2004-01-10 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München © Infineon Technologies AG 2004. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. 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Dpto.Componentes Ronda de Europa,5 E-28760 Tres Cantos-Madrid T (+34)91-5 14 71 51 Fax (+34)91-5 14 70 13 CoreControl TM MAL Infineon Technologies AG Sdn Bhd Bayan Lepas Free Industrial Zone1 11900 Penang T (+60)4 -6 44 99 75 Fax (+60)4 -6 41 48 72 GB N Infineon Technologies Siemens House Oldbury GB-Bracknell,Berkshire RG12 8FZ T (+44)13 44-39 66 18 Fax (+44)13 44-39 66 32 Siemens Components Scandinavia Østre Aker vei 24 Postboks 10,Veitvet N-0518 Oslo T (+47)22-63 30 00 Fax (+47)22-68 49 13 Email: [email protected] H Simacomp Kft. Lajos u.103 H-1036 Budapest T (+36)1-4 57 16 90 Fax (+36)1-4 57 16 92 NL Siemens Electronic Components Benelux Postbus 16068 NL-2500 BB Den Haag T (+31)70-3 33 20 65 Fax (+31)70-3 33 28 15 Email:[email protected] HK Infineon Technologies Hong Kong Ltd. Suite 302,Level 3, Festival Walk, 80 Tat Chee Avenue, Yam Yat Tsuen, Kowloon Tong Hong Kong T (+8 52)28 32 05 00 Fax (+8 52)28 27 97 62 NZ Siemens Auckland 300 Great South Road Greenland Auckland T (+64)9-5 20 30 33 Fax (+64)9-5 20 15 56 I P Siemens S..A. Semiconductor Sales Via Piero e Alberto Pirelli,10 I-20126 Milano T (+39)02-66 76 -1 Fax (+39)02-66 76 43 95 Siemens S.A. an Componentes Electronicos R.Irmaos Siemens,1 Alfragide P-2720-093 Amadora T (+351)1-4 17 85 90 Fax (+351)1-4 17 80 83 IND Siemens Ltd. Components Division No.84 Keonics Electronic City Hosur Road Bangalore 561 229 T (+91)80-8 52 11 22 Fax (+91)80-8 52 11 80 Siemens Ltd. CMP Div,5th Floor 4A Ring Road,IP Estate New Delhi 110 002 T (+91)11-3 31 99 12 Fax (+91)11-3 31 96 04 Siemens Ltd. CMP Div,4th Floor 130,Pandurang Budhkar Marg, Worli Mumbai 400 018 T (+91)22-4 96 21 99 Fax (+91)22-4 96 22 01 IRL Siemens Ltd. Electronic Components Division 8,Raglan Road IRL-Dublin 4 T (+3 53)1-2 16 23 42 Fax (+3 53)1-2 16 23 49 IL Nisko Ltd. 2A,Habarzel St. P.O.Box 58151 61580 Tel Aviv –Isreal T (+9 72)3 -7 65 73 00 Fax (+9 72)3 -7 65 73 33 PK Siemens Pakistan Engineering Co.Ltd. PO Box 1129,Islamabad 44000 23 West Jinnah Ave Islamabad T (+92)51-21 22 00 Fax (+92)51-21 16 10 PL Siemens SP.z.o.o. ul.Zupnicza 11 PL-03-821 Warszawa T (+48)22-8 70 91 50 Fax (+48)22-8 70 91 59 ROK Siemens Ltd. Asia Tower,10th Floor 726 Yeoksam-dong,Kang-nam Ku CPO Box 3001 Seoul 135-080 T (+82)2-5 27 77 00 Fax (+82)2-5 27 77 79 RUS Infineon Technologies Asia Pacific,Pte.Ltd. 168 Kallang Way Singapore 349 253 T (+65)8 40 06 10 Fax (+65)7 42 62 39 USA Infineon Technologies Corporation 1730 North First Street San Jose,CA 95112 T (+1)4 08-5 01 60 00 Fax (+1)4 08-5 01 24 24 Siemens Components,Inc. Optoelectronics Division 19000 Homestead Road Cupertino,CA 95014 T (+1)4 08-2 57 79 10 Fax (+1)4 08-7 25 34 39 Siemens Components,Inc. Special Products Division 186 Wood Avenue South Iselin,NJ 08830-2770 T (+1)7 32-9 06 43 00 Fax (+1)7 32-6 32 28 30 VRC Infineon Technologies Hong Kong Ltd. Beijing Office Room 2106,Building A Vantone New World Plaza No.2 Fu Cheng Men Wai Da Jie Jie 100037 Beijing T (+86)10 -68 57 90 -06,-07 Fax (+86)10 -68 57 90 08 Infineon Technologies Hong Kong Ltd. Chengdu Office Room14J1,Jinyang Mansion 58 Tidu Street Chengdu, Sichuan Province 610 016 T (+86)28-6 61 54 46 /79 51 Fax (+86)28 -6 61 01 59 Infineon Technologies Hong Kong Ltd. Shanghai Office Room1101,Lucky Target Square No.500 Chengdu Road North Shanghai 200003 T (+86)21-63 6126 18 /19 Fax (+86)21-63 61 11 67 Infineon Technologies Hong Kong Ltd. Shenzhen Office Room 1502,Block A Tian An International Building Renim South Road Shenzhen 518 005 T (+86)7 55 -2 28 91 04 Fax (+86)7 55-2 28 02 17 ZA INTECH electronics ul.Smolnaya,24/1203 RUS-125 445 Moskva T (+7)0 95 -4 51 97 37 Fax (+7)0 95 -4 51 86 08 S Siemens Components Scandinavia Österögatan 1,Box 46 S-164 93 Kista T (+46)8-7 03 35 00 Fax (+46)8-7 03 35 01 Email: [email protected] Page 25 of 25 SGP Siemens Ltd. Components Division P.O.B.3438 Halfway House 1685 T (+27)11-6 52 -27 02 Fax (+27)11-6 52 20 42 DS-CoreControl-TDA21302