RT9237A
Preliminary
Multi-Phase DC/DC Controller for CPU Core Power Supply
General Description
The RT9237A is a multi-phase buck DC/DC
controller integrated with all control functions for
high performance processor VRM. The RT9237A
drives 2, 3 or 4 buck switching stages operating in
interleaved phase set automatically. The multi-phase
architecture provides high output current while
maintaining low power dissipation on power devices
and low stress on input and output capacitors. The
high equivalent operating frequency also reduces
the component dimension and the output voltage
ripple in load transient.
RT9237A regulates both easily set voltage and
current loops. Precise current sharing for power
stage is achieved by differential input current sense
and processing circuit. The settings of current sense,
droop tuning and over current protection are
independent to compensation circuit of voltage loop.
The feature greatly facilitates the flexibility of CPU
power supply design and tuning.
The RT9237A uses a 5-bit DAC of 1.1V to 1.85V
(25mV/step) output with load current droop
compensation to meet the strict VRM transient
requirement. The IC monitors the VCORE voltage
for PGOOD and over voltage protection. Soft start,
over current protection and programmable under
voltage lockout are also provided to assure the
safety of microprocessor and power system.
Features
Multi-Phase Power Conversion with Automatic
Phase Selection
VRM 9.0 DAC Output with Active Droop
Compensation for Fast Load Transient
Precise Channel Current Sharing with
Differential Sense Input
Hiccup Mode Over Current Protection
Programmable Under Voltage Lockout and
Soft Start
High Ripple Frequency, (Channel Frequency
100kHz) Times Channel Number
Pin Configurations
Part Number
RT9237ACS
(Plastic SOP-28)
Pin Configurations
TOP VIEW
VID4
VID3
VID2
VID1
VID0
COMP
FB
ADJ
GND
3
VDD
PGOOD
26 PWM4
4
25
5
24
23
1
28
2
27
6
7
8
9
VSEN 10
IRMP 11
DVD 12
IMAX 13
SS 14
ISP4
ISP1
PWM1
22 PWM2
21 ISP2
20 ISP3
19
PWM3
ISN1
17 ISN2
16 ISN3
18
15
ISN4
Applications
Power Supply for Server and Workstation
Power Supply for High Current Microprocessor
Ordering Information
RT9237A
Package Type
S : SOP-28
Operating Temperature Range
C: Commercial Standard
DS9237A-00 December 2002
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1
RT9237A
Preliminary
Absolute Maximum Ratings
Supply Voltage
Input, Output or I/O Voltage
Ambient Temperature Range
Operating Junction Temperature Range
Storage Temperature Range
Power Dissipation, PD @ TA = 25°C
SOP-28
Package Thermal Resistance
SOP-28, θJA
Lead Temperature (Soldering, 10 sec.)
7V
GND-0.3V ~ VDD+0.3V
0°C ~ 70°C
0°C ~ 125°C
-65°C ~ 150°C
0.625W
60°C /W
260°C
Electrical Characteristics
(VDD = 5V, GND = 0V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
--
5
12
mA
VDD Rising Threshold
4.2
4.35
4.6
V
VDD Falling Threshold
--
3.85
--
V
Hysteresis
0.2
0.6
--
V
VDVD Rising Trip Threshold
1.19
1.25
1.31
V
For each phase
85
100
115
kHz
RIRMP = 112kΩ
--
1
--
V
Ramp Valley
1.0
1.3
--
V
Maximum On Time of Each Channel
70
75
80
%
0.95
1
1.05
V
-1.0
--
+1.0
%
DAC (VID0-VID4) Input Low Voltage
--
--
0.8
V
DAC (VID0-VID4) Input High Voltage
2.0
--
--
V
DAC (VID0-VID4) Bias Current
20
28
36
µA
DC Gain
--
85
--
DB
Bandwidth
--
10
--
MHz
--
5
--
V/µS
VDD Supply Current
Nominal Supply Current
IDD
PWM 1,2,3,4 Open
Power-On Reset
Oscillator
Frequency
Ramp Amplitude
IRMP Pin Voltage
∆VOSC
RIRMP = 50kΩ
Reference and DAC
DACOUT Voltage Accuracy
PWM Controller Error Amplifier
Slew Rate
CL = 10pF
To be continued
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2
DS9237A-00 December 2002
RT9237A
Preliminary
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
ISP 1,2,3,4 Full Scale Source Current
50
--
--
µA
ISP 1,2,3,4 Current for OCP
80
90
--
µA
0.55
0.6
0.65
V
8
13
18
µA
118
122
126
%
Current Sense GM Amplifier
Protection
IMAX Voltage
RIMAX = 15k
SS Current
VSS = 1V
Over-Voltage Trip (VSEN/DACOUT)
Power Good
Upper Threshold (VSEN/DACOUT)
VSEN Rising
106
110
114
%
Lower Threshold (VSEN/DACOUT)
VSEN Rising
86
92
94
%
Function Block Diagram
DVD
IMAX
Pow er On Reset
VDD
IRMP
Oscillator
PGOOD
_
+
+
+
92%
VDAC
PWMCP
INH
OVP, PGOOD
POR Logic
_
108%
VDAC
+
INH
_
DAC
INH
+
_
VID0
VID1
VID2
VID3
VID4
120%
VDAC
_
Balance
Droop
Control
Processor
PWMCP
INH
+
ADJ
Current
_
VSEN
PWMCP
INH
+
Current
Limit
_
PWM Logic
& Driver
PWM1
PWM Logic
& Driver
PWM2
PWM Logic
& Driver
PWM3
PWM Logic
& Driver
PWM4
GND
CS3
CS4
COMP
DS9237A-00 December 2002
+ _
+ _
_
CS2
SS
Control
ISP1
ISN1
ISP2
ISN2
ISP3
ISN3
+ _
+
FB
CS1
+ _
PWMCP
EA
ISP4
ISN4
SS
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3
RT9237A
Preliminary
Table 1 Output Voltage Program
Pin Name
Nominal Output Voltage DACOUT
VID4
VID3
VID2
VID1
VID0
1
1
1
1
1
Off
1
1
1
1
0
1.100V
1
1
1
0
1
1.125V
1
1
1
0
0
1.150V
1
1
0
1
1
1.175V
1
1
0
1
0
1.200V
1
1
0
0
1
1.225V
1
1
0
0
0
1.250V
1
0
1
1
1
1.275V
1
0
1
1
0
1.300V
1
0
1
0
1
1.325V
1
0
1
0
0
1.350V
1
0
0
1
1
1.375V
1
0
0
1
0
1.400V
1
0
0
0
1
1.425V
1
0
0
0
0
1.450V
0
1
1
1
1
1.475V
0
1
1
1
0
1.500V
0
1
1
0
1
1.525V
0
1
1
0
0
1.550V
0
1
0
1
1
1.575V
0
1
0
1
0
1.600V
0
1
0
0
1
1.625V
0
1
0
0
0
1.650V
0
0
1
1
1
1.675V
0
0
1
1
0
1.700V
0
0
1
0
1
1.725V
0
0
1
0
0
1.750V
0
0
0
1
1
1.775V
0
0
0
1
0
1.800V
0
0
0
0
1
1.825V
0
0
0
0
0
1.850V
Note: (1) 0:Connected to GND (2) 1:Open
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4
DS9237A-00 December 2002
DS9237A-00 December 2002
C 14
R 15
39K
12V
R9
1K
R8
R 11
12K
2.4K
C 17
0.1µF
14
13
13K
11
10
9
8
7
6
5
4
12
VID0
VID1
3
VID2
R 12
R 14
33pF
C 12
1.5K
R7
15K
R5
2
VID3
ISN4
ISN3
ISN2
ISN1
PWM3
ISP3
ISP2
PWM2
PWM1
ISP1
ISP4
PWM4
PGOOD
VDD
RT9237A
SS
IMA X
DVD
IRMP
VSEN
GND
ADJ
FB
COMP
VID0
VID1
VID2
VID3
VID4
15
16
17
18
19
20
21
22
23
24
25
26
27
28
2.4K
R13
2.4K
R10
5V
2.4K
R1
2.4K
R2
5V
PGOOD
10K
Ty pical 12V
R3
7
3
C 13
1µF
Ty pical 12V
3
1µF
C4
6
PHASE
PWM
4
GND
5
8
PHASE
LGATE
5
8
BOOT 1
UGATE
2
LGATE
RT9600
PVCC
4
GND
6
VCC
PWM
2
BOOT 1
UGATE
RT9600
VCC
7
PVCC
Q4
PHB95NO3LT
C 11
1µF
Q2
PHB95NO3LT
C3
1µF
C1
1µF
C8
0.01µF
2µH
L3
Q3
PHB83NO3LT
1µF
L2
2µH
0.01µF
Q1
PHB83NO3LT
C2
100µF
2µH
L1
C5
1000µF
C 15
1000µF
C9
100µF
12V
C 16
1000µF
1000µF
C6
VCORE
Typical Application Circuit
C 10
10nF R 6
1
VID4
1µF
C7
+5V
Preliminary
RT9237A
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5
RT9237A
Preliminary
Functional Pin Description
VID4, VID3, VID2, VID1 and VID0 (Pin1,2,3,4,5)
DAC voltage identification inputs for VRM9.0. These
pins are TTL-compatible and internally pulled to VDD
if left open.
COMP (Pin 6)
Output of the error amplifier and input of the PWM
comparator.
ISEN1 (Pin 18), ISEN2 (Pin 17), ISEN3 (Pin 16) and
ISEN4 (Pin 15)
Current sense inputs from the individual converter
channel’s sense component GND nodes.
ISP1 (Pin 24), ISEN2 (Pin 21), ISEN3 (Pin 20) and
ISEN4 (Pin 25)
Current sense inputs for individual converter
channels. Tie this pin to the component sense node.
FB (Pin 7)
Inverting input of the internal error amplifier.
PWM1 (Pin 23), PWM2 (Pin 22), PWM3 (Pin 19)
and PWM4 (Pin 26)
ADJ (Pin 8)
PWM outputs for each driven channel. Connect these
pins to the PWM input of the MOSFET driver. For
systems which use 3 channels, connect PWM4 high.
Two channel systems connect PWM3 and PWM4
high.
Current sense output for active droop adjust.
Connect a resistor from this pin to GND to set the
amount of load droop.
GND (Pin 9)
Ground for the IC.
PGOOD (Pin 27)
Power good open-drain output.
VSEN (Pin 10)
Power good and over voltage monitor input. Connect
to the microprocessor-CORE voltage.
VDD (Pin 28)
IC power supply. Connect this pin to a 5V supply.
IRMP (Pin 11)
PWM ramp amplitude set by external resistor. Ramp
amplitude = 1V × ( 112KΩ / R [IRMP] )
DVD (Pin 12)
Programmable power UVLO detection input. Trip
threshold = 1.25V at V(DVD) rising
IMAX (Pin 13)
Over current protection amplitude set.
SS (Pin 14)
Connect this SS pin to GND with a capacitor to set
the start time interval. Pull this pin below 1V(ramp
valley of saw-tooth wave in pulse width modulator) to
shutdown the converter output.
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DS9237A-00 December 2002
RT9237A
Preliminary
Simplified Block Diagram Control Loops for a Two Phase Converter
+ _
VDAC
PWM2
PWMCP
CS1
GND
SS
Control
CS2
SS
_ +
+ _
Processor
+ _
Current
EA
COMP
PWM Logic
& Driver
PWMCP
Droop
Control
Balance
FB
PWM1
_ +
ADJ
PWM Logic
& Driver
ISP1
ISN1
ISP2
ISN2
VIN
RT9600
R LOAD
C OUT
VIN
RT9600
Voltage loop
Current loop
DS9237A-00 December 2002
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7
RT9237A
Preliminary
Operation
RT9237A is a multi-phase DC/DC controller that
precisely regulates CPU core voltage and balances
the current of different power channels. The
converter consists of RT9237A and its companion
MOSFET driver provide high quality CPU power and
all protection function to meet the requirement of
modern VRM.
Fault detection
The chip detects VCORE for over voltage and power
good detection. The “hiccup mode” operation of over
current protection is adopted to reduce the short
circuit current. The in-rush current at the start up is
suppressed by the soft start circuit through clamping
the pulse width and output voltage.
Voltage control
The reference of VCORE is provided by a 5-bit DAC of
VRM9.0 specification. Control loop consists of error
amplifier, multi-phase pulse width modulator, driver
and power components. Like conventional voltage
mode PWM controller, the output voltage is locked at
the VREF of error amplifier and the error signal is
used as the control signal VC of pulse width
modulator. The PWM signals of different channels
are generated by comparison of EA output and spiltphase saw-tooth wave. Power stage transforms VIN
to output by PWM signal on-time ratio.
Current balance
RT9237A senses the current of low side MOSFET in
each synchronous rectifier when it is conducting for
channel current balance and droop tuning. The
differential sensing GM amplifier converts the voltage
on the sense component (can be a sense resistor or
the RDS(ON) of the low side MOSFET) to current
signal into internal balance circuit. The current
balance circuit sums and averages the current
signals then produces the balancing signals injected
to pulse width modulator. If the current of some
power channel is greater than average, the balancing
signal reduces the output pulse width to keep the
balance.
Application Circuit setting
Phase setting and converter start up
RT9237A interface with companion MOSFET driver
(like RT9600 or HIP660X series) for correct converter
initialization. The tri-phase PWM output (high, low,
high impedance) pins sense the interface voltage at
IC POR acts (both VDD and DVD trip). The channel
is enabled if the pin voltage is 1.2V less than VDD.
Please tie the PWM output to VDD and the current
sense pins to GND or left float if the channel is
unused. For 2-channel application, connect PWM3
and PWM4 high. 3-channel application connect
PWM4 high.
Current sensing setting
RT9237A senses the current of low side MOSFET in
each synchronous rectifier when it is conducting for
channel current balance and droop tuning. The
differential sensing GM amplifier converts the voltage
on the sense component (can be a sense resistor or
the RDS(ON) of the low side MOSFET) to current
signal into internal circuit (see Fig.1).
IX
Load Droop
Sample & Hold
To Current Balance
To Droop Tune
GM
+
The sensed power channel current signals regulate
the reference of DAC to form a output voltage droop
proportional to the load current. The droop or so call
“active voltage positioning” can reduce the output
voltage ripple at load transient and the LC filter size.
_
IBP
IBN
ISPX RSP
RS
ISN X
2/3 IX
RSN
2/3 IX
To Over Current Detection
2/3 IX
Fig.1 Current Sense Circuit
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8
DS9237A-00 December 2002
IL
RT9237A
Preliminary
The sensing circuit gets IX =
IL × RS
by local feedback.
RSP
RSP = RSN to cancel the voltage drop caused by GM
amplifier input bias current. IX is sampled and held
just before low side MOSFET turns off (See Fig.2).
Therefore,
IX (S / H) =
VO TOFF
IL(S / H) × RS
, IL(S / H) = IL( AVG) −
,
×
L
2
RSP
VIN − VO
TOFF =
× 10µS , for operating frequency = 100kHz
VIN
VIN − VO
VO −
× 10µS
V
IN
× RS
IX( S / H) = IL( AVG ) −
2L
RSP
Falling Slope = VO /L
IL
IL (AVG)
PWM Signal & High Side MOSFET Gate Signal
Low Side MOSFET Gate Signal
Fig. 2 Inductor Current and PWM Signal
Droop Tuning
The S/H current signals from power channels are
injected to ADJ pin to create droop voltage.
V ADJ = R ADJ ×
2
3
EA
COUNT = 3
4V
VADJ
VDAC - VADJ
2V
∑
∑ IX
ADJ
R ADJ
SS
V CORE
0V
2/3 IX1
VDAC
_
+
COMP
FB +
Over current protection trip point is set by the resistor
RIMAX connected to IMAX pin. OCP is triggered if one
3
0.6
channel S/H current signal IX> ×
. Controller
2 RIMAX
forces PWM output latched at high impedance to turn
off both high and low side MOSFET in the power
stage and initial the hiccup mode protection. The SS
pin voltage is pulled low with a 10µA current after it is
less than 90% VDD. The converter restarts after SS
pin voltage < 0.2V. Three times of OCP disable the
converter and only release the latch by POR acts
(see Fig.4).
COUNT = 1 COUNT = 2
∑ IX
The DAC output voltage decreases by VADJ to form
the VCORE load droop(see Fig.3).
_
For OVP, the RT9237A detects the VCORE by VSEN
pin. Eliminate the parasitic delay and noise influence
on the PCB path for fast and accurate detection. The
trip point of OVP is 120% of normal output level. The
PWM outputs are pulled low to turn on the low side
MOSFET and turn off the high side MOSFET of the
synchronous rectifier at OVP. The OVP latch can
only be reset by VDD or DVD restart power on reset
sequence. The PGOOD detection trip point of VCORE
is ±8% out of the normal level. The PGOOD open
drain output pulls low when VOCRE exceeds the
range.
Soft start circuit generates a ramp voltage by
charging external capacitor with 10uA current after IC
POR acts. The PWM pulse width and VCORE are
clamped by the rising ramp to reduce the in-rush
current and protect the power devices.
IL (S/H)
Inductor Current
Protection and SS function
OVERLOAD
APPLIED
IL
2/3 IX2
2/3 IX3
2/3 IX4
0A
T0T1
T3T4
T2
TIME
Fig. 4
Fig. 3 Droop Tune Circuit
DS9237A-00 December 2002
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9
RT9237A
Preliminary
3-Phase Converter and Components Function Grouping
12V
VCC
PVCC
BOOT
UGATE
PHASE
RT9600
PWM
LGATE
GND
+5V
VDD
VID
ISP1
Compensation
& Offset
ISN1
VCC
PVCC
COMP
BOOT
+VCORE
UGATE
PHASE
RT9600
FB
VSEN
PWM2
PWM
LGATE
GND
ADJ
Droop Setting
12V
PWM1
RT9237A
12V
Driver Power
UVLO
ISP2
ISN2
DVD
IRMP
ISP3
Ramp Setting
IMA X
OCP Setting
PWM3
12V
SS
ISN3
BOOT
VCC
PVCC
GND
UGATE
PHASE
RT9600
PWM
LGATE
GND
Design Procedure Suggestion
Voltage Loop setting
a. Output filter pole and zero (Inductor, output
capacitor value & ESR)
b. Error amplifier compensation & saw-tooth wave
amplitude(compensation network & IRMP pin
resistor)
Current loop setting
a. GM amplifier S/H current(current sense
component Ron, ISPx & ISNx pin external resistor
value, keep ISPx current < 50uA at full load
condition)
b. Over current protection trip point(IMAX pin resistor,
keep ISPx current<80uA at OCP condition)
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10
Current Sense
Components
VRM load line setting
a. Droop amplitude (ADJ pin resistor)
b. No load offset(additional resistor in compensation
network)
Power sequence & SS
DVD pin external resistor and SS pin capacitor
PCB layout
a. Kelvin sense for current sense GM amplifier
input
b. Refer to layout guide for other item
DS9237A-00 December 2002
RT9237A
Preliminary
Design Example
1. Compensation setting
VIN
Modulator Gain = VRAMP , saw-tooth wave
amplitude VRAMP = 1V × 112kΩ , choose RIRMP
RIMP
= 78K, VRAMP = 1.4V, modulator Gain = 8.6 =
1
ESR zero = πCRESR
2
1
2π LC
= 8.8kHz
= 1.2kHz ,
R2
. Choose R1 = 2.4KΩ, R2 =
R1
24KΩ, C1 = 6.6nF, C2 = 33pF, get FZ = 1KHz,
Fp = 200KHz, mid-band Gain=10=20dB,
shown as Fig. 6.
C3
R3
VCORE
C2
R1
COMP
_
FB
+
EA
DACOUT
0
Compensated EA Gain
PWM Loop Gain
-40
-60
Modulator Gain
10
10
100
100
1K
1000
10K
10000
100K
100000
1M
10M
1000000
10000000
Frequency (Hz)
R 3, C3 are used in type 3
compensation scheme (left
NC in type 2)
R OL
R OL for no load offset
setting
Fig. 5 EA Compensation Network
Full load current of each power channel = 60A/3 =
20Amp, the ripple current = ∆IL =
10µS ×
1 .5 V 1 .5 V
× 1 −
= 6.56 A
12V
2µH
∆IL
, load current at S/H = 20 A − 2 = 16.72A , GM
RDS( ON) × 16.72A
Amp S/H IX(MAX ) =
, suggested IX
RSP
at full = 40µA〜50µA, choose RSP = RSN = 2.4KΩ,
41.8µA×3×2/3×RADJ ，RADJ = 1.44KΩ.
compensation and PWM loop Gain Bode
R2
20
IX(MAX) = 41.8µA, required Droop = 120mV =
modulator asymptotic Bode plot of EA
C1
Uncompensated EA Gain
40
2. Droop setting
C1 × C2
2πR 2(
)
C1 + C2
mid-band gain =
60
Fig. 6 Asymptotic Bode Plot of PWM Loop Gain
b. EA compensation network
Use type 2 compensation scheme (see Fig. 5),
1
1
,FZ =
, FP =
2πR 2C1
80
-20
a. Modulator Gain, Pole and Zero
18.7dB, LC filter pole =
Asymptotic Bode Plot of PWM Loop Gain
100
Gain (dB)
Three phase converter VCORE = 1.5V, VIN = 12V, full
load current = 60Amp, droop voltage at full load =
120mV, OCP trip point for each power stage =
30Amp (at Sample/Hold), low side MOSFET RDS(ON)
= 6mΩ at room temperature, L = 2µH, COUT =
9000µF, capacitor ESR = 2m Ω.
Take the temperature rising for consideration, if
MOSFET working temperature=70°C and the
temperature coefficient =5000ppm/°C, the
RDS(ON)(70°C) = 6mΩ × {1+(70°C-27°C) ×
5000ppm/°C} = 7.3 mΩ, RADJ(70°C) = RADJ(27°C)
× {RDS(ON)(27°C)/RDS(ON)(70°C)} = 1.19KΩ
3. Over Current Protection setting
OCP trip point current = 30A (at Sample/Hold)，
RDS(ON) × 30 A 3 0.6 V ，RIMAX=13.6KΩ
IX =
= ×
RSP
2
RIMAX
Take the temperature rising for consideration,
RIMAX(70°C) = RIMAX(27°C) ×
{RDS(ON)(27°C)/RDS(ON)(70°C)} = 11.2KΩ
4. SS capacitor
CSS = 0.1µF is the suitable value for most
application.
DS9237A-00 December 2002
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11
RT9237A
Preliminary
Layout Guide
Layout Guide
Place the high-power switching components first, and
separate them from sensitive nodes.
1. Most critical path: the current sense circuit is
the most sensitive part of the converter. The
current sense resistors tied to ISP1,2,3,4 and
ISN1,2,3,4 should be located not more than 0.5
inch from the IC and away from the noise
switching nodes. The PCB trace of sense
nodes should be parallel and as short as
possible. Kelvin connection of the sense
component (additional sense resistor or
MOSFET RDS(ON)) ensures the accurate stable
current sensing.
No Kelvin sense, no guarantee
for stable operation!
SW1
2. Switching ripple current path:
a. Input capacitor to high side MOSFET
b. Low side MOSFET to output capacitor
c. The return path of input and output capacitor
d. Separate the power and signal GND
e. The switching nodes(the connection node of
high/low side MOSFET and inductor) is the
most noisy points. Keep them away from
sensitive small-signal node.
f. Reduce parasitic R, L by minimum length,
enough copper thickness and avoiding of via.
3. MOSFET driver should be close to MOSFET
4. The compensation, bypass and other function
setting components should be near the IC and
away from the noisy power path.
L1
VIN
VOUT
R IN
C OUT
C IN
RL
V
SW2
L2
Fig.7 Power Stage Ripple Current Path
www.richtek.com
12
DS9237A-00 December 2002
RT9237A
Preliminary
Next to IC Pin(s)
+12V
+12V or +5V
CBP
PVCC VCC
Use Individual Metal Runs for
Each Channel to help Isolate
Output Stages
CBOOT
LO1
RT9600
PWM
IMAX
IRMP
ADJ
V CORE
CBP
Next to IC Pin(s)
COMP
RT9237A
PHASE
Kelvin
Sense
Parallel Trace
Locate near Transistor
CC
RC
COUT
CIN
+5VIN
VCC
RISP
RISN
Locate next
to IC
FB
RFB
ISPX
ISNX
Locate next
to FB Pin
VSEN
Fig.8 Layout Consideration
DS9237A-00 December 2002
www.richtek.com
13
RT9237A
Preliminary
Package Information
H
M
B
B
J
A
C
F
Symbol
D
I
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
17.704
18.110
0.697
0.713
B
7.391
7.595
0.291
0.299
C
2.362
2.642
0.093
0.104
D
0.330
0.508
0.013
0.020
F
1.194
1.346
0.047
0.053
H
0.229
0.330
0.009
0.013
I
0.102
0.305
0.004
0.012
J
10.008
10.643
0.394
0.419
M
0.381
1.270
0.015
0.050
28–Lead SOP Plastic Package
www.richtek.com
14
DS9237A-00 December 2002
Preliminary
DS9237A-00 December 2002
RT9237A
www.richtek.com
15
RT9237A
Preliminary
RICHTEK TECHNOLOGY CORP.
RICHTEK TECHNOLOGY CORP.
Headquarter
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
8F-1, No. 137, Lane 235, Paochiao Road, Hsintien City
Hsinchu, Taiwan, R.O.C.
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)89191466 Fax: (8862)89191465
Email: [email protected]
www.richtek.com
16
DS9237A-00 December 2002