ETC RT9241B

RT9241A/B
Two-Phase DC/DC Controller for CPU Core Power Supply
General Description
The RT9241A/B is a two-phase buck DC/DC
controller integrated with all control functions for high
performance processor VRM. The RT9241A/B
drives 2 buck switching stages operating in 180
degree phase shift. The two-phase architecture
provides high output current while maintaining low
power dissipation on power devices and low stress
on input and output capacitors. The high equivalent
operating frequency also reduces the component
dimension and the output voltage ripple in load
transient.
RT9241A/B regulates both easily set voltage and
current loops. Precise current sharing for power stage
is achieved by differential input current sense and
processing circuit. The settings of current sense,
droop tuning and over current protection are
independent to compensation circuit of voltage loop.
The feature greatly facilitates the flexibility of CPU
power supply design and tuning.
The RT9241A/B uses a 5-bit DAC of 1.1V to 1.85V
(25mV/step) output with load current droop
compensation to meet the strict VRM transient
requirement. The IC monitors the VCORE voltage for
PGOOD and over voltage protection. Soft start, over
current protection and programmable under voltage
lockout are also provided to assure the safety of
microprocessor and power system.
Ordering Information
Features
Two-Phase Power Conversion
VRM 9.0 DAC Output with Active Droop
Compensation for Fast Load Transient
Precise Channel Current Sharing with
Differential Sense Input
Hiccup Mode Over Current Protection
Programmable Under Voltage Lockout and Soft
Start
High Ripple Frequency, (Channel Frequency
Times Channel Number)
100KHz Version (RT9241B) for Lower Switching
Loss
Applications
Power Supply for Server and Workstation
Power Supply for High Current Microprocessor
Pin Configurations
Part Number
Pin Configurations
RT9241A/B CS
TOP VIEW
(Plastic SOP-20)
VID4
1
20
VDD
VID3
2
19
PGOOD
VID2
3
18
ISP1
VID1
4
17
PWM1
VID0
5
16
PWM2
COMP
6
15
ISP2
FB
7
14
VSEN
ADJ
8
13
DVD
9
12
GND
ISN1
10
11
ISN2
SS
RT9241A/B
Package type
S : SOP-20
Operating temperature range
C: Commercial standard
Operating frequency version
A : 200KHz
B : 100KHz
DS9241AB-01
October 2002
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1
RT9241A/B
Absolute Maximum Ratings
Supply Voltage
Input, Output or I/O Voltage
Power Dissipation, PD @ TA = 25°C
SOP-20
Package Thermal Resistance
SOP-20, θJA
Ambient Temperature Range
Junction Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec.)
7V
GND-0.3V ~ VDD+0.3V
0.625W
110°C /W
0°C ~ 70°C
0°C ~ 125°C
-40°C ~ 150°C
260°C
Electrical Characteristics
(VDD = 5V, GND = 0V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
--
4
10
mA
VDD Rising Threshold
4.2
4.35
4.6
V
VDD Falling Threshold
--
3.85
--
V
Hysteresis
0.2
0.6
--
V
VDVD Rising Trip Threshold
1.19
1.25
1.31
V
170
200
230
85
100
115
--
1.7
--
V
Ramp Valley
1.0
1.3
--
V
Maximum On Time of Each Channel
70
75
80
%
-1.0
--
+1.0
%
DAC (VID0-VID4) Input Low Voltage
--
--
0.8
V
DAC (VID0-VID4) Input High Voltage
2.0
--
--
V
DAC (VID0-VID4) Bias Current
20
28
36
µA
DC Gain
--
85
--
dB
Bandwidth
--
10
--
MHz
--
5
--
V/µS
VDD Supply Current
Nominal Supply Current
IDD
PWM 1,2 Open
Power-On Reset
Oscillator
Frequency
RT9241A
RT9241B
For each phase
Ramp Amplitude
kHz
Reference and DAC
DACOUT Voltage Accuracy
PWM Controller Error Amplifier
Slew Rate
CL = 10pF
To be continued
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2
DS9241AB-01
October 2002
RT9241A/B
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
ISP 1,2 Full Scale Source Current
50
--
--
µA
ISP 1,2 Current for OCP
70
75
--
µA
8
13
18
µA
118
122
126
%
Current Sense GM Amplifier
Protection
SS Current
VSS = 1V
Over-Voltage Trip (VSEN/DACOUT)
Power Good
Upper Threshold (VSEN/DACOUT)
VSEN Rising
106
110
114
%
Lower Threshold (VSEN/DACOUT)
VSEN Rising
86
90
94
%
Function Block Diagram
DVD
Pow er On Reset
VDD
Oscillator
Balance
_
Processor
CS1
Droop
Control
CS2
ISP1
ISN1
ISP2
ISN2
+
SS
Control
EA
_
FB
PWM2
PWMCP
VSEN
ADJ
PWM Logic
& Driver
+
Current
Limit
Current
PWM1
_
_
PWMCP
INH
PWM Logic
& Driver
_
_
+
92%
VDAC
OVP, PGOOD
POR Logic
_
+
108%
VDAC
INH
_
+
DAC
INH
+
120%
VDAC
+
VID0
VID1
VID2
VID3
VID4
+
PGOOD
GND
COMP
DS9241AB-01
October 2002
SS
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3
RT9241A/B
Table 1 Output Voltage Program
Pin Name
Nominal Output Voltage DACOUT
VID4
VID3
VID2
VID1
VID0
1
1
1
1
1
Off
1
1
1
1
0
1.100V
1
1
1
0
1
1.125V
1
1
1
0
0
1.150V
1
1
0
1
1
1.175V
1
1
0
1
0
1.200V
1
1
0
0
1
1.225V
1
1
0
0
0
1.250V
1
0
1
1
1
1.275V
1
0
1
1
0
1.300V
1
0
1
0
1
1.325V
1
0
1
0
0
1.350V
1
0
0
1
1
1.375V
1
0
0
1
0
1.400V
1
0
0
0
1
1.425V
1
0
0
0
0
1.450V
0
1
1
1
1
1.475V
0
1
1
1
0
1.500V
0
1
1
0
1
1.525V
0
1
1
0
0
1.550V
0
1
0
1
1
1.575V
0
1
0
1
0
1.600V
0
1
0
0
1
1.625V
0
1
0
0
0
1.650V
0
0
1
1
1
1.675V
0
0
1
1
0
1.700V
0
0
1
0
1
1.725V
0
0
1
0
0
1.750V
0
0
0
1
1
1.775V
0
0
0
1
0
1.800V
0
0
0
0
1
1.825V
0
0
0
0
0
1.850V
Note: (1) 0:Connected to GND (2) 1:Open
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DS9241AB-01
October 2002
DS9241AB-01
October 2002
C14
12V
R9
1K
R8
2.4K
R5
13K
R12
R7
R14
2.4K
33pF
C12
24K
C10
6.6nF R
6
ADJ
FB
COMP
VID0
VID1
VID2
VID3
VID4
10
9
14
SS
PWM2
ISN2
ISP2
ISN1
ISP1
PWM1
PGOOD
VDD
RT9241A
DVD
VSEN
13 GND
8
7
6
5
C17
0.1µF
VID0
4
3
VID2
VID1
2
VID3
1
16
11
15
12
18
17
19
20
R1
2.4K
R13
2.4K
R2
2.4K
R10
2.4K
PGOOD
Typical 12V
R3
10K
6
3
PHASE
PWM
6
PWM
4
GND
5
PHASE
LGATE
5
8
2
BOOT
1
UGATE
LGATE
RT9600
4
GND
8
2
BOOT
1
UGATE
RT9600
VCC
PVCC
7 VCC
PVCC
C13
1µF
Typical 12V
3
C4
1µF
7
Q4
PHB95N03LT
C11
1µF
Q2
PHB95N03LT
C3
1µF
C1
1µF
0.01µF
2µH
L3
Q3
PHB83N03LT
C8
1µF
2µH
L2
0.01µF
Q1
PHB83N03LT
C2
1000µF/16V
1µH
L1
C5
1500µF
C15
1500µF
C9
1000µF
12V
C16
1500µF
C6
1500µF
VCORE
Typical Application Circuit
R15
+5V
VID4
C7
1µF
+5V
RT9241A/B
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5
12V
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6
13K
2.4K
+5V
2.4K
33pF
24K
6.6nF
9
8
7
6
5
0.1µF
10
2.4K
VID0
4
3
VID2
VID1
2
1
VID3
VID4
SS
PWM2
ISN2
ISP2
GND
VSEN
ISN1
ISP1
PWM1
PGOOD
VDD
RT9241A
DVD
ADJ
FB
COMP
VID0
VID1
VID2
VID3
VID4
13
14
12
18
17
19
20
16
11
15
1µF
3K
3K
3K
3K
+5V
PGOOD
10K
2µH
2µH
1000µF
×1500µF
1000µF
×1500µF
1.2µH
VCORE
12V
PHB95N03LT
0.01µF
PHB83N03LT
1µF
PHB95N03LT
1µF
13
12
1µF
11
PHASE2
UGATE2
PWM1
PVCC
PGND
GND
PWM2
10
BOOT2
7 LGATE 2
8
9
14
VCC
RT9602
PHASE1
UGATE1
BOOT1
4 LGATE 1
0.01µF
PHB83N03LT
1µF
6
3
2
1
5
1µF
10
12V
RT9241A/B
DS9241AB-01
October 2002
RT9241A/B
Typical Operating Characteristics
Over Current Protection at Power-Up
Over Current Protection at Steady State
PWM1
PWM1
PWM2
PWM2
VSS
VSS
20A/DIV)
IOUT
20A/DIV)
IOUT
Time (25mS/DIV)
Time (25mS/DIV)
Current Sharing between Two Phases
Two-Phase Converter without Current Sharing
PWM1
PWM1
PWM2
PWM2
IL1
IL2
IL1
IL2
IL1
IL2
IL1
IL2
Time (5μS/DIV)
The Hysteresis of VDD
1.6
1.4
1.4
1.2
1.2
1
1
0.8
0.6
0.8
0.6
0.4
0.4
0.2
0.2
0
0
1
2
3
VDD (V)
DS9241AB-01
October 2002
4
The Hysteresis of VDVD
1.6
VCORE (V)
VCORE (V)
Time (5μS/DIV)
5
6
0.9
1
1.1
1.2
1.3
1.4
1.5
VDVD (V)
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RT9241A/B
Functional Pin Description
VID4, VID3, VID2, VID1 and VID0 ( Pin1,2,3,4,5)
DAC voltage identification inputs for VRM9.0. These
pins are TTL-compatible and internally pulled to VDD
if left open.
PGOOD (Pin 19)
Power good open-drain output.
VDD (Pin 20)
IC power supply. Connect this pin to a 5V supply.
COMP (Pin 6)
Output of the error amplifier and input of the PWM
comparator.
FB (Pin 7)
Inverting input of the internal error amplifier.
ADJ (Pin 8)
Current sense output for active droop adjust. Connect
a resistor from this pin to GND to set the amount of
load droop. This pin should not be opened.
DVD (Pin 9)
Programmable power UVLO detection input. Trip
threshold = 1.25V at VDVD rising
SS (Pin 10)
Connect this SS pin to GND with a capacitor to set the
start time interval. Pull this pin below 1V(ramp valley
of saw-tooth wave in pulse width modulator) to
shutdown the converter output.
ISN1 (Pin 12), ISN2 (Pin 11)
Current sense inputs from the individual converter
channel’s sense component GND nodes.
GND (Pin 13)
Ground for the IC.
VSEN (Pin 14)
Power good and over voltage monitor input. Connect
to the microprocessor-CORE voltage.
ISP1 (Pin 18), ISP2 (Pin 15)
Current sense inputs for individual converter channels.
Tie this pin to the component sense node.
PWM1 (Pin 17), PWM2 (Pin 16)
PWM outputs for each driven channel. Connect these
pins to the PWM input of the MOSFET driver.
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DS9241AB-01
October 2002
RT9241A/B
Simplified Block Diagram Control Loops for a Two Phase Converter
+
_
VDAC
Droop
ADJ
Control
PWM Logic
& Driver
PWM2
Balance
_
PWMCP
CS1
GND
+
Processor
_
SS
Control
CS2
SS
+
_
_
EA
COMP
PWM1
PWMCP
Current
+
+
FB
PWM Logic
& Driver
ISP1
ISN1
ISP2
ISN2
VIN
RT9600
RLOAD
COUT
VIN
RT9600
Voltage loop
Current loop
DS9241AB-01
October 2002
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9
RT9241A/B
RT9241A/B is a two-phase DC/DC controller that
precisely regulates CPU core voltage and balances
the current of different power channels. The converter
consists of RT9241A/B and its companion MOSFET
driver provide high quality CPU power and all
protection function to meet the requirement of modern
VRM.
Voltage control
The reference of VCORE is provided by a 5-bit DAC of
VRM9.0 specification. Control loop consists of error
amplifier, two-phase pulse width modulator, driver and
power components. Like conventional voltage mode
PWM controller, the output voltage is locked at the
VREF of error amplifier and the error signal is used as
the control signal VC of pulse width modulator. The
PWM signals of different channels are generated by
comparison of EA output and split-phase saw-tooth
wave. Power stage transforms VIN to output by PWM
signal on-time ratio.
Current balance
RT9241A/B senses the current of low side MOSFET
in each synchronous rectifier when it is conducting for
channel current balance and droop tuning. The
differential sensing GM amplifier converts the voltage
on the sense component (can be a sense resistor or
the RDS(ON) of the low side MOSFET) to current
signal into internal balance circuit. The current
balance circuit sums and averages the current signals
then produces the balancing signals injected to pulse
width modulator. If the current of some power channel
is greater than average, the balancing signal reduces
the output pulse width to keep the balance.
Load droop
The sensed power channel current signals regulate
the reference of DAC to form a output voltage droop
proportional to the load current. The droop or so call
“active voltage positioning” can reduce the output
voltage ripple at load transient and the LC filter size.
Fault detection
The chip detects VCORE for over voltage and power
good detection. The “hiccup mode” operation of over
current protection is adopted to reduce the short
circuit current. The in-rush current at the start up is
suppressed by the soft start circuit through clamping
the pulse width and output voltage.
Application Circuit Setting
MOSFET driver detection and converter start up
RT9241A/B interface with companion MOSFET driver
(like RT9600 or HIP660X series) for correct converter
initialization. The tri-phase PWM output (high, low,
high impedance) pins sense the interface voltage at
IC POR acts (both VDD and VDVD trip). The channel is
enabled if the pin voltage is 1.2V less than VDD.
Please tie the both PWM output to driver input for
correct converter start-up.
Current sensing setting
RT9241A/B senses the current of low side MOSFET
in each synchronous rectifier when it is conducting for
channel current balance and droop tuning. The
differential sensing GM amplifier converts the voltage
on the sense component (can be a sense resistor or
the RDS(ON) of the low side MOSFET) to current
signal into internal circuit (see Fig.1).
IX
_
Sample & Hold
To Current Balance
To Droop Tune
GM
+
Operation
IBP
IBN
ISPX RSP
RS
ISN X
2/3 IX
RSN
2/3 IX
To Over Current Detection
2/3 IX
Fig.1 Current Sense Circuit
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10
DS9241AB-01
October 2002
IL
RT9241A/B
IL × RS
by local
The sensing circuit gets IX =
RSP
feedback. RSP = RSN to cancel the voltage drop
caused by GM amplifier input bias current. IX is
sampled and held just before low side MOSFET turns
off (See Fig.2). Therefore,
IL(S / H) × RS
VO TOFF
×
IL(S / H) = IL( AVG) −,
IX(S / H) =
2
RSP
, L
 VIN − VO 
×
TOFF = 
 VIN 
TS, for switching
period = TS


 VIN − VO 
VO − 
× TS 

 VIN 
 × RS
IX(S / H) = IL( AVG ) −

 RSP
2L




Falling Slope = VO /L
IL
IL (AVG)
IL (S/H)
Inductor Current
Soft start circuit generates a ramp voltage by charging
external capacitor with 10uA current after IC POR
acts. The PWM pulse width and VCORE are clamped
by the rising ramp to reduce the in-rush current and
protect the power components.
OCP is triggered if one channel S/H current signal IX>
75µA. Controller forces PWM output latched at high
impedance to turn off both high and low side
MOSFET in the power stage and initial the hiccup
mode protection. The SS pin voltage is pulled low with
a 10µA current after it is less than 90% VDD. The
converter restarts after SS pin voltage < 0.2V. Three
times of OCP disable the converter and only release
the latch by POR acts (see Fig.4).
PWM Signal & High Side MOSFET Gate Signal
Low Side MOSFET Gate Signal
Fig. 2 Inductor Current and PWM Signal
Droop tuning
The S/H current signals from power channels are
injected to ADJ pin to create droop voltage.
V ADJ = R ADJ ×
Protection and SS function
For OVP, the RT9241A/B detects the VCORE by VSEN
pin. Eliminate the parasitic delay and noise influence
on the PCB path for fast and accurate detection. The
trip point of OVP is 120% of normal output level. The
PWM outputs are pulled low to turn on the low side
MOSFET and turn off the high side MOSFET of the
synchronous rectifier at OVP. The OVP latch can only
be reset by VDD or VDVD restart power on reset
sequence. The PGOOD detection trip point of VCORE
is ±8% out of the normal level. The PGOOD open
drain output pulls low when VOCRE exceeds the
range.
2
∑ IX
3
COUNT = 1 COUNT = 2
COUNT = 3
4V
2V
0V
The DAC output voltage decreases by VADJ to form
the VCORE load droop(see Fig.3).
SS
V CORE
OVERLOAD
APPLIED
IL
0A
_
EA
FB +
_
+
COMP
VDAC
VADJ
VDAC - VADJ
∑
∑ I
X
2/3 IX1
T0T1
T3T4
T2
TIME
2/3 IX2
Fig. 4
ADJ
RADJ
Fig. 3 Droop Tune Circuit
DS9241AB-01
October 2002
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11
RT9241A/B
Two-Phase Converter and Components Function Grouping
12V
VCC
PVCC
BOOT
UGATE
PHASE
RT9600
PWM
+5V
LGATE
GND
VDD
VID
12V
PWM1
Compensation
& Offset
ISP1
COMP
ISN1
PVCC
FB
ADJ
Driver Power
UVLO
+VCORE
UGATE
RT9600
PWM2
RT9241A/B
12V
BOOT
PHASE
VSEN
Droop Setting
VCC
PWM
LGATE
GND
DVD
Current Sense
Components
ISP2
ISN2
SS
GND
Design Procedure Suggestion
Voltage loop setting
a. Output filter pole and zero (Inductor, output
capacitor value & ESR)
b. Error amplifier compensation network
Current loop setting
a. Over current protection trip point setting by GM
amplifier S/H current(current sense component
Ron, ISPx & ISNx pin external resistor value, keep
ISPx current = 75µA at OCP condition)
Power sequence & SS
DVD pin external resistor and SS pin capacitor
PCB layout
a. Kelvin sense for current sense GM amplifier
input
b. Refer to layout guide for other item
VRM load line setting
a. Droop amplitude (ADJ pin resistor)
b. No load offset (additional resistor in compensation
network)
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DS9241AB-01
October 2002
RT9241A/B
Design Example for RT9241A
1. Compensation setting
a. Modulator Gain, Pole and Zero
Asymptotic Bode Plot of PWM Loop Gain
100
80
60
Gain (dB)
Two phase converter VCORE = 1.5V, VIN = 12V, full load
current = 40Amp, droop voltage at full load = 120mV,
OCP trip point for each power stage = 30Amp (at
Sample/Hold), low side MOSFET RDS(ON) = 6mΩ at
room temperature, L = 2µH, COUT = 9000µF,
capacitor ESR = 2mΩ.
20
0
VIN
-40
saw-tooth wave amplitude VRAMP = 1.7V,
-60
modulator Gain = 8.6 = 18.7dB
1
2π LC
= 1.2kHz
,
R2
mid-band gain =
R1
Modulator Gain
10
10
100
100
1K
1000
10K
10000
100K
100000
1M
10M
1000000
10000000
Fig. 6 Asymptotic Bode Plot of PWM Loop Gain
2. Over Current Protection setting
b. EA compensation network
Use type 2 compensation scheme (see Fig. 5),
1
,FZ =
, 1
FP =
2πR 2(
PWM Loop Gain
Frequency (Hz)
1
ESR zero = πCRESR = 8.8kHz
2
2πR 2C1
Compensated EA Gain
-20
Modulator Gain = VRAMP
LC filter pole =
Uncompensated EA Gain
40
C1 × C2
)
C1 + C2
. Choose R1 = 2.4KΩ,
R2 = 24KΩ, C1 = 6.6nF, C2 = 33pF, get FZ = 1KHz,
Fp = 200KHz, mid-band Gain=10=20dB,
OCP trip point current = 30A (at Sample/Hold)，
IX =
RDS(ON) × 30 A
= 75µ,A RISP = 2.4KΩ
RSP
Take the temperature rising for consideration, if
MOSFET working temperature=70°C and the
temperature coefficient =5000ppm/°C, RISP(70°C)
= RISP(27°C) × {RDS(ON)(70°C)/RDS(ON)(27°C)} =
1.75KΩ
3. Droop setting
modulator asymptotic Bode plot of EA
compensation and PWM loop Gain Bode shown
as Fig. 6.
Full load current of each power channel = 40A/2 =
20Amp, the ripple current = ∆IL =
1.5 V  1.5 V 
× 1 −
 = 3.28 A
2µH 
12V 
∆IL
, load current at S/H 20 A − 2 = 18.36 A
RDS(ON) × 18.36 A
IX(MAX ) =
=
, GM Amp
RISP
5µS ×
C1
C3
R2
R3
VCORE
C2
R1
S/H
COMP
_
FB
+
EA
DACOUT
R 3, C3 are used in type 3
compensation scheme (left
NC in type 2)
R OL
R OL for no load offset
setting
,
RISP = RISN = 2.4KΩ, IX(MAX) = 46µA, required Droop
= 120mV = 46µA×2×2/3×RADJ ，RADJ = 1.97KΩ.
Take the temperature rising for consideration, we
just modify RISP like OCP setting.
4. SS capacitor
Fig. 5 EA Compensation Network
DS9241AB-01
October 2002
CSS = 0.1µF is the suitable value for most
application.
www.richtek.com
13
RT9241A/B
Layout Guide
Layout Guide
Place the high-power switching components first, and
separate them from sensitive nodes.
1. Most critical path: the current sense circuit is
the most sensitive part of the converter. The
current sense resistors tied to ISP1,2 and
ISN1,2, should be located not more than 0.5
inch from the IC and away from the noise
switching nodes. The PCB trace of sense
nodes should be parallel and as short as
possible. Kelvin connection of the sense
component (additional sense resistor or
MOSFET RDS(ON)) ensures the accurate stable
current sensing.
No
Kelvin
sense,
no
guarantee
for
stable
Switching ripple current path:
a. Input capacitor to high side MOSFET
b. Low side MOSFET to output capacitor
c. The return path of input and output capacitor
d. Separate the power and signal GND
e. The switching nodes(the connection node of
high/low side MOSFET and inductor) is the
most noisy points. Keep them away from
sensitive small-signal node.
f. Reduce parasitic R, L by minimum length,
enough copper thickness and avoiding of via.
2. MOSFET driver should be close to MOSFET
4.The compensation, bypass and other function
setting components should be near the IC and
away from the noisy power path.
operation!
SW1
L1
VIN
VOUT
R IN
C OUT
C IN
RL
V
SW2
L2
Fig.7 Power Stage Ripple Current Path
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14
DS9241AB-01
October 2002
RT9241A/B
Next to IC Pin(s)
+12V
+12V or +5V
CBP
PVCC VCC
CBOOT
Use Individual Metal Runs for
Each Channel to help Isolate
Output Stages
PWM
+5VIN
VCC
CBP
Next to IC Pin(s)
LO1
RT9600
ADJ
VCORE
PHASE
CIN
Parallel Trace
Locate near Transistor
CC1
RT9241A/B
COUT
Kelvin
Sense
COMP
RISP
RISN
Locate next
to IC
RC
FB
RFB
ISPX
ISNX
CC2
Locate next
to FB Pin
VSEN
Fig.8 Layout Consideration
DS9241AB-01
October 2002
www.richtek.com
15
RT9241A/B
Package Information
H
M
B
B
J
A
C
F
Symbol
D
I
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
12.598
13.005
0.496
0.512
B
7.391
7.595
0.291
0.299
C
2.362
2.642
0.093
0.104
D
0.330
0.508
0.013
0.020
F
1.194
1.346
0.047
0.053
H
0.229
0.330
0.009
0.013
I
0.102
0.305
0.004
0.012
J
10.008
10.643
0.394
0.419
M
0.381
1.270
0.015
0.050
20–Lead SOP Plastic Package
www.richtek.com
16
DS9241AB-01
October 2002
RT9241A/B
DS9241AB-01
October 2002
www.richtek.com
17
RT9241A/B
RICHTEK TECHNOLOGY CORP.
RICHTEK TECHNOLOGY CORP.
Headquarter
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
8F-1, No. 137, Lane 235, Paochiao Road, Hsintien City
Hsinchu, Taiwan, R.O.C.
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)89191466 Fax: (8862)89191465
Email: [email protected]
www.richtek.com
18
DS9241AB-01
October 2002