Precision Instrumentation Amplifier AD8221 Available in space-saving MSOP package Gain set with 1 external resistor (gain range 1 to 1000) Wide power supply range: ±2.3 V to ±18 V Temperature range for specified performance: –40°C to +85°C Operational up to 125°C1 EXCELLENT AC SPECIFICATONS 80 dB min CMRR to 10 kHz ( G = 1) 825 kHz –3 dB bandwidth (G = 1) 2 V/µs slew rate LOW NOISE 8 nV/√Hz, @ 1 kHz, max input voltage noise 0.25 µV p-p input noise (0.1 Hz to 10 Hz) HIGH ACCURACY DC PERFORMANCE (AD8221BR) 90 dB min CMRR (G = 1) 25 µV max input offset voltage 0.3 µV/°C max input offset drift 0.4 nA max input bias current –IN 1 8 +VS RG 2 7 VOUT RG 3 6 REF +IN 4 5 –VS AD8221 TOP VIEW 03149-0-001 CONNECTION DIAGRAM FEATURES Figure 1. SOIC and MSOP Connection Diagram 120 110 AD8221 CMRR (dB) 100 90 COMPETITOR 1 80 70 APPLICATIONS 60 Weigh scales Industrial process controls Bridge amplifiers Precision data acquisition systems Medical instrumentation Strain gages Transducer interfaces GENERAL DESCRIPTION The AD8221 is a gain programmable, high performance instrumentation amplifier that delivers the industry’s highest CMRR over frequency. The CMRR of instrumentation amplifiers on the market today falls off at 200 Hz. In contrast, the AD8221 maintains a minimum CMRR of 80 dB to 10 kHz for all grades at G = 1. High CMRR over frequency allows the AD8221 to reject wideband interference and line harmonics, greatly simplifying filter requirements. Possible applications include precision data acquisition, biomedical analysis, and aerospace instrumentation. Low voltage offset, low offset drift, low gain drift, high gain accuracy, and high CMRR make this part an excellent choice in applications that demand the best dc performance possible, such as bridge signal conditioning. COMPETITOR 2 40 10 100 1k 10k FREQUENCY (Hz) 100k 03149-0-002 50 Figure 2. Typical CMRR vs. Frequency for G = 1 Programmable gain affords the user design flexibility. A single resistor sets the gain from 1 to 1000. The AD8221 operates on both single and dual supplies, and is well suited for applications where ±10 V input voltages are encountered. The AD8221 is available in low cost 8-lead SOIC and MSOP packages, both of which offer the industry’s best performance. The MSOP requires half the board space of the SOIC, making it ideal for multichannel or space-constrained applications. Performance is specified over the entire industrial temperature range of –40°C to +85°C for all grades. Furthermore, the AD8221 is operational from –40°C to +125°C1. 1 See Typical Performance Curves for expected operation from 85°C to 125°C. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. AD8221 TABLE OF CONTENTS Specifications..................................................................................... 3 Input Protection ......................................................................... 15 Absolute Maximum Ratings............................................................ 5 RF Interference ........................................................................... 16 ESD Caution.................................................................................. 5 Precision Strain Gage................................................................. 16 Typical Performance Characteristics ............................................. 6 Conditioning ±10 V Signals for a +5 V Differential Input ADC ............................................................................................. 17 Theory of Operation ...................................................................... 13 Gain Selection ............................................................................. 14 Layout........................................................................................... 14 Reference Terminal .................................................................... 15 AC-Coupled Instrumentation Amplifier ................................ 17 Outline Dimensions ....................................................................... 18 Ordering Guide .......................................................................... 18 Power Supply Regulation and Bypassing ................................ 15 Input Bias Current Return Path................................................ 15 REVISION HISTORY Revision A 11/03—Data Sheet Changed from Rev. 0 to Rev. A Change Page Changes to Features...............................................................................1 Changes to Specifications section .......................................................4 Change to Theory of Operation section...........................................13 Change to Gain Selection section......................................................14 Rev. A | Page 2 of 20 AD8221 SPECIFICATIONS Table 1. VS = ±15 V, VREF = 0 V, TA = +25°C, G = 1, RL = 2 kΩ, unless otherwise noted Parameter COMMON-MODE REJECTION RATIO (CMRR) CMRR DC to 60 Hz with 1 kΩ Source Imbalance G=1 G = 10 G = 100 G = 1000 CMRR at 10 kHz G=1 G = 10 G = 100 G = 1000 NOISE Voltage Noise, 1 kHz Input Voltage Noise, eNI Output Voltage Noise, eNO RTI G=1 G = 10 G = 100 to 1000 Current Noise VOLTAGE OFFSET1 Input Offset, VOSI Over Temperature Average TC Output Offset, VOSO Over Temperature Average TC Offset RTI vs. Supply (PSR) G=1 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current Over Temperature Average TC Input Offset Current Over Temperature Average TC REFERENCE INPUT RIN IIN Voltage Range Gain to Output POWER SUPPLY Operating Range Quiescent Current Over Temperature Conditions Min AR Grade Typ Max Min BR Grade Typ Max ARM Grade Min Typ Max Unit VCM = –10 V to +10 V 80 100 120 130 90 110 130 140 80 100 120 130 dB dB dB dB 80 90 100 100 80 100 110 110 80 90 100 100 dB dB dB dB VCM = –10 V to +10 V RTI noise = √eNI2 + (eNO/G)2 VIN+, VIN–, VREF = 0 8 75 8 75 8 75 nV/√Hz nV/√Hz f = 0.1 Hz to 10 Hz 2 0.5 0.25 40 6 f = 1 kHz f = 0.1 Hz to 10 Hz VS = ±5 V to ±15 V T = –40°C to +85°C 2 0.5 0.25 40 6 60 86 0.4 300 0.66 6 VS = ±5 V to ±15 V T = –40°C to +85°C 2 0.5 0.25 40 6 25 45 0.3 200 0.45 5 µV p-p µV p-p µV p-p fA/√Hz pA p-p 70 135 0.9 600 1.00 9 µV µV µV/°C µV mV µV/°C VS = ±2.3 V to ±18 V 90 110 124 130 110 120 130 140 0.5 T = –40°C to +85°C 1 0.2 T = –40°C to +85°C 94 114 130 140 1.5 2.0 0.2 1 0.1 0.6 0.8 1 20 50 VIN+, VIN–, VREF = 0 –VS T = –40°C to +85°C ±2.3 0.9 1 90 100 120 120 0.4 1 60 +VS 20 50 –VS 3 0.3 0.4 0.6 Rev. A | Page 3 of 20 ±2.3 0.9 1 dB dB dB dB 2 3 1 1.5 3 60 +VS 20 50 –VS 1 ± 0.0001 ±18 1 1.2 100 120 140 140 0.5 1 1 ± 0.0001 VS = ±2.3 V to ±18 V 110 130 140 150 60 +VS kΩ µA V V/V ±18 1 1.2 V mA mA 1 ± 0.0001 ±18 1 1.2 ±2.3 0.9 1 nA nA pA/°C nA nA pA/°C AD8221 AR Grade Parameter DYNAMIC RESPONSE Small Signal –3 dB Bandwidth G=1 G = 10 G = 100 G = 1000 Settling Time 0.01% G = 1 to 100 G = 1000 Settling Time 0.001% G = 1 to 100 G = 1000 Slew Rate GAIN Gain Range Gain Error G=1 G = 10 G = 100 G = 1000 Gain Nonlinearity G = 1 to 10 G = 100 G = 1000 G = 1 to 100 Gain vs. Temperature G=1 G > 12 INPUT Input Impedance Differential Common Mode Input Operating Voltage Range3 Over Temperature Input Operating Voltage Range Over Temperature OUTPUT Output Swing Over Temperature Output Swing Over Temperature Short-Circuit Current TEMPERATURE RANGE Specified Performance Operational4 Conditions Min Typ Max BR Grade Min Typ ARM Grade Max Min Typ Max Unit 825 562 100 14.7 825 562 100 14.7 825 562 100 14.7 kHz kHz kHz kHz 10 80 10 80 10 80 µs µs 13 110 2 2.5 13 110 2 2.5 13 110 2 2.5 µs µs V/µs V/µs 10 V Step 10 V Step G=1 G = 5–100 G = 1 + (49.4 kΩ/RG) 1.5 2 1 1.5 2 1000 1 1.5 2 1000 1 1000 V/V 0.1 0.3 0.3 0.3 % % % % VOUT ±10 V 0.03 0.3 0.3 0.3 VOUT = –10 V to +10 V RL = 10 kΩ RL = 10 kΩ RL = 10 kΩ RL = 2 kΩ 0.02 0.15 0.15 0.15 3 5 10 10 10 15 40 95 3 5 10 10 10 15 40 95 5 7 10 15 15 20 50 100 ppm ppm ppm ppm 3 10 –50 2 5 –50 3 10 –50 ppm/°C ppm/°C 100||2 100||2 100||2 100||2 VS = ±2.3 V to ±5 V –VS + 1.9 +VS – 1.1 –VS + 1.9 +VS – 1.1 –VS + 1.9 +VS – 1.1 GΩ||pF GΩ||pF V T = –40°C to +85°C VS = ±5 V to ±18 V –VS + 2.0 –VS + 1.9 +VS – 1.2 +VS – 1.2 –VS + 2.0 –VS + 1.9 +VS – 1.2 +VS – 1.2 –VS + 2.0 –VS + 1.9 +VS – 1.2 +VS – 1.2 V V T = –40°C to +85°C RL = 10 kΩ VS = ±2.3 V to ±5 V T = –40°C to +85°C VS = ±5 V to ±18 V T = –40°C to +85°C –VS + 2.0 +VS – 1.2 –VS + 2.0 +VS – 1.2 –VS + 2.0 +VS – 1.2 V –VS + 1.1 –VS + 1.4 –VS + 1.2 –VS + 1.6 +VS – 1.2 +Vs – 1.3 +VS – 1.4 +VS – 1.5 –VS + 1.1 –VS + 1.4 –VS + 1.2 –VS + 1.6 +VS – 1.2 +Vs – 1.3 +VS – 1.4 +VS – 1.5 –VS + 1.1 –VS + 1.4 –VS + 1.2 –VS + 1.6 +VS – 1.2 +Vs – 1.3 +VS – 1.4 +VS – 1.5 V V V V mA +85 +125 °C °C 18 –40 –40 100||2 100||2 18 +85 +125 –40 –40 1 Total RTI VOS = (VOSI) + (VOSO/G). Does not include the effects of external resistor RG. 3 One input grounded. G = 1. 4 See Typical Performance Curves for expected operation between 85°C to 125°C. 2 Rev. A | Page 4 of 20 18 +85 +125 –40 –40 AD8221 ABSOLUTE MAXIMUM RATINGS Table 2. AD8221 Absolute Maximum Ratings Parameter Supply Voltage Internal Power Dissipation Output Short Circuit Current Input Voltage (Common-Mode) Differential Input Voltage Storage Temperature Operational* Temperature Range Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Rating ±18 V 200 mW Indefinite ±VS ±Vs –65°C to +150°C –40°C to +125°C Specification is for device in free air: *Temperature range for specified performance is –40°C to +85°C. See Typical Performance Curves for expected operation from +85°C to +125°C. SOIC θJA (4 Layer JEDEC Board) = 121°C/W. MSOP θJA (4 Layer JEDEC Board) = 135°C/W. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 5 of 20 AD8221 TYPICAL PERFORMANCE CHARACTERISTICS (@+25°C, VS = ±15 V, RL = 10 kΩ, unless otherwise noted.) 1600 3500 1400 3000 1200 2500 UNITS UNITS 1000 800 2000 1500 600 1000 400 –100 –50 0 50 100 150 CMR (µV/V) 0 –0.9 03149-0-003 0.6 0.9 1500 1200 900 600 –40 –20 0 20 40 60 INPUT OFFSET VOLTAGE (µV) VS = ±15V 5 0 VS = ±5V –5 –10 –15 –15 03149-0-004 300 10 –10 –5 0 5 10 15 OUTPUT VOLTAGE (V) 03149-0-007 INPUT COMMON-MODE VOLTAGE (V) 1800 UNITS 0.3 15 2100 Figure 7. Input Common-Mode Range vs. Output Voltage, G = 1 Figure 4. Typical Distribution of Input Offset Voltage 15 INPUT COMMON-MODE VOLTAGE (V) 3000 2500 2000 1500 1000 500 –1.0 –0.5 0 0.5 1.0 INPUT BIAS CURRENT (nA) 1.5 03149-0-005 UNITS 0 Figure 6. Typical Distribution of Input Offset Current 2400 0 –1.5 –0.3 INPUT OFFSET CURRENT (nA) Figure 3. Typical Distribution for CMR (G = 1) 0 –60 –0.6 10 VS = ±15V 5 0 VS = ±5V –5 –10 –15 –15 –10 –5 0 5 10 15 OUTPUT VOLTAGE (V) Figure 8. Input Common-Mode Range vs. Output Voltage, G = 100 Figure 5. Typical Distribution of Input Bias Current Rev. A | Page 6 of 20 03149-0-008 0 –150 03149-0-006 500 200 AD8221 0.80 180 0.75 160 0.70 140 VS = ±5V 120 GAIN = 10 100 GAIN = 1 GAIN = 1000 0.55 80 0.50 60 0.45 40 0.40 –15 –10 –5 0 5 10 15 COMMON-MODE VOLTAGE (V) 20 0.1 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 12. Positive PSRR vs. Frequency, RTI (G = 1 to 1000) Figure 9. IBIAS vs. CMV 2.00 180 1.75 160 1.50 140 1.25 120 GAIN = 10 100 GAIN = 1 GAIN = 1000 1.00 0.75 80 0.50 60 0.25 40 0 0.01 0.1 1 10 WARM-UP TIME (min) 20 0.1 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) 03149-0-013 PSRR (dB) GAIN = 100 03149-0-010 CHANGE IN INPUT OFFSET VOLTAGE (µV) GAIN = 100 03149-0-012 0.60 PSRR (dB) VS = ±15V 0.65 03149-0-009 INPUT BIAS CURRENT (nA) GAIN = 1000 Figure 13. Negative PSRR vs. Frequency, RTI (G = 1 to 1000) Figure 10. Change in Input Offset Voltage vs. Warm-Up Time 100k 5.0 4.0 TOTAL DRIFT 25°C – 85°C RTI (µV) VS = ±15V 2.0 1.0 INPUT OFFSET CURRENT INPUT BIAS CURRENT –1.0 –2.0 –3.0 10k BEST AVAILABLE FET INPUT IN-AMP GAIN = 1 1k BEST AVAILABLE FET INPUT IN-AMP GAIN = 1000 AD8221 GAIN = 1 100 –4.0 –5.0 –40 AD8221 GAIN = 1000 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) Figure 11. Input Bias Current and Offset Current vs. Temperature 10 10 100 1k 10k 100k 1M SOURCE RESISTANCE (Ω) Figure 14. Total Drift vs. Source Resistance Rev. A | Page 7 of 20 10M 03149-0-014 0 03149-0-011 INPUT CURRENT (nA) 3.0 AD8221 100 70 GAIN = 1000 80 60 60 50 CMR (µV/V) 40 30 10 0 GAIN = 1 20 0 –20 –40 –10 –60 –20 –80 –30 100 1k 10k 100k 1M 10M FREQUENCY (Hz) –100 –40 0 20 40 60 80 100 120 140 TEMPERATURE (°C) Figure 18. CMR vs. Temperature Figure 15. Gain vs. Frequency +VS–0.0 160 GAIN = 1000 INPUT VOLTAGE LIMIT (V) REFERRED TO SUPPLY VOLTAGES –0.4 140 GAIN = 100 120 CMRR (dB) –20 03149-0-041 20 GAIN = 10 03149-0-015 GAIN (dB) 40 GAIN = 100 GAIN = 10 GAIN = 1000 100 GAIN = 1 GAIN = 10 80 GAIN = 100 60 –0.8 –1.2 –1.6 –2.0 –2.4 +2.4 +2.0 +1.6 +1.2 +0.8 10 100 1k 10k 100k 1M FREQUENCY (Hz) –VS+0.0 0 15 20 Figure 19. Input Voltage Limit vs. Supply Voltage, G = 1 +VS–0.0 160 –0.4 GAIN = 100 140 GAIN = 10 120 GAIN = 1 GAIN = 100 GAIN = 1000 80 60 10 100 1k 10k 100k 1M FREQUENCY (Hz) 03149-0-017 1 RL = 10kΩ –1.2 RL = 2kΩ –1.6 –2.0 +2.0 +1.6 RL = 2kΩ +1.2 +0.8 RL = 10kΩ +0.4 GAIN = 10 40 0.1 –0.8 –VS+0.0 0 5 10 15 20 ± SUPPLY VOLTAGE (V) Figure 20. Output Voltage Swing vs. Supply Voltage, G = 1 Figure 17. CMRR vs. Frequency, RTI, 1 kΩ Source Imbalance Rev. A | Page 8 of 20 03149-0-019 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES GAIN = 1000 CMRR (dB) 10 ± SUPPLY VOLTAGE (V) Figure 16. CMRR vs. Frequency, RTI 100 5 03149-0-018 1 03149-0-016 +0.4 40 0.1 AD8221 30 VS = ±15V 20 10 1 10 100 1k 03149-0-020 0 10k LOAD RESISTANCE (Ω) –10 Figure 21. Output Voltage Swing vs. Load Resistance –8 –6 –4 –2 0 2 4 OUTPUT VOLTAGE (V) 6 8 10 03149-0-023 ERROR (10ppm/DIV) OUTPUT VOLTAGE SWING (V p-p) VS = ±15V Figure 24. Gain Nonlinearity, G = 100, RL = 10 kΩ VS = ±15V –1 SOURCING –2 ERROR (100ppm/DIV) –3 +3 +2 SINKING +1 0 1 2 3 4 5 6 7 8 9 10 11 03149-0-021 –VS+0 12 OUTPUT CURRENT (mA) –10 –8 –6 –4 –2 0 2 4 6 8 10 OUTPUT VOLTAGE (V) Figure 22. Output Voltage Swing vs. Output Current, G = 1 03149-0-024 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES +VS–0 Figure 25. Gain Nonlinearity, G = 1000, RL = 10 kΩ 1k ERROR (1ppm/DIV) VOLTAGE NOISE RTI (nV/ Hz) VS = ±15V GAIN = 1 100 GAIN = 10 GAIN = 100 10 GAIN = 1000 –8 –6 –4 –2 0 2 4 6 8 OUTPUT VOLTAGE (V) Figure 23. Gain Nonlinearity, G = 1, RL = 10 kΩ 10 1 03149-0-022 –10 1 10 100 1k FREQUENCY (Hz) 10k 100k 03149-0-025 GAIN = 1000 BW LIMIT Figure 26. Voltage Noise Spectral Density vs. Frequency (G = 1 to 1000) Rev. A | Page 9 of 20 1s/DIV 5pA/DIV Figure 27. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1) 1s/DIV 03149-0-029 2µV/DIV 03149-0-026 AD8221 Figure 30. 0.1 Hz to 10 Hz Current Noise 30 VS = ±15V OUTPUT VOLTAGE (V p-p) 25 20 GAIN = 1 GAIN = 10, 100, 1000 15 10 1s/DIV 0 1k 10k 100k 1M FREQUENCY (Hz) Figure 28. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000) 03149-0-030 0.1µV/DIV 03149-0-027 5 Figure 31. Large Signal Frequency Response 5V/DIV 100 10 1 10 100 1k 10k FREQUENCY (Hz) Figure 29. Current Noise Spectral Density vs. Frequency 7.9µs TO 0.01% 8.5µs TO 0.001% 20µs/DIV 03149-0-031 10mV/DIV 03149-0-028 CURRENT NOISE (fA/ Hz) 1k Figure 32. Large Signal Pulse Response and Settling Time (G = 1), 0.002%/div Rev. A | Page 10 of 20 AD8221 5V/div 10mV/div 4.9µs TO 0.01% 5.6µs TO 0.001% Figure 33. Large Signal Pulse Response and Settling Time (G = 10), 0.002%/div 4µs/DIV 03149-0-035 20µs/div 03149-0-032 20mV/DIV Figure 36. Small Signal Response, G = 1, RL = 2 kΩ, CL = 100 pF 5V/DIV 10mV/DIV 10.3µs TO 0.01% 13.4µs TO 0.001% Figure 34. Large Signal Pulse Response and Settling Time (G = 100), 0.002%/div 4µs/DIV 03149-0-036 20µs/DIV 03149-0-033 20mV/DIV Figure 37. Small Signal Response, G = 10, RL = 2 kΩ, CL = 100 pF 5V/DIV 10mV/DIV 83µs TO 0.01% 112µs TO 0.001% Figure 35. Large Signal Pulse Response and Settling Time (G = 1000), 0.002%/div Rev. A | Page 11 of 20 10µs/DIV Figure 38. Small Signal Response, G = 100, RL = 2 kΩ, CL = 100 pF 03149-0-037 20µs/DIV 03149-0-034 20mV/DIV AD8221 SETTLING TIME (µs) 1k 2 100 SETTLED TO 0.001% 10 03149-0-038 100µs/DIV 1 1 10 100 GAIN Figure 41. Settling Time vs. Gain for a 10 V Step Figure 39. Small Signal Response, G = 1000, RL = 2 kΩ, CL = 100 pF 10 SETTLED TO 0.001% SETTLED TO 0.01% 5 0 0 5 10 15 OUTPUT VOLTAGE STEP SIZE (V) 20 03149-0-039 SETTLING TIME (µs) 15 Figure 40. Settling Time vs. Step Size (G = 1) Rev. A | Page 12 of 20 1k 03149-0-040 SETTLED TO 0.01% 20mV/DIV AD8221 THEORY OF OPERATION VB I I A1 IB COMPENSATION A2 IB COMPENSATION 10kΩ C1 C2 +VS 10kΩ OUTPUT A3 10kΩ +VS –IN +VS 400Ω Q1 R2 +VS R1 24.7kΩ +VS +VS 24.7kΩ 400Ω Q2 +IN –VS REF 10kΩ RG –VS 03149-0-042 –VS –VS –VS –VS Figure 42. Simplified Schematic Using superbeta input transistors and an IB compensation scheme, the AD8221 offers extremely high input impedance, low IB, low IB drift, low IOS, low input bias current noise, and extremely low voltage noise of 8 nV/√Hz. Since the input amplifiers employ a current feedback architecture, the AD8221’s gain-bandwidth product increases with gain, resulting in a system that does not suffer from the expected bandwidth loss of voltage feedback architectures at higher gains. In order to maintain precision even at low input levels, special attention was given to the AD8221’s design and layout, resulting in an in-amp whose performance satisfies the most demanding applications. A unique pinout enables the AD8221 to meet a CMRR specification of 80 dB at 10 kHz (G = 1) and 110 dB at 1 kHz (G = 1000). The balanced pinout, shown in Figure 43, reduces the parasitics that had, in the past, adversely affected CMRR performance. In addition, the new pinout simplifies board layout because associated traces are grouped together. For example, the gain setting resistor pins are adjacent to the inputs, and the reference pin is next to the output. The transfer function of the AD8221 is 49.4 kΩ G = 1+ RG –IN 1 8 +VS RG 2 7 VOUT RG 3 6 REF +IN 4 5 –VS AD8221 TOP VIEW Figure 43. Pinout Diagram Users can easily and accurately set the gain using a single, standard resistor. Rev. A | Page 13 of 20 03149-0-001 The AD8221 is a monolithic instrumentation amplifier based on the classic 3-op amp topology. Input transistors Q1 and Q2 are biased at a fixed current, so that any differential input signal will force the output voltages of A1 and A2 to change accordingly. A signal applied to the input creates a current through RG, R1, and R2, such that the outputs of A1 and A2 deliver the correct voltage. Topologically, Q1, A1, R1 and Q2, A2, R2 can be viewed as precision current feedback amplifiers. The amplified differential and common-mode signals are applied to a difference amplifier that rejects the common-mode voltage but amplifies the differential voltage. The difference amplifier employs innovations that result in low output offset voltage as well as low output offset voltage drift. Laser-trimmed resistors allow for a highly accurate in-amp with gain error typically less than 20 ppm and CMRR that exceeds 90 dB (G = 1). AD8221 GAIN SELECTION Grounding Placing a resistor across the RG terminals will set the AD8221’s gain, which may be calculated by referring to Table 3 or by using the gain equation The AD8221’s output voltage is developed with respect to the potential on the reference terminal. Care should be taken to tie REF to the appropriate “local ground.” RG = In mixed-signal environments, low level analog signals need to be isolated from the noisy digital environment. Many ADCs have separate analog and digital ground pins. Although it is convenient to tie both grounds to a single ground plane, the current traveling through the ground wires and PC board may cause hundreds of millivolts of error. Therefore, separate analog and digital ground returns should be used to minimize the current flow from sensitive points to the system ground. An example layout is shown in Figure 44 and Figure 45. 49.4 kΩ G −1 Table 3. Gains Achieved Using 1% Resistors 1% Std Table Value of RG (Ω) 49.9 k 12.4 k 5.49 k 2.61 k 1.00 k 499 249 100 49.9 Calculated Gain 1.990 4.984 9.998 19.93 50.40 100.0 199.4 495.0 991.0 The AD8221 defaults to G = 1 when no gain resistor is used. Gain accuracy is determined by the absolute tolerance of RG. The TC of the external gain resistor will increase the gain drift of the instrumentation amplifier. Gain error and gain drift are kept to a minimum when the gain resistor is not used. Careful board layout maximizes system performance. Traces from the gain setting resistor to the RG pins should be kept as short as possible to minimize parasitic inductance. To ensure the most accurate output, the trace from the REF pin should either be connected to the AD8221’s local ground as shown in Figure 47, or connected to a voltage that is referenced to the AD8221’s local ground. 03149-0-051 LAYOUT Figure 44.Top Layer of the AD8221-EVAL Common-Mode Rejection One benefit of the AD8221’s high CMRR over frequency is that it has greater immunity to disturbances such as line noise and its associated harmonics than do typical in-amps. These, typically, have CMRR fall-off at 200 Hz; common-mode filters are often used to compensate for this shortcoming. The AD8221 is able to reject CMRR over a greater frequency range, reducing the need for filtering. 03149-0-052 A well implemented layout helps to maintain the AD8221’s high CMRR over frequency. Input source impedance and capacitance should be closely matched. In addition, source resistance and capacitance should be placed as close to the inputs as permissible. Figure 45.Bottom Layer of the AD8221-EVAL Rev. A | Page 14 of 20 AD8221 +VS REFERENCE TERMINAL As shown in Figure 42, the reference terminal, REF, is at one end of a 10 kΩ resistor. The instrumentation amplifier’s output is referenced to the voltage on the REF terminal; this is useful when the output signal needs to be offset to a precise midsupply level. For example, a voltage source can be tied to the REF pin to level-shift the output so that the AD8221 can interface with an ADC. The allowable reference voltage range is a function of the gain, input and supply voltage. The REF pin should not exceed either +VS or –VS by more than 0.5 V. AD8221 REF –VS TRANSFORMER +VS For best performance, source impedance to the REF terminal should be kept low, since parasitic resistance can adversely affect CMRR and gain accuracy. AD8221 REF POWER SUPPLY REGULATION AND BYPASSING A stable dc voltage should be used to power the instrumentation amplifier. Noise on the supply pins may adversely affect performance. Bypass capacitors should be used to decouple the amplifier. –VS THERMOCOUPLE +VS A 0.1 µF capacitor should be placed close to each supply pin. As shown in Figure 47, a 10 µF tantalum capacitor may be used further away from the part. In most cases, it may be shared by other precision integrated circuits. C R 1 fHIGH-PASS = 2πRC AD8221 C REF Figure 46 –VS CAPACITOR COUPLED +VS 03149-0-044 R Figure 48. Creating an IBIAS Path 0.1µF 10µF INPUT PROTECTION +IN INPUT BIAS CURRENT RETURN PATH All terminals of the AD8221 are protected against ESD1. In addition, the input structure allows for dc overload conditions below the negative supply, –Vs. The internal 400 Ω resistors limit current in the event of a negative fault condition. However, in the case of a dc overload voltage above the positive supply, +Vs, a large current would flow directly through the ESD diode to the positive rail. Therefore, an external resistor should be used in series with the input to limit current for voltages above +Vs. In either scenario, the AD8221 can safely handle a continuous 6 mA current, I = VIN/REXT for positive overvoltage and I = VIN/(400 Ω + REXT) for negative overvoltage. The AD8221’s input bias current must have a return path to common. When the source, such as a thermocouple, cannot provide a return current path, one should be created, as shown in Figure 48. For applications where the AD8221 encounters extreme overload voltages, as in cardiac defibrillators, external series resistors and low leakage diode clamps such as BAV199Ls, FJH1100s, or SP720s should be used. VOUT AD8221 LOAD 0.1µF 10µF –VS 03149-0-043 REF –IN Figure 47. Supply Decoupling,. REF and Output Referred to Local Ground 1 1 kV—Human Body Model. Rev. A | Page 15 of 20 AD8221 RF INTERFERENCE RF rectification is often a problem when amplifiers are used in applications where there are strong RF signals. The disturbance may appear as a small dc offset voltage. High frequency signals can be filtered with a low-pass R-C network placed at the input of the instrumentation amplifier, as shown in Figure 49. The filter limits the input signal bandwidth according to the following relationship: FilterFreq Diff 1 = 2 πR(2CD + CC ) FilterFreqCM = CD affects the difference signal and CC affects the commonmode signal. Values of R and CC should be chosen to minimize RFI. Mismatch between the R × CC at the positive input and the R × CC at negative input will degrade the AD8221’s CMRR. By using a value of CD one magnitude larger than CC, the effect of the mismatch is reduced, and hence, performance is improved. PRECISION STRAIN GAGE The AD8221’s low offset and high CMRR over frequency make it an excellent candidate for bridge measurements. As shown in Figure 50, the bridge can be directly connected to the inputs of the amplifier. 1 2πRCC +5V 10µF where CD ≥ 10CC. 350Ω +IN +15V 350Ω 0.1µF CC 10µF – 1nF R +IN R1 10nF 499Ω Figure 50. Precision Strain Gage VOUT AD8221 R REF –IN 4.02kΩ 1nF 0.1µF 10µF –15V 03149-0-045 CC + AD8221 R –IN 4.02kΩ CD 350Ω Figure 49. RFI Suppression Rev. A | Page 16 of 20 +2.5V 03149-0-049 350Ω 0.1µF AD8221 +12V +2.5V +12V R3 1kΩ 0.1µF +5V 10µF +12V 0.1µF R6 27.4Ω 10nF AD8022 C1 470pF 0.1µF +IN +5V (½) AVDD DVDD VIN+ R1 REF 10kΩ –12V R5 499Ω –IN R2 10kΩ 10µF 0.1µF OP27 VIN– AGND VGND REF1 REF2 0.1µF 0.1µF 0.1µF AD7723 C2 220µF +12V R7 27.4Ω –12V AD8022 –12V (½) R4 1kΩ 220nF 0.1µF 10nF +5V –12V VIN 10µF 0.1µF VOUT AD780 2.5V 22µF 03149-0-047 AD8221 GND Figure 51. Interfacing to a Differential Input ADC AC-COUPLED INSTRUMENTATION AMPLIFIER There is a need in many applications to condition ±10 V signals. However, many of today’s ADCs and digital ICs operate on much lower, single-supply voltages. Furthermore, new ADCs have differential inputs because they provide better commonmode rejection, noise immunity, and performance at low supply voltages. Interfacing a ±10 V, single-ended instrumentation amplifier to a +5 V, differential ADC may be a challenge. Interfacing the in-amp to the ADC requires attenuation and a level shift. A solution is shown in Figure 51. Measuring small signals that are in the amplifier’s noise or offset can be a challenge. Figure 52 shows a circuit that can improve the resolution of small ac signals. The large gain reduces the referred input noise of the amplifier to 8 nV/√Hz. Thus, smaller signals can be measured since the noise floor is lower. DC offsets that would have been gained by 100 are eliminated from the AD8221’s output by the integrator feedback network. At low frequencies, the OP1177 forces the AD8221’s output to 0 V. Once a signal exceeds fHIGH-PASS, the AD8221 outputs the amplified input signal. In this topology, an OP27 sets the AD8221’s reference voltage. The in-amp’s output signal is taken across the OUT pin and the REF pin. Two 1 kΩ resistors and a 499 Ω resistor attenuate the ±10 V signal to +4 V. An optional capacitor, C1, may serve as an ant aliasing filter. An AD8022 is used to drive the ADC. This topology has five benefits. In addition to level-shifting and attenuation, very little noise is contributed to the system. Noise from R1 and R2 is common to both of the ADC’s inputs and is easily rejected. R5 adds a third of the dominant noise and therefore makes a negligible contribution to the noise of the system. The attenuator divides the noise from R3 and R4. Likewise, its noise contribution is negligible. The fourth benefit of this interface circuit is that the AD8221’s acquisition time is reduced by a factor of 2. With the help of the OP27, the AD8221 only needs to deliver one-half of the full swing; therefore, signals can settle more quickly. Lastly, the AD8022 settles quickly, which is helpful because the shorter the settling time, the more bits that can be resolved when the ADC acquires data. This configuration provides attenuation, a level-shift, and a convenient interface with a differential input ADC while maintaining performance. Rev. A | Page 17 of 20 +VS 0.1µF +IN R 499Ω fHIGH-PASS = 1 2πRC AD8221 R 15.8kΩ REF C 1µF –IN +VS 0.1µF 0.1µF –VS OP1177 +VS 10µF –VS 10µF 0.1µF –VS Figure 52. AC-Coupled Circuit 03149-0-048 CONDITIONING ±10 V SIGNALS FOR A +5 V DIFFERENTIAL INPUT ADC AD8221 OUTLINE DIMENSIONS 3.00 BSC 8 5 4.90 BSC 3.00 BSC 4 PIN 1 0.65 BSC 1.10 MAX 0.15 0.00 0.38 0.22 COPLANARITY 0.10 0.80 0.60 0.40 8° 0° 0.23 0.08 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-187AA Figure 53. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 5.00 (0.1968) 4.80 (0.1890) 8 5 4.00 (0.1574) 3.80 (0.1497) 1 4 6.20 (0.2440) 5.80 (0.2284) 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) COPLANARITY 0.31 (0.0122) SEATING 0.10 PLANE 0.50 (0.0196) × 45° 0.25 (0.0099) 8° 0.25 (0.0098) 0° 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 54. 8-Lead Shrink Small Outline Package [SOIC] (R-8) ORDERING GUIDE Model AD8221AR AD8221AR-REEL AD8221AR-REEL7 AD8221ARM AD8221ARM-REEL AD8221ARM-REEL7 AD8221BR AD8221BR-REEL AD8221BR-REEL7 AD8221-EVAL 1 Temperature Range for Specified Performance –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Operational1 Temperature Range –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C See Typical Performance Curves for expected operation from 85°C to 125°C. Rev. A | Page 18 of 20 Package Description 8-Lead SOIC 13" Tape and Reel 7" Tape and Reel 8-Lead MSOP 13" Tape and Reel 7" Tape and Reel 8-Lead SOIC 13" Tape and Reel 7" Tape and Reel Evaluation Board Package Option R-8 R-8 R-8 RM-8 RM-8 RM-8 R-8 R-8 R-8 Branding JLA JLA JLA AD8221 NOTES Rev. A | Page 19 of 20 AD8221 NOTES © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03149–0–11/03(A) Rev. A | Page 20 of 20