AD AD8300

a
+3 Volt, Serial Input
Complete 12-Bit DAC
AD8300
FEATURES
Complete 12-Bit DAC
No External Components
Single +3 Volt Operation
0.5 mV/Bit with 2.0475 V Full Scale
6 ␮s Output Voltage Settling Time
Low Power: 3.6 mW
Compact SO-8 1.5 mm Height Package
FUNCTIONAL BLOCK DIAGRAM
REF
CLR
SERIAL
REGISTER
SDI
AD8300
A double buffered serial data interface offers high speed, threewire, DSP and microcontroller compatible inputs using data in
(SDI), clock (CLK) and load strobe (LD) pins. A chip select
(CS) pin simplifies connection of multiple DAC packages by
enabling the clock input when active low. Additionally, a CLR
input sets the output to zero scale at power on or upon user
demand.
The AD8300 is specified over the extended industrial (–40°C to
+85°C) temperature range. AD8300s are available in plastic
DIP, and low profile 1.5 mm height SO-8 surface mount packages.
3.0
1.00
INL LINEARITY ERROR – LSB
DVFS 1 LSB
DATA = FFFH
TA = +258C
2.6
PROPER OPERATION
WHEN VDD SUPPLY
VOLTAGE ABOVE
CURVE
2.2
0.75
0.1
1.0
OUTPUT LOAD CURRENT – mA
10
Figure 1. Minimum Supply Voltage vs. Load
VDD = +2.7V
TA = –408C, +258C, +1258C
0.50
0.25
0.00
–0.25
–0.50
= –408C
= +258C
= +1258C
–0.75
2.0
0.01
GND
EN
CLK
The 2.0475 V full-scale voltage output is laser trimmed to
maintain accuracy over the operating temperature range of the
device. The binary input data format provides an easy-to-use
one-half-millivolt-per-bit software programmability. The voltage
outputs are capable of sourcing 5 mA.
MINIMUM SUPPLY VOLTAGE – Volts
12
CS
The AD8300 is a complete 12-bit, voltage-output digital-toanalog converter designed to operate from a single +3 volt supply. Built using a CBCMOS process, this monolithic DAC
offers the user low cost, and ease-of-use in single-supply +3 volt
systems. Operation is guaranteed over the supply voltage range
of +2.7 V to +5.5 V making this device ideal for battery operated applications.
VDD
DAC
REGISTER
LD
GENERAL DESCRIPTION
2.4
VOUT
12
APPLICATIONS
Portable Communications
Digitally Controlled Calibration
Servo Controls
PC Peripherals
2.8
12-BIT
DAC
–1.00
0
1024
2048
3072
DIGITAL INPUT CODE – Decimal
4096
Figure 2. Linearity Error vs. Digital Code and Temperature
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
AD8300–SPECIFICATIONS
+3 V OPERATION (@ V
DD
= +5 V ⴞ 10%, –40ⴗC ≤ TA ≤ +85ⴗC, unless otherwise noted)
Parameter
Symbol
Condition
Min
STATIC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity2
Zero-Scale Error
Full-Scale Voltage3
Full-Scale Tempco
N
INL
DNL
VZSE
VFS
TCVFS
[Note 1]
12
–2
–1
ANALOG OUTPUT
Output Current (Source)
Output Current (Sink)
Load Regulation
Output Resistance to GND
Capacitive Load
IOUT
IOUT
LREG
ROUT
CL
Data = 800H, ∆VOUT = 5 LSB
Data = 800H, ∆VOUT = 5 LSB
RL = 200 Ω to ∞, Data = 800H
Data = 000H
No Oscillation4
LOGIC INPUTS
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance
VIL
VIH
IIL
CIL
INTERFACE TIMING
SPECIFICATIONS4, 5
Clock Width High
Clock Width Low
Load Pulsewidth
Data Setup
Data Hold
Clear Pulsewidth
Load Setup
Load Hold
Select
Deselect
tCH
tCL
tLDW
tDS
tDH
tCLRW
tLD1
tLD2
tCSS
tCSH
AC CHARACTERISTICS4
Voltage Output Settling Time
tS
Output Slew Rate
DAC Glitch
Digital Feedthrough
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Power Dissipation
Power Supply Sensitivity
SR
VDD RANGE
IDD
PDISS
PSS
Monotonic
Data = 000H
Data = FFFH
[Notes 3, 4]
Typ
± 1/2
± 1/2
+1/2
2.039 2.0475
16
1.5
30
500
Max
Units
+2
+1
+3
2.056
Bits
LSB
LSB
mV
Volts
ppm/°C
5
2
5
mA
mA
LSB
Ω
pF
0.6
V
V
µA
pF
2.1
10
10
40
40
50
15
15
40
15
40
40
40
To ± 0.2% of Full Scale
To ± 1 LSB of Final Value6
Data = 000H to FFFH to 000H
DNL < ± 1 LSB
VDD = 3 V, VIL = 0 V, Data = 000H
VDD = 3.6 V, VIH = 2.3 V, Data = FFFH
VDD = 3 V, VIL = 0 V, Data = 000H
∆VDD = ± 5%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
V/µs
nV/s
nV/s
7
14
2.0
15
15
2.7
1.2
1.9
3.6
0.001
5.5
1.7
3.0
5.1
0.005
V
mA
mA
mW
%/%
NOTES
1
LSB = 0.5 mV for 0 V to +2.0475 V output range.
2
The first two codes (000 H, 001H) are excluded from the linearity error measurement.
3
Includes internal voltage reference error.
4
These parameters are guaranteed by design and not subject to production testing.
5
All input control signals are specified with t R = tF = 2 ns (10% to 90% of +3 V) and timed from a voltage level of 1.6 V.
6
The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in
this 6 LSB region.
Specifications subject to change without notice.
–2–
REV. A
AD8300
+5 V OPERATION
(@ VDD = +5 V ⴞ 10%, –40ⴗC ≤ TA ≤ +85ⴗC, unless otherwise noted)
Parameter
Symbol
Condition
Min
STATIC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity2
Zero-Scale Error
Full-Scale Voltage3
Full-Scale Tempco
N
INL
DNL
VZSE
VFS
TCVFS
[Note 1]
12
–2
–1
ANALOG OUTPUT
Output Current (Source)
Output Current (Sink)
Load Regulation
Output Resistance to GND
Capacitive Load
IOUT
IOUT
LREG
ROUT
CL
Data = 800H, ∆VOUT = 5 LSB
Data = 800H, ∆VOUT = 5 LSB
RL = 200 Ω to ∞, Data = 800H
Data = 000H
No Oscillation4
LOGIC INPUTS
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance
VIL
VIH
IIL
CIL
INTERFACE TIMING
SPECIFICATIONS4, 5
Clock Width High
Clock Width Low
Load Pulsewidth
Data Setup
Data Hold
Clear Pulsewidth
Load Setup
Load Hold
Select
Deselect
tCH
tCL
tLDW
tDS
tDH
tCLWR
tLD1
tLD2
tCSS
tCSH
AC CHARACTERISTICS4
Voltage Output Settling Time
tS
Output Slew Rate
DAC Glitch
Digital Feedthrough
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Power Dissipation
Power Supply Sensitivity
SR
VDD RANGE
IDD
PDISS
PSS
Monotonic
Data = 000H
Data = FFFH
[Notes 3, 4]
Typ
± 1/2
± 1/2
+1/2
2.039 2.0475
16
1.5
30
500
Max
Units
+2
+1
+3
2.056
Bits
LSB
LSB
mV
Volts
ppm/°C
5
2
5
mA
mA
LSB
Ω
pF
0.8
V
V
µA
pF
2.4
10
10
30
30
30
15
15
30
15
30
30
30
To ± 0.2% of Full Scale
To ± 1 LSB of Final Value6
Data = 000H to FFFH to 000H
DNL < ± 1 LSB
VDD = 5 V, VIL = 0 V, Data = 000H
VDD = 5.5 V, VIH = 2.3 V, Data = FFFH
VDD = 5 V, VIL = 0 V, Data = 000H
∆VDD = ± 10%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
V/µs
nV/s
nV/s
6
13
2.2
15
15
2.7
1.2
2.8
6
0.001
5.5
1.7
4.0
5.1
0.006
V
mA
mA
mW
%/%
NOTES
1
1 LSB = 0.5 mV for 0 V to +2.0475 V output range.
2
The first two codes (000 H, 001H) are excluded from the linearity error measurement.
3
Includes internal voltage reference error.
4
These parameters are guaranteed by design and not subject to production testing.
5
All input control signals are specified with t R = tF = 2 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
6
The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in
this 6 LSB region.
Specifications subject to change without notice.
REV. A
–3–
AD8300
ABSOLUTE MAXIMUM RATINGS *
PIN CONFIGURATIONS
SO-8
Plastic DIP
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
VOUT to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
IOUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package Power Dissipation . . . . . . . . . . . . . (TJ Max – TA)/θJA
Thermal Resistance θJA
8-Lead Plastic DIP Package (N-8) . . . . . . . . . . . . . 103°C/W
8-Lead SOIC Package (SO-8) . . . . . . . . . . . . . . . . 158°C/W
Maximum Junction Temperature (TJ Max) . . . . . . . . . . 150°C
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C
1
4
Temp
Package
Description
Package
Options
AD8300AN
AD8300AR
±2
±2
XIND
XIND
8-Lead P-DIP
8-Lead SOIC
N-8
SO-8
D11
D10
D9
D8
D7
AD8300 7 GND
CLK 3 TOP VIEW 6 CLR
5 LD
PIN DESCRIPTIONS
NOTES
XIND = –40°C to +85°C.
The AD8300 contains 630 transistors. The die size measures 72 mil × 65 mil.
SDI
8 VOUT
CS 2
(Not to Scale)
ORDERING GUIDE
INL
5
VDD 1
SDI 4
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Model
8
D6
Pin #
Name
Function
1
VDD
2
CS
3
CLK
4
SDI
5
LD
6
CLR
7
8
GND
VOUT
Positive power supply input. Specified range
of operation +2.7 V to +5.5 V.
Chip Select, active low input. Disables shift
register loading when high. Does not affect
LD operation.
Clock input, positive edge clocks data into
shift register.
Serial Data Input, input data loads directly
into the shift register, MSB first.
Load DAC register strobes, active low.
Transfers shift register data to DAC register.
See Truth Table I for operation. Asynchronous active low input.
Resets DAC register to zero condition.
Asynchronous active low input.
Analog and Digital Ground.
DAC voltage output, 2.0475 V full scale
with 0.5 mV per bit. An internal temperature stabilized reference maintains a fixed
full-scale voltage independent of time, temperature and power supply variations.
D5
D4
D3
D2
D1
D0
CLK
t CSS
t CSH
CS
t LD1
t LD2
LD
SDI
t DS
CLK
t DH
t CL
t CH
t LDW
LD
t CLRW
CLR
tS
tS
FS
VOUT
ZS
61LSB
ERROR BAND
Figure 3. Timing Diagram
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8300 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. A
Typical Performance Characteristics–AD8300
2.5
80
POSITIVE
CURRENT
LIMIT
VDD = +5V
40
LOGIC THRESHOLD VOLTAGE
OUTPUT CURRENT – mA
60
VDD = +3V
20
DATA = 800H
RL TIED TO +1.024V
0
–20
–40
VDD = +3V
–60
–80
NEGATIVE
CURRENT
LIMIT
VDD = +5V
TA = –40 TO +858C
2.0
1.5
1.0
0.5
0
0
1
OUTPUT VOLTAGE – Volts
2
HORIZONTAL = 1ms/DIV
0
2
3
1
4
5
VDD SUPPLY VOLTAGE – Volts
6
Figure 5. Logic Input Threshold
Voltage vs. VDD
Figure 4. IOUT vs. VOUT
Figure 6. Detail Settling Time
BROADBAND NOISE – 200mV/DIV
POWER SUPPLY REJECTION – dB
50
TIME = 100ms/DIV
45
VDD = +5V 610%
40
35
30
25
VDD = +3V 610%
20
15
10
TA = +258C
DATA = FFFH
5
0
10
HORIZONTAL = 20ms/DIV
100
10k
100k
1k
FREQUENCY – Hz
1M
Figure 8. Power Supply Rejection
vs. Frequency
Figure 7. Broadband Noise
Figure 9. Large Signal Settling Time
3.5
SUPPLY CURRENT – mA
3.0
2.5
VDD = +3V
2.0
1.5
VDD = +5V
1.0
TA = +258C
DATA = FFFH
0.5
0
CODE 800H TO 7FFH
0
1
2
3
4
LOGIC VOLTAGE – Volts
Figure 10. Supply Current vs. Logic
Input Voltage
REV. A
0.5ms/DIV
5
Figure 11. Midscale Transition
Performance
–5–
Figure 12. Digital Feedthrough vs.
Time
AD8300
20
VDD = +5V
0
–0.5
–1.0
10
–1
–1.5
–55 –35 –15
0
1
2
3
4
5
6
TOTAL UNADJUSTED ERROR – mV
Figure 13. Total Unadjusted
Error Histogram
VDD = +5.5V
0
–0.5
VDD = +2.7V
NOISE DENSITY – mV/Hz
VOUT DRIFT – mV
0.5
VDD = +4.5V
1.8
VDD = +2.7, 3.0, 3.3V
DATA = FFFH
VIH = +2.4V
VIL = 0V
1.4
–20
20
60
100
TEMPERATURE – 8C
140
VDD = +3V
DATA = FFFH
60
50
1
0.1
VDD = +3V
DATA FFFH
TA = –40 TO +858C
40
30
20
10
0.01
1
10
100
1k
FREQUENCY – Hz
10k
100k
Figure 17. Output Voltage Noise
Density vs. Frequency
0
–50 –40 –30 –20 –10 0 10 20 30 40
TEMPERATURE COEFFICIENT – ppm/8C
Figure 18. Full-Scale Output
Tempco Histogram
2.4
NOMINAL VOLTAGE CHANGE – mV
Figure 16. Full-Scale Voltage Drift
vs. Temperature
2.2
70
–1.0
–1.5
–55 –35 –15 5
25 45 65 85 105 125
TEMPERATURE – 8C
VDD = +5.0V
Figure 15. Supply Current vs.
Temperature
10
NO LOAD
ss = 300 UNITS
NORMALIZED TO +258C
2.6
1.0
–60
5
25 45 65 85 105 125
TEMPERATURE – 8C
Figure 14. Zero-Scale Voltage Drift
vs. Temperature
1.5
1.0
VDD = +2.7V
IDD SUPPLY CURRENT – mA
30
0.5
VDD = +5.5V
FREQUENCY
FREQUENCY
40
NO LOAD
ss = 300 UNITS
NORMALIZED TO +258C
1.0
VOUT DRIFT – mV
TUE = SINL+ZS+FS
ss = 300 UNITS
VDD = +3V
TA = +258C
50
0
3.0
1.5
60
VDD = +2.7V
ss = 135 UNITS
2.0
1.6
FULL SCALE (DATA = FFFH)
1.2
0.8
0.4
ZERO SCALE (DATA = 000H)
0
0
100 200
300
400
500 600
HOURS OF OPERATION AT +1508C
Figure 19. Long Term Drift
Accelerated by Burn-In
–6–
REV. A
AD8300
Table I. Control Logic Truth Table
CS
CLK
CLR
LD
Serial Shift Register Function
DAC Register Function
H
L
L
L
↑
H
H
H
H
X
L
H
↑
L
X
X
X
X
H
H
H
H
H
H
H
L
↑
H
H
H
H
H
↓
L
X
H
No Effect
No Effect
No Effect
Shift-Register-Data Advanced One Bit
No Effect
No Effect
No Effect
No Effect
No Effect
Latched
Latched
Latched
Latched
Latched
Updated with Current Shift Register Contents
Transparent
Loaded with All Zeros
Latched All Zeros
NOTES
1. ↑ = Positive Logic Transition; ↓ = Negative Logic Transition; X = Don’t Care.
2. Do not clock in serial data while LD is LOW.
3. Data loads MSB first.
OPERATION
OUTPUT SECTION
The AD8300 is a complete ready to use 12-bit digital-to-analog
converter. Only one +3 V power supply is necessary for operation. It contains a 12-bit laser-trimmed digital-to-analog
converter, a curvature-corrected bandgap reference, rail-to-rail
output op amp, serial-input register, and DAC register. The
serial data interface consists of a serial-data-input (SDI) clock
(CLK), and load strobe pins (LD) with an active low CS strobe.
In addition an asynchronous CLR pin will set all DAC register
bits to zero causing the VOUT to become zero volts. This function is useful for power on reset or system failure recovery to a
known state.
The rail-to-rail output stage of this amplifier has been designed
to provide precision performance while operating near either
power supply. Figure 21 shows an equivalent output schematic
of the rail-to-rail amplifier with its N-channel pull-down FETs
that will pull an output load directly to GND. The output
sourcing current is provided by a P-channel pull-up device that
can source current to GND terminated loads.
VDD
P-CH
N-CH
D/A CONVERTER SECTION
The internal DAC is a 12-bit device with an output that swings
from GND potential to 0.4 volt generated from the internal bandgap voltage, see Figure 20. It uses a laser-trimmed segmented
R-2R ladder which is switched by N-channel MOSFETs. The
output voltage of the DAC has a constant resistance independent of digital input code. The DAC output is internally connected to the rail-to-rail output op amp.
AGND
Figure 21. Equivalent Analog Output Circuit
The rail-to-rail output stage achieves the minimum operating
supply voltage capability shown in Figure 2. The N-channel
output pull-down MOSFET shown in Figure 21 has a 35 Ω on
resistance which sets the sink current capability near ground. In
addition to resistive load driving capability, the amplifier has
also been carefully designed and characterized for up to 500 pF
capacitive load driving capability.
AMPLIFIER SECTION
The internal DAC’s output is buffered by a low power consumption precision amplifier. This low power amplifier contains
a differential PNP pair input stage that provides low offset voltage and low noise, as well as the ability to amplify the zero-scale
DAC output voltages. The rail-to-rail amplifier is configured
with a gain of approximately five in order to set the 2.0475 volt
full-scale output (0.5 mV/LSB). See Figure 20 for an equivalent
circuit schematic of the analog section.
BANDGAP 1.2V
REF
12-BIT DAC
REFERENCE SECTION
The internal curvature-corrected bandgap voltage reference is
laser trimmed for both initial accuracy and low temperature
coefficient. Figure 18 provides a histogram of total output performance of full-scale vs. temperature which is dominated by
the reference performance.
POWER SUPPLY
0.4V
FS
The very low power consumption of the AD8300 is a direct
result of a circuit design optimizing use of a CBCMOS process.
By using the low power characteristics of the CMOS for the
logic, and the low noise, tight matching of the complementary
bipolar transistors, good analog accuracy is achieved.
VOUT
2.047V
FS
0.4V
R1
R2
Figure 20. Equivalent AD8300 Schematic of Analog Portion
The op amp has a 2 µs typical settling time to 0.4% of full scale.
There are slight differences in settling time for negative slewing
signals versus positive. Also negative transition settling time to
within the last 6 LSB of zero volts has an extended settling time.
See the oscilloscope photos in the typical performances section
of this data sheet.
REV. A
VOUT
–7–
For power-consumption sensitive applications it is important to
note that the internal power consumption of the AD8300 is
strongly dependent on the actual logic input voltage levels
present on the SDI, CLK, CS, LD, and CLR pins. Since these
inputs are standard CMOS logic structures, they contribute
static power dissipation dependent on the actual driving logic
AD8300
Table II. Unipolar Code Table
As with any analog system, it is recommended that the AD8300
power supply be bypassed on the same PC card that contains
the chip. Figure 8 shows the power supply rejection versus frequency performance. This should be taken into account when
using higher frequency switched-mode power supplies with
ripple frequencies of 100 kHz and higher.
Hexadecimal
Number in
DAC Register
Decimal
Number in
DAC Register
Analog Output
Voltage (V)
FFF
801
800
7FF
000
4095
2049
2048
2047
0
+2.0475
+1.0245
+1.0240
+1.0235
+0.0000
One advantage of the rail-to-rail output amplifiers used in the
AD8300 is the wide range of usable supply voltage. The part is
fully specified and tested over temperature for operation from
+2.7 V to +5.5 V. If reduced linearity and source current capability near full scale can be tolerated, operation of the AD8300
is possible down to +2.1 volts. The minimum operating supply
voltage versus load current plot in Figure 2 provides information
for operation below VDD = +2.7 V.
C1968a–0–5/99
VOH and VOL voltage levels. Consequently, for optimum dissipation use of CMOS logic versus TTL provides minimal dissipation in the static state. A VINL = 0 V on the logic input pins
provides the lowest standby dissipation of 1.2 mA with a +3.3 V
power supply.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SOIC (SO-8)
0.1968 (5.00)
0.1890 (4.80)
TIMING AND CONTROL
The AD8300 has a separate serial-input register from the 12-bit
DAC register that allows preloading of a new data value MSB
first into the serial register without disturbing the present DAC
output voltage value. Data can only be loaded when the CS pin
is active low. After the new value is fully loaded in the serialinput register, it can be asynchronously transferred to the DAC
register by strobing the LD pin. The DAC register uses a level
sensitive LD strobe that should be returned high before any new
data is loaded into the serial-input register. At any time the
contents of the DAC resister can be reset to zero by strobing the
CLR pin which causes the DAC output voltage to go to zero
volts. All of the timing requirements are detailed in Figure 3
along with Table I. Control Logic Truth Table.
0.1574 (4.00)
0.1497 (3.80)
8
5
1
4
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.0196 (0.50)
3 458
0.0099 (0.25)
0.0500 (1.27)
BSC
0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0040 (0.10)
SEATING
PLANE
88
0.0098 (0.25) 08 0.0500 (1.27)
0.0160 (0.41)
0.0075 (0.19)
0.0192 (0.49)
0.0138 (0.35)
8-Lead Plastic DIP (N-8)
0.430 (10.92)
0.348 (8.84)
All digital inputs are protected with a Zener type ESD protection
structure (Figure 22) that allows logic input voltages to exceed
the VDD supply voltage. This feature can be useful if the user is
loading one or more of the digital inputs with a 5 V CMOS logic
input voltage level while operating the AD8300 on a +3.3 V
power supply. If this mode of interface is used, make sure that
the VOL of the +5 V CMOS meets the VIL input requirement of
the AD8300 operating at 3 V. See Figure 5 for the effect on
digital logic input threshold versus operating VDD supply voltage.
8
5
1
PIN 1
0.210
(5.33)
MAX
0.160 (4.06)
0.115 (2.93)
0.280 (7.11)
0.240 (6.10)
4
0.100 (2.54)
BSC
0.325 (8.25)
0.300 (7.62)
0.015
(0.381)
TYP
0.195 (4.95)
0.115 (2.93)
0.130
(3.30)
MIN
0.022 (0.558) 0.070 (1.77) SEATING
0.014 (0.356) 0.045 (1.15) PLANE
158
08
0.015 (0.381)
0.008 (0.204)
PRINTED IN U.S.A.
VDD
LOGIC
IN
GND
Figure 22. Equivalent Digital Input ESD Protection
Unipolar Output Operation
This is the basic mode of operation for the AD8300. The
AD8300 has been designed to drive loads as low as 400 Ω in
parallel with 500 pF. The code table for this operation is shown
in Table II.
APPLICATIONS INFORMATION
See DAC8512 data sheet for additional application circuit ideas.
–8–
REV. A