BB DAC7612U

®
DAC7612
DAC
761
2
Dual, 12-Bit Serial Input
DIGITAL-TO-ANALOG CONVERTER
FEATURES
DESCRIPTION
● LOW POWER: 3.7mW
● FAST SETTLING: 7µs to 1 LSB
The DAC7612 is a dual, 12-bit digital-to-analog converter (DAC) with guaranteed 12-bit monotonicity
performance over the industrial temperature range. It
requires a single +5V supply and contains an input
shift register, latch, 2.435V reference, a dual DAC, and
high speed rail-to-rail output amplifiers. For a fullscale step, each output will settle to 1 LSB within 7µs
while only consuming 3.7mW.
● 1mV LSB WITH 4.095V FULL-SCALE
RANGE
● COMPLETE WITH REFERENCE
● 12-BIT LINEARITY AND MONOTONICITY
OVER INDUSTRIAL TEMP RANGE
● 3-WIRE INTERFACE: Up to 20MHz Clock
The synchronous serial interface is compatible with a
wide variety of DSPs and microcontrollers. Clock
(CLK), Serial Data In (SDI), Chip Select (CS) and
Load DACs (LOADDACS) comprise the serial interface.
● SMALL PACKAGE: 8-Lead SOIC
APPLICATIONS
● PROCESS CONTROL
The DAC7612 is available in an 8-lead SOIC package
and is fully specified over the industrial temperature
range of –40°C to +85°C.
● DATA ACQUISITION SYSTEMS
● CLOSED-LOOP SERVO-CONTROL
● PC PERIPHERALS
● PORTABLE INSTRUMENTATION
VDD
12-Bit DAC A
VOUTA
12
DAC Register A
LOADDACS
12
CS
CLK
14-Bit Serial Shift Register
SDI
12
Ref
DAC Register B
12
12-Bit DAC B
VOUTB
DAC7612
GND
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1999 Burr-Brown Corporation
PDS-1501A
Printed in U.S.A. June, 1999
SPECIFICATIONS
At TA = –40°C to +85°C, and VDD = +5V, unless otherwise noted.
DAC7612U
PARAMETER
CONDITIONS
RESOLUTION
MIN
DAC7612UB
TYP
MAX
Guaranteed Monotonic
Code 000H
Code 000H
Code FFFH
Code FFFH
ANALOG OUTPUT
Output Current
Load Regulation
Capacitive Load
Short-Circuit Current
Short-Circuit Duration
Code 800H
RLOAD ≥ 402Ω, Code 800H
No Oscillation
±1/2
±1/2
+1
1/2
4.095
1/2
–2
–1
–1
4.079
±5
±7
1
500
±15
Indefinite
GND or VDD
DIGITAL INPUT
Data Format
Data Coding
Logic Family
Logic Levels
VIH
VIL
IIH
IIL
TYP
+2
+1
+3
–1
–1
✻
4.111
4.087
✻
3
Bits
±1/4
±1/4
✻
1/2
4.095
1/2
✻
✻
✻
✻
✻
+4.75
TEMPERATURE RANGE
Specified Performance
–40
+5.0
0.75
3.5
0.0025
LSB
LSB
LSB
LSB
V
LSB
mA
LSB
pF
mA
+5.25
1.5
7.5
0.002
✻
+85
✻
✻
✻
✻
✻
V
V
µA
µA
µs
nV-s
nV-s
✻
✻
✻
7
2.5
0.5
V IH = 5V, VIL = 0V, No Load, at Code 000H
VIH = 5V, VIL = 0V, No Load
∆VDD = ±5%
✻
✻
✻
✻
0.3 • VDD
±10
±10
POWER SUPPLY
VDD
IDD
Power Dissipation
Power Supply Sensitivity
+1
+1
✻
2
4.103
2
✻
0.7 • VDD
To ±1 LSB of Final Value
UNITS
✻
✻
✻
Serial
Straight Binary
CMOS
DYNAMIC PERFORMANCE
Settling Time(2) (tS)
DAC Glitch
Digital Feedthrough
MAX
✻
12
ACCURACY
Relative Accuracy(1)
Differential Nonlinearity
Zero-Scale Error
Zero Scale Match
Full-Scale Voltage
Full-Scale Match
MIN
✻
✻
✻
✻
V
mA
mW
%/%
✻
°C
✻ Same specification as for DAC7612U.
NOTES: (1) This term is sometimes referred to as Linearity Error or Integral Nonlinearity (INL). (2) Specification does not apply to negative-going transitions where
the final output voltage will be within 3 LSBs of ground. In this region, settling time may be double the value indicated.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
DAC7612
2
PIN CONFIGURATION
PIN DESCRIPTIONS
Top View
PIN
SO-8
LABEL
1
SDI
1
CLK
2
LOADDACS
3
CS
4
DAC7612U
8
VOUTA
7
VDD
6
GND
5
VOUTB
DESCRIPTION
SDI
Serial Data Input. Data is clocked into the internal
serial register on the rising edge of CLK.
2
CLK
3
LOADDACS
Synchronous Clock for the Serial Data Input.
Loads the internal DAC registers. All DAC registers
are transparent latches and are transparent when
LOADDACS is LOW (regardless of the state of CS
or CLK).
4
CS
5
VOUTB
DAC B Output Voltage
6
GND
Ground
7
VDD
Positive Power Supply
8
VOUTA
DAC A Output Voltage
ABSOLUTE MAXIMUM RATINGS(1)
Chip Select. Active LOW.
ELECTROSTATIC
DISCHARGE SENSITIVITY
VDD to GND .......................................................................... –0.3V to 6V
Digital Inputs to GND .............................................. –0.3V to VDD + 0.3V
VOUT to GND ........................................................... –0.3V to VDD + 0.3V
Power Dissipation ........................................................................ 325mW
Thermal Resistance, θJA ........................................................... 150°C/W
Maximum Junction Temperature .................................................. +150°C
Operating Temperature Range ...................................... –40°C to +85°C
Storage Temperature Range ....................................... –65°C to +150°C
Lead Temperature (soldering, 10s) .............................................. +300°C
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION
PRODUCT
MINIMUM
RELATIVE
ACCURACY
(LSB)
DIFFERENTIAL
NONLINEARITY
(LSB)
SPECIFICATION
TEMPERATURE
RANGE
PACKAGE
PACKAGE
DRAWING
NUMBER(1)
DAC7612U
±2
±1
–40°C to +85°C
SO-8
182
"
"
"
"
"
"
DAC7612UB
±1
±1
–40°C to +85°C
SO-8
182
"
"
"
"
"
"
ORDERING
NUMBER(2)
TRANSPORT
MEDIA
DAC7612U
DAC7612U/2K5
DAC7612UB
DAC7612UB/2K5
Rails
Tape and Reel
Rails
Tape and Reel
NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are
available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “DAC7612U/2K5” will get a single
2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.
®
3
DAC7612
EQUIVALENT INPUT LOGIC
ESD protection
diodes to VDD
and GND
DAC Switches
12
DAC B Register
LOADDACS
12
Data
SDI
Serial Shift Register
CS
12
DAC A Register
CLK
12
DAC Switches
®
DAC7612
4
TIMING DIAGRAMS
(MSB)
SDI
A0
A1
(LSB)
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CLK
tCSS
tCSH
CS
tLD1
tLD2
LOADDACS
tDS
tDH
SDI
tCL
tCH
CLK
tLDW
LOADDACS
tS
FS
±1 LSB
Error Band
VOUT
ZS
LOGIC TRUTH TABLE
TIMING SPECIFICATIONS
SERIAL SHIFT
DAC
REGISTER REGISTER A
TA = –40°C to +85°C and VDD = +5V.
DAC
REGISTER B
A1
A0
CLK
CS
LOADDACS
X
X
X
H
H
No Change
No Change
No Change
X
X
↑
L
H
Shifts One Bit
No Change
No Change
L
No Change
Loads Serial
Data Word
SYMBOL
DESCRIPTION
tCH
Clock Width HIGH
MIN TYP MAX UNITS
30
ns
Loads Serial
Data Word
tCL
Clock Width LOW
30
ns
L
X
X
H(1)
tLDW
Load Pulse Width
20
ns
H
L
X
H
L
No Change
Loads Serial
Data Word
No Change
tDS
Data Setup
15
ns
15
ns
H
X
H
L
No Change
No Change
Loads Serial
Data Word
tDH
Data Hold
H
t LD1
Load Setup
15
ns
↑ Positive Logic Transition; X = Don’t Care.
NOTE: (1) A HIGH value is suggested in order to avoid to “false clock” from
advancing the shift register and changing the DAC voltage.
t LD2
Load Hold
10
ns
tCSS
Select
30
ns
t CSH
Deselect
20
ns
NOTE: All input control signals are specified with tR = tF = 5ns (10% to 90%
of +5V) and timed from a voltage level of 2.5V. These parameters are
guaranteed by design and are not subject to production testing.
DATA INPUT TABLE
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10 B11 B12 B13
A1
A0
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
®
5
DAC7612
TYPICAL PERFORMANCE CURVES
At TA = +25°, and VDD = 5V, unless otherwise specified.
PULL-DOWN VOLTAGE vs OUTPUT SINK CURRENT
OUTPUT SWING vs LOAD
5
1k
+85°C
100
RL tied to GND
Data = FFFH
Delta VOUT (mV)
Output Voltage (V)
4
3
2
1
10
+25°C
1
–40°C
0.1
RL tied to VDD
Data = 000H
Data = 000H
0
10
100
1k
10k
0.01
0.001
100k
0.01
0.1
Load Resistance (Ω)
1
10
100
Current (mA)
BROADBAND NOISE
SUPPLY CURRENT vs LOGIC INPUT VOLTAGE
4.0
Supply Current (mA)
Noise Voltage (500µV/div)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
Time (2ms/div)
Code = FFFH, BW = 1MHz
2
3
4
5
Logic Voltage (V)
POWER SUPPLY REJECTION vs FREQUENCY
MINIMUM SUPPLY VOLTAGE vs LOAD
70
5.0
Data = FFFH
VDD = 5V
±200mV AC
60
4.8
VDD Minimum (V)
50
PSR (dB)
1
40
30
20
4.6
4.4
4.2
10
0
10
100
1k
10k
100k
4.0
0.01
1M
Frequency (Hz)
®
DAC7612
0.1
1
Output Load Current (mA)
6
10
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°, and VDD = 5V, unless otherwise specified.
SHORT-CIRCUIT CURRENT vs OUTPUT VOLTAGE
SUPPLY CURRENT vs TEMPERATURE
2.0
20
Supply Current (mA)
1.6
Data = 800H
Output tied to ISOURCE
5
0
–5
–10
Negative
Current
Limit
–15
VDD = 5.25V
1.4
1.2
1.0
VDD = 4.75V
0.8
0.6
0.4
At worst-case digital inputs.
0.2
0
–20
0
1
2
3
4
5
6
–50
–30
–10
10
30
50
70
90
Output Voltage (V)
Temperature (°C)
MIDSCALE GLITCH PERFORMANCE
MIDSCALE GLITCH PERFORMANCE
LOADDACS
110
130
VOUT (5mV/div)
VOUT (5mV/div)
LOADDACS
7FFH to 800H
800H to 7FFH
Time (500ns/div)
Time (500ns/div)
LARGE-SIGNAL SETTLING TIME
RISE TIME DETAIL
LOADDACS
CL = 100pF
RL = No Load
VOUT (1mV/div)
CL = 100pF
RL = No Load
VOUT (1V/div)
Output Current (mA)
10
VDD = 5.0V
VLOGIC = 3.5V
Data = FFFH
No Load
1.8
Positive
Current
Limit
15
LOADDACS
Time (10µs/div)
Time (20µs/div)
®
7
DAC7612
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°, and VDD = 5V, unless otherwise specified.
FALL TIME DETAIL
OUTPUT VOLTAGE NOISE vs FREQUENCY
10.000
CL = 100pF
RL = No Load
VOUT (1mV/div)
Noise (µV/√Hz)
Data = FFFH
1.000
0.100
LOADDACS
0.010
Time (10µs/div)
10
100
1k
10k
100k
Frequency (Hz)
TOTAL UNADJUSTED ERROR HISTOGRAM
LONG-TERM DRIFT ACCELERATED BY BURN-IN
35
4
Max
3
2
1
Avg
0
–1
–2
T.U.E = Σ (INL + ZSE + FSE)
Sample Size = 200 Units
TA = +25°C
30
Number of Units
Output Voltage Change at FS (mV)
5
Min
–3
25
20
15
10
5
–4
0
–5
0
168
336
504
672
840
1008
–12 –10 –8
–6
–4
–2
0
2
4
6
8
10
12
Hours of Operation at +150°C
FULL-SCALE VOLTAGE vs TEMPERATURE
ZERO-SCALE VOLTAGE vs TEMPERATURE
4.111
3
Avg + 3σ
Zero-Scale Output (mV)
Full-Scale Output (V)
Avg + 3σ
4.103
Avg
4.095
4.087
2
Avg
1
Avg – 3σ
0
Avg – 3σ
4.079
–1
–40
–15
10
35
60
85
–40
Temperature (°C)
10
35
Temperature (°C)
®
DAC7612
–15
8
60
85
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°, and VDD = 5V, unless otherwise specified.
LINEARITY ERROR vs DIGITAL CODE
(DAC B at +85°C)
2.0
2.0
1.5
1.5
1.0
Linearity Error (LSBs)
Linearity Error (LSBs)
LINEARITY ERROR vs DIGITAL CODE
(DAC A at +85°C)
0.5
0
–0.5
–1.0
–1.5
0
–0.5
–1.0
–2.0
0
512
1024
1536
2048
2560
3072
3584
4096
0
512
1024
1536
2048
2560
3072
Code
Code
LINEARITY ERROR vs DIGITAL CODE
(DAC A at +25°C)
LINEARITY ERROR vs DIGITAL CODE
(DAC B at +25°C)
2.0
2.0
1.5
1.5
Linearity Error (LSBs)
Linearity Error (LSBs)
0.5
–1.5
–2.0
1.0
0.5
0
–0.5
–1.0
3584
4096
3584
4096
3584
4096
1.0
0.5
0
–0.5
–1.0
–1.5
–1.5
–2.0
–2.0
0
512
1024
1536
2048
2560
3072
3584
0
4096
512
1024
1536
2048
2560
3072
Code
Code
LINEARITY ERROR vs DIGITAL CODE
(DAC A at –40°C)
LINEARITY ERROR vs DIGITAL CODE
(DAC B at –40°C)
2.0
2.0
1.5
1.5
1.0
Linearity Error (LSBs)
Linearity Error (LSBs)
1.0
0.5
0
–0.5
–1.0
–1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.0
0
512
1024
1536
2048
2560
3072
3584
4096
0
Code
512
1024
1536
2048
2560
3072
Code
®
9
DAC7612
next 12 bits are the code (MSB-first) sent to the DAC. The
data format is Straight Binary and is loaded MSB-first into
the shift registers after loading the address bits. Table I shows
the relationship between input code and output voltage.
OPERATION
The DAC7612 is a dual, 12-bit digital-to-analog converter
(DAC) complete with a serial-to-parallel shift register, DAC
registers, laser-trimmed 12-bit DACs, on-board reference,
and rail-to-rail output amplifiers. Figure 1 shows the basic
operation of the DAC7612.
The digital data into the DAC7612 is double-buffered. This
means that new data can be entered into the chosen DAC
without disturbing the old data and the analog output of the
converter. At some point after the data has been entered into
the serial shift register, this data can be transferred into the
DAC registers. This transfer is accomplished with a HIGH
to LOW transition of the LOADDACS pin. The LOADDACS
pin makes the DAC registers transparent. If new data is
shifted into the shift register while LOADDACS is LOW,
the DAC output voltages will change as each new bit is
entered. To prevent this, LOADDACS must be returned
HIGH prior to shifting in new serial data.
INTERFACE
Figure 1 shows the basic connection between a
microcontroller and the DAC7612. The interface consists of
a Serial Clock (CLK), Serial Data (SDI), and a Load DAC
signal (LOADDACS). In addition, a chip select (CS) input is
available to enable serial communication when there are
multiple serial devices. Loading either DAC A or DAC B is
done by shifting 14 serial bits in via the SDI input. The first
2 bits represent the address of the DAC to be updated and the
DIGITAL-TO-ANALOG CONVERTER
The internal DAC section is a 12-bit voltage output
device that swings between ground and the internal reference voltage. The DAC is realized by a laser-trimmed
R-2R ladder network which is switched by N-channel
MOSFETs. Each DAC output is internally connected to a
rail-to-rail output operational amplifier.
DAC7612 Full-Scale Range = 4.095V
Least Significant Bit = 1mV
DIGITAL INPUT CODE
STRAIGHT OFFSETBINARY
ANALOG OUTPUT
(V)
DESCRIPTION
FFFH
+4.095
801H
+2.049
Full Scale
Midscale + 1 LSB
800H
+2.048
Midscale
7FFH
+2.047
Midscale – 1 LSB
000H
0
OUTPUT AMPLIFIER
A precision, low-power amplifier buffers the output of each
DAC section and provides additional gain to achieve a 0V to
4.095V range. Each amplifier has low offset voltage, low
Zero Scale
TABLE I. Digital Input Code and Corresponding Ideal
Analog Output.
DAC7612U
Serial Data
1
SDI
VOUTA
8
Serial Clock
2
CLK
VDD
7
Load DACs
3
LOADDACS
GND
6
Chip Select
4
CS
VOUTB
5
0V to +4.095V
0.1µF
FIGURE 1. Basic Operation of the DAC7612.
®
DAC7612
10
+
10µF
0V to +4.095V
If power consumption is critical, it is important to keep the
logic levels on the digital inputs (SDI, CLK, CS,
LOADDACS) as close as possible to either VDD or ground.
This will keep the CMOS inputs (see “Supply Current vs
Logic Input Voltages” in the Typical Performance Curves)
from shunting current between VDD and ground.
noise, and a set gain of 1.682V/V (4.095/2.435). See Figure
2 for an equivalent circuit schematic of the analog portion of
the DAC7612.
The output amplifier has a 7µs typical settling time to ±1
LSB of the final value. Note that there are differences in the
settling time for negative-going signals versus positivegoing signals.
The rail-to-rail output stage of the amplifier provides the fullscale range of 0V to 4.095V while operating on a supply voltage
as low as 4.75V. In addition to its ability to drive resistive loads,
the amplifier will remain stable while driving capacitive loads
of up to 500pF. See Figure 3 for an equivalent circuit schematic
of the amplifier’s output driver and the Typical Performance
Curves section for more information regarding settling time,
load driving capability, and output noise.
The DAC7612 power supply should be bypassed as shown
in Figure 1. The bypass capacitors should be placed as close
to the device as possible, with the 0.1µF capacitor taking
priority in this regard. The “Power Supply Rejection vs
Frequency” graph in the Typical Performance Curves section shows the PSRR performance of the DAC7612. This
should be taken into account when using switching power
supplies or DC/DC converters.
In addition to offering guaranteed performance with VDD in
the 4.75V to 5.25V range, the DAC7612 will operate with
reduced performance down to 4.5V. Operation between
4.5V and 4.75V will result in longer settling time, reduced
performance, and current sourcing capability. Consult the
“VDD vs Load Current” graph in the Typical Performance
Curves section for more information.
POWER SUPPLY
A BiCMOS process and careful design of the bipolar and
CMOS sections of the DAC7612 result in a very low power
device. Bipolar transistors are used where tight matching
and low noise are needed to achieve analog accuracy, and
CMOS transistors are used for logic, switching functions
and for other low power stages.
R-2R DAC
2R
Output Amplifier
R
Buffer
Bandgap
Reference
2R
R2
2.435V
R
R1
2R
R
2R
Typical of DAC A or DAC B
2R
FIGURE 2. Simplified Schematic of Analog Portion.
VDD
P-Channel
VOUT
N-Channel
GND
FIGURE 3. Simplified Driver Section of Output Amplifier.
®
11
DAC7612
reference point for the internal bandgap reference. Ideally,
GND would be connected directly to an analog ground
plane. This plane would be separate from the ground connection for the digital components until they are connected
at the power entry point of the system (see Figure 4).
APPLICATIONS
POWER AND GROUNDING
The DAC7612 can be used in a wide variety of situations—
from low power, battery operated systems to large-scale
industrial process control systems. In addition, some applications require better performance than others, or are particularly sensitive to one or two specific parameters. This
diversity makes it difficult to define definite rules to follow
concerning the power supply, bypassing, and grounding.
The following discussion must be considered in relation to
the desired performance and needs of the particular system.
The power applied to VDD should be well regulated and lownoise. Switching power supplies and DC/DC converters will
often have high-frequency glitches or spikes riding on the
output voltage. In addition, digital components can create
similar high frequency spikes as their internal logic switches
states. This noise can easily couple into the DAC output
voltage through various paths between VDD and VOUT.
As with the GND connection, VDD should be connected to
a +5V power supply plane or trace that is separate from the
connection for digital logic until they are connected at the
power entry point. In addition, the 10µF and 0.1µF capacitors shown in Figure 4 are strongly recommended and
should be installed as close to VDD and ground as possible.
In some situations, additional bypassing may be required
such as a 100µF electrolytic capacitor or even a “Pi” filter
made up of inductors and capacitors—all designed to essentially lowpass filter the +5V supply, removing the high
frequency noise (see Figure 4).
A precision analog component requires careful layout, adequate bypassing, and a clean, well-regulated power supply.
As the DAC7612 is a single-supply, +5V component, it will
often be used in conjunction with digital logic,
microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the
higher the switching speed, the more difficult it will be to
achieve good performance.
Because the DAC7612 has a single ground pin, all return
currents, including digital and analog return currents, must
flow through this pin. The GND pin is also the ground
Digital Circuits
+5V
Power
Supply
+5V
+5V
GND
DAC7612
GND
100µF
+
+
VDD
10µF
0.1µF
GND
Optional
Other
Analog
Components
FIGURE 4. Suggested Power and Ground Connections for a DAC7612 Sharing a +5V Supply with a Digital System.
®
DAC7612
12