ST20C2/C4 Core
Instruction Set
Reference Manual
72-TRN-273-01
January 1996
2/212
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11
1.12
2
Instruction name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Error signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Comments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Notation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.7.1 The processor state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.7.2 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.7.3 Undefined values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.7.4 Data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.7.5 Representing memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.7.6 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Block move registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Operators used in the definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Conditions to instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Addressing and data representation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.1 Word address and byte selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.2 Ordering of information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.3 Signed integers and sign extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.1 Machine registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.1.1 Process state registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.1.2 Other machine registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.2 The process descriptor and its associated register fields . . . . . . . . . . . . . 24
4
Instruction representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.1 Instruction encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.1.1 An instruction component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.1.2 The instruction data value and prefixing . . . . . . . . . . . . . . . . . . .25
4.1.3 Primary Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.1.4 Secondary instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.1.5 Summary of encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.2 Generating prefix sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.2.1 Prefixing a constant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.2.2 Evaluating minimal symbol offsets . . . . . . . . . . . . . . . . . . . . . . . .29
5
Instruction Set Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
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Contents
4/212
1
Introduction
This manual provides a summary and reference to the ST20 instruction set for C2 and
C4 cores. The instructions are listed in alphabetical order, one to a page. Descriptions
are presented in a standard format with the instruction mnemonic and full name of the
instruction at the top of the page, followed by these categories of information:
•
Code: the instruction code;
•
Description: a brief summary of the purpose and behavior of the instruction;
•
Definition: a more complete description of the instruction, using the notation
described below in section 1.7;
•
Error signals: a list of errors and other signals which can occur;
•
Comments: a list of other important features of the instruction;
•
See also: for some instructions, a cross reference is provided to other instructions with a related function.
These categories are explained in more detail below, using the add instruction as an
example.
1.1
Instruction name
The header at the top of each page shows the instruction mnemonic and, on the right,
the full name of the instruction. For primary instructions the mnemonic is followed by
‘n’ to indicate the operand to the instruction; the same notation is used in the
description to show how the operand is used.
1.2
Code
For secondar y instructions the instruction ‘operation code’ is shown as the memory
code — the actual bytes, including any prefixes, which are stored in memory. The
value is given as a sequence of bytes in hexadecimal, decoded left to right. The codes
are stored in memory in ‘little-endian’ format — with the first byte at the lowest
address.
For primary instructions the code stored in memory is determined partly by the value
of the operand to the instruction. In this case the op-code is shown as ‘Function x’
where x is the function code in the last byte of the instruction. For example, adc (add
constant) is shown as ‘Function 8’.
Example
The entry for the add instruction is:
Code: F5
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1.3
Description
The description section provides an indication of the purpose of the instruction as well
as a summary of the behavior. This includes details of the use of registers, whose
initial values may be used as parameters and into which results may be stored.
Example
The add instruction contains the following description:
Description: Add Areg and Breg, with checking for overflow.
1.4
Definition
The definition section provides a formal description of the behavior of the instruction.
The behavior is defined in ter ms of its effect on the state of the processor (i.e. the
values in registers and memory before and after the instruction has executed).
The effects of the instruction on registers, etc. are given as relationships of the
following form:
register′
←
expression involving registers, etc.
Primed names (e.g. Areg′ ) represent values after instruction execution, while
unprimed names represent values when instruction execution starts. For example,
Areg represents the value in Areg before the execution of the instruction while Areg′
represents the value in Areg afterwards. So, the example above states that the
register on the left hand side becomes equal to the value of the expression on the
right hand side after the instruction has been executed.
The description is written with the main function of the instruction stated first (e .g. the
main function of the add instruction is to put the sum of Areg and Breg into Areg).
This is followed by the other effects of the instruction (e.g. popping the stack). There is
no temporal ordering implied by the order in which the statements are written.
The notation is described more fully in section 1.7.
Example
The add instruction contains the following description:
Definition:
Areg′
←
Breg + checked Areg
Breg′
Creg′
←
←
Creg
undefined
This says that the integer stack is popped and Areg assigned the sum of the values
that were initially in Breg and Areg. After the instruction has executed Breg contains
the value that was originally in Creg, and Creg is undefined.
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1.5
Error signals
This section lists the errors and other exceptional conditions that can be signalled by
the instruction. This only indicates the error signal, not the action that will be taken by
the processor - this will depend on the trap enable bits which are set, the value in the
trap handler location, etc.
The order of the error signals listed is significant in that if a par ticular error is signalled
then errors later in the list may not be signalled. The errors that may be signalled are
as follows:
IntegerError indicates a variety of general errors such as a value out of range.
IntegerOverflow indicates that an overflow occurred during an integer arithmetic operation.
LoadTrap indicates that an attempt has been made to load a new trap handler.
This provides a basic mechanism for a supervisor kernel to manage user processes installing trap handlers.
StoreTrap, analogous to LoadTrap, indicates that an attempt has been made to
store a trap handler so that it can be inspected. Again this allows a supervisor
kernel to manage the trap system used by user processes.
Example
As an example, the error signals listed for the add instruction are:
Error signals:
IntegerOverflow can be signalled by +checked
So, the only error that can be caused by add is an integer overflow during the addition
of Areg and Breg.
1.6
Comments
This section is used for listing other information about the instructions that may be of
interest. Firstly, there is an indication of the type of the instruction. These are:
“Primary instruction” — indicates one of the 13 functions which are directly
encoded in a single byte instruction.
“Secondary instruction” — indicates an instruction which is encoded using opr.
Then there is information concerning the scheduling of the process:
“Instruction is a descheduling point” — a process may be descheduled after
executing this instruction.
“Instruction is a timeslicing point” — a process may be timesliced after executing this instruction.
“Instruction is interruptible” — the execution of this instruction may be interrupted by a high priority process.
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This section also describes any situations where the operation of the instruction is
undefined or invalid.
Example
Using the add instruction as an example again, the comments listed are:
Comments:
Secondary instruction.
This says that add is a secondar y instruction.
1.7
Notation
The following sections give a full description of the notation used in the ‘definition’
section of the instruction descriptions.
1.7.1
The processor state
The processor state consists of the registers (mainly Areg, Breg, Creg, Iptr, and
Wptr), the contents of memory, and various flags and special registers (such as the
error flags , process queue pointers, clock registers, etc.).
The Wptr register is used for the address of the workspace of the current process.
This address is word aligned and therefore has the two least significant bits set to
zero. Wdesc is used for the ‘process descriptor’ — the value that is held in memory as
an identifier of the process when the process is not being executed. This value is
composed of the top 31 bits of the Wptr plus the process priority stored in bit 0 of the
word. Bit 0 is set to 0 for high priority processes and 1 for low priority processes. Bit 1
of the process descriptor is always 0.
1.7.2
General
The instruction descriptions are not intended to describe the way the instructions are
implemented, but only their effect on the state of the processor. So, for example, the
block move instructions are described in terms of a sequence of byte reads and writes
even though the instructions are implemented to perform the minimum number of
word reads and writes.
Comments (in italics) are used to both clarify the description and to describe actions
or values that cannot easily be represented by the notation used here; e.g. start next
process. These actions may be performed in another subsystem in the device, such
as the communications subsystem, and so any changes to machine state are not
necessarily completely synchronized with the execution of the instruction (as the
different subsystems work independently and in parallel).
Ellipses are used to show a range of values; e.g. ‘i = 0..31’ means that i has
values from 0 to 31, inclusive.
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Subscripts are used to indicate particular bits in a word; e.g. Aregi for bit i of Areg; and
Areg0..7 for the least significant byte of Areg. Note that bit 0 is the least significant bit in
a word, and bit 31 is the most significant bit.
Generally, if the description does not mention the state of a register or memory
location after the instruction, then the value will not be changed by the instruction.
One exception to this general rule is Iptr, which is assigned the address of the next
instruction in the code before every instruction execution starts. The Iptr is included in
the description only when it is directly affected by the instruction (e.g. in the jump
instruction). In these cases the address of the next instruction is indicated by the
comment “next instruction”.
Scheduling operations
Some registers, such as the timer and scheduling list pointers and some special
workspace locations, can be changed at any time by scheduling operations. Changes
to these are included in the description only when they are directly caused by the
instruction, and not just as an effect of any scheduling operation which might take
place.
1.7.3
Undefined v alues
Many instructions leave the contents of a register or memory location in an undefined
state. This means that the value of the location may be changed by the instruction, but
the new value cannot be easily defined, or is not a meaningful result of the instruction.
For example, when the integer stack is popped, Creg becomes undefined, i.e. it does
not contain any meaningful data. An undefined value is represented by the name
undefined. The values of registers which become undefined as a result of executing
an instruction are implementation dependent and are not guaranteed to be the same
on different members of the ST20 family of processors.
1.7.4
Data types
The instruction set includes operations on four sizes of data: 8, 16, 32 and 64-bit
objects. 8-bit and 16-bit data can represent signed or unsigned integers; 32-bit data
can represent addresses, signed or unsigned integers, or single length floating point
numbers; and 64-bit data can represent signed or unsigned integers, or double length
floating point values. Normally it is clear from the context (e.g. from the operators
used) whether a particular object represents a signed, unsigned or floating point
number. A subscripted label is added (e.g. Aregunsigned) to clarify where necessary.
1.7.5
Representing memory
The memory is represented by arrays of each data type. These are indexed by a value
representing a byte address. Access to the four data types is represented in the
instruction descriptions in the following way:
byte[address]references a byte in memory at the given address
sixteen[address]references a 16-bit object in memory
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word[address]references a 32-bit word in memory
For all of these, the state of the machine referenced is that before the instruction if the
function is used without a prime (e.g. word[]), and that after the instruction if the
function is used with a prime (e.g. word′[]).
For example, writing a value given by an expression, expr, to the word in memory at
address addr is represented by:
word′[addr] ← expr
and reading a word from a memory location is achieved by:
Areg′ ← word[addr]
Writing to memory in any of these ways will update the contents of memory, and these
updates will be consistently visible to the other representations of the memory, e.g.
writing a byte at address 0 will modify the least significant byte of the word at address
0.
Reading and writing in this way cannot be used to access on-chip peripherals.
Reading or writing to memory addresses between PeripheralStart and PeripheralEnd
will have undefined effects.
Data alignment
Each of these data items have restrictions on their alignment in memory. Byte values
can be accessed at any byte address, i.e. they are byte aligned. 16-bit objects can
only be accessed at even byte addresses, i.e. the least significant bit of the address
must be 0. 32-bit and 64-bit objects must be word aligned, i.e. the 2 least significant
bits of the address must be zero.
Address calculation
An address identifies a par ticular byte in memory. Addresses are frequently calculated
from a base address and an offset. For different instructions the offset may be given in
units of bytes, words or double words depending on the data type being accessed. In
order to calculate the address of the data, the offset must be converted to a byte offset
before being added to the base address. This is done by multiplying the offset by the
number of bytes in the particular units being used. So, for example, a word offset is
converted to a byte offset by multiplying it by the number of bytes in a word (4 in the
case of the ST20).
As there are many accesses to memory at word offsets, a shorthand notation is used
to represent the calculation of a word address. The notation register @ x is used to
represent an address which is offset by x words (4x bytes) from register. For example,
in the specification of load non-local there is:
Areg′ ← word[Areg @ n]
Here, Areg is loaded with the contents of the word that is n words from the address
pointed to by Areg (i.e. Areg + 4n).
In all cases, if the given base address has the correct alignment then any offset used
will also give a correctly aligned address.
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1.7.6
On-chip peripherals
On-chip peripherals may have memory-mapped registers in the address range
PeripheralStart to PeripheralEnd. Access to these registers is represented in the
following way:
PeripheralByte[address] references an 8-bit peripheral register
PeripheralSixteen[address] references a 16-bit peripheral register
PeripheralWord[address] references a 32-bit peripheral register
For all of these, the state of the peripheral referenced is that before the instruction if
the function is used without a prime (e.g. PeripheralWord[]), and that after the
instruction if the function is used with a prime (e.g. PeripheralWord′[]).
For example, writing a value given by an expression, expr, to the register at address
addr is represented by:
PeripheralWord′[addr] ← expr
and reading a word from a peripheral is achieved by:
Areg′ ← PeripheralWord[addr]
1.8
Block move registers
A group of registers is used in the implementation of block moves. These are referred
to as the ‘block move registers’ and include Move2dBlockLength, Move2dDestStride,
and Move2dSourceStride.
1.9
Constants
A number of data structures have been defined in this book. Each compr ises a
number of data slots that are referenced by name in the text and the following
instructions descriptions.
These data structures is listed in Table 1.2 to Table 1.4.
word offset
slot name
purpose
0
pw.Temp
slot used by some instructions for storing temporary values
-1
pw.Iptr
the instruction pointer of a descheduled process
-2
pw.Link
the address of the workspace of the next process in scheduling list
-3
pw.Pointer
saved pointer to communication data area
-3
pw.State
saved alternative state
-4
pw.TLink
address of the workspace of the next process on the timer list
-5
pw.Time
time that a process on a timer list is waiting for
Table 1.1 Process workspace data structure
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word offset
slot name
purpose
0
le.Index
contains the loop control variable
1
le.Count
contains number of iterations left to perform
Table 1.2 Loop end data structure
word offset
slot name
purpose
1
pp.Count
contains unsigned count of parallel processes
0
pp.IptrSucc
contains pointer to first instr uction of successor process
Table 1.3 Parallel process data structure
word offset
slot name
purpose
2
s.Back
back of waiting queue
1
s.Front
front of waiting queue
0
s.Count
number of extra processes that the semaphore will allow to continue
running on a wait request
Table 1.4 Semaphore data structure
In addition, a number of constants are used to identify word length related values etc.;
These are listed in Table 1.5 .
Name
Value
Meaning
BitsPerByte
8 The number of bits in a byte.
BitsPerWord
32 The number of bits in a word.
ByteSelectMask
#00000003 Used to select the byte select bits of an address.
WordSelectMask
#FFFFFFFC Used to select the byte select bits of an address.
BytesPerWord
4 The number of bytes in a word.
MostNeg
#80000000 The most negative integer value.
MostPos
#7FFFFFFF The most positive signed integer value.
MostPosUnsigned
#FFFFFFFF The most positive unsigned integer value.
PeripheralStart
#20000000 The lowest address reserved for memory-mapped onchip peripherals.
PeripheralEnd
#3FFFFFFF The highest address reserved for memory-mapped onchip peripherals.
Table 1.5 Constants used in the instruction descriptions
A number of values are used by the ST20 to indicate the state of a process and other
conditions. These are listed in Table 1.6.
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Name
Value
Meaning
DeviceId
Depends on processor type. See
below.
A value used to identify the type and revision of processor.
Returned by the ldprodid and lddevid instructions.
Disabling.p
MostNeg + #03 Stored in the pw.State location while an alternative is being
#80000003 disabled.
Enabling.p
MostNeg + #01 Stored in the pw.State location while an alternative is being
#80000001 enabled.
false
NoneSelected.o
NotProcess.p
0 The boolean value ‘false’.
-1 Stored in the pw.Temp slot of a process’ workspace while no
#FFFFFFFF branch of an alternative has yet been selected during the
waiting and disabling phases.
MostNeg Used, wherever a process descriptor is expected, to indicate
#80000000 that there is no process.
Ready.p
MostNeg + #03 Stored in the pw.State location during the enabling phase of
#80000003 an alternative, to indicate that a guard is ready.
TimeNotSet.p
MostNeg + #02 Stored in pw.TLink location during enabling of a timer alter#80000002 native after a time to wait for has been encountered.
TimeSet.p
MostNeg + #01 Stored in pw.TLink location during enabling of a timer alter#80000001 native after a time to wait for has been encountered.
true
Waiting.p
1 The boolean value ‘true’.
MostNeg + #02 Stored in the pw.State location by altwt and taltwt to indicate
#80000002 that the alternative is waiting.
HighPriority
0 High priority
LowPriority
1 Low priority
Table 1.6 Constants used within the ST20
Product identity values
These are values returned by the lddevid and ldprodid instructions. For specific
product ids in the ST20 family refer to SGS-THOMSON.
1.10 Operators used in the definitions
Modulo operators
Arithmetic on addresses is done using modulo arithmetic — i.e. there is no checking
for errors and, if the calculation overflows, the result ‘wraps around’ the range of
values representable in the word length of the processor — e.g. adding 1 to the
address at the top of the address map produces the address of the byte at the bottom
of the address map. There is also a number of instructions for performing modulo
arithmetic, such as sum, prod, etc. These operators are represented by the symbols
‘+’, ‘−’, etc.
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Error conditions
Any errors that can occur in instructions which are defined in ter ms of the modulo
operators are indicated explicitly in the instruction description. For example the div
(divide) instruction indicates the cases that can cause overflow, independently of the
actual division:
if (Areg = 0) or ((Breg = MostNeg) and (Areg = -1))
{
Areg′ ← undefined
IntegerOverflow
}
else
Areg′ ←
Breg′ ←
Creg′ ←
Breg / Areg
Creg
undefined
Checked operators
To simplify the description of checked arithmetic, the operators ‘+checked’, ‘−checked’,
etc. are used to indicate operations that perform checked arithmetic on signed
integers. These operators signal an IntegerOverflow if an overflow, divide by zero, or
other arithmetic error occurs. If no trap is taken, the operators also deliver the modulo
result.
A number of comparison operators are also used and there are versions of some of
these that treat the operands as unsigned integers. A full list of the operators used in
the instruction definitions is giv en in Table 1.7.
1.11 Functions
Type conversions
The following function is used to indicate a type conversion:
unsign(x) causes the bit-pattern in x to be interpreted as an unsigned integer.
1.12 Conditions to instructions
In many cases, the action of an instruction depends on the current state of the
processor. In these cases the conditions are shown by an if clause; this can take one
of the following forms:
•
if condition
statement
•
if condition
statement
else
statement
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Symbol
Meaning
Integer arithmetic with overflow checking
+checked
−checked
×checked
Add, subtract, and multiply of signed integers. If the computation overflows an
IntegerOverflow is signalled and the result of the operation is truncated to the
word length.
Unchecked (modulo) integer arithmetic
+
−
×
/
rem
Integer add, subtract, multiply, divide and remainder. If the computation overflo ws the result of the operation is truncated to the word length. If a divide or
remainder by zero occurs the result of the operation is undefined. No errors are
signalled. The operator ‘−’ is also used as a monadic operator. The sign of the
remainder is the same as the sign of the dividend.
Signed comparison operators
<
>
≤
≥
=
≠
Comparisons of signed integer and floating point v alues: ‘less than’, ‘greater
than’, ‘less than or equal’, ‘greater than or equal’, ‘equal’ and ‘not equal’.
Unsigned comparison operators
<unsigned
>unsigned
≥unsigned
after
Comparisons of unsigned integer values: ‘less than’, ‘greater than’, ‘greater than
or equal’, and ‘after’ (for comparison of times).
Logical bitwise operations
∼ (or BITNOT)
∧ (or BITAND)
∨ (or BITOR)
⊗ (or BITXOR)
>>
<<
‘Not’ (1’s complement), ‘and’, ‘or’, ‘exclusive or’, and logical left and right shift
operations on bits in words.
Boolean operators
not
and
or
•
Boolean combination in conditionals.
Table 1.7 Operators used in the instruction descriptions
if condition
statement
else if condition
statement
else
statement
These conditions can be nested. Braces, {}, are used to group statements which are
dependent on a condition. For example, the cj (conditional jump) instruction contains
the following lines:
if (Areg = 0)
IptrReg′ ←
next instruction + n
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else
{
IptrReg′ ←
Areg′ ←
Breg′ ←
Creg′ ←
next instruction
Breg
Creg
undefined
}
This says that if the value in Areg is zero, then the jump is taken (the instruction
operand, n, is added to the instruction pointer), otherwise the stack is popped and
execution continues with the next instruction.
16/212
2
Addressing and data representation
The ST20 processor is a 32-bit word machine, with byte addressing and a 4 Gbyte
address space. This chapter explains how data is loaded from and stored into that
address space, explains how signed arithmetic is represented, and defines the
arithmetic significance of order ing of data items.
2.1
Word address and byte selector
A machine address is a single word of data which identifies a b yte in memory - i.e. a
byte address. It comprises two parts, a word address and a byte selector. The byte
selector occupies the two least significant bits of the word; the word address the thirty
most significant bits. An address is treated as a signed value, the range of which
starts at the most negative integer and continues, through zero, to the most positive
integer. This enables the standard comparison functions to be used on pointer
(address) values in the same way that they are used on numerical values.
Certain values can never be used as pointers because they represent reserved
addresses at the bottom of memory space. They are reserved for use by the
processor and initialization. In this text, names are used to represent these and other
values (e.g. NotProcess.p, Disabling.p). A full list of names and values of constants
used in this book is given in section 1.9.
2.2
Ordering of information
The ST20 is ‘little-endian’ — i.e. less significant data is always held in lower
addresses. This applies to bits in bytes, bytes in words and words in memory. Hence,
in a word of data representing an integer, one byte is more significant than another if
its byte selector is the larger of the two. Figure 2.1 shows the ordering of bytes in
words and memory for the ST20. Note that this ordering is compatible with Intel
processors, but not Motorola or SPARC.
Memory
(bytes)
X+7
X+6
X+5
X+4
X+3
X+2
X+1
X+0
words (wordlength is 32 bits)
MSB
X+7
31
X+6
24 23
MSB
X+3
31
X+5
16 15
X+2
24 23
LSB
X+4
87
LSB
X+0
X+1
16 15
0
87
0
X is a word-aligned byte address
X+n is the byte n bytes past X
Figure 2.1 Bytes in memory and words
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Most instructions that involve fetching data from or storing data into memory, use word
aligned addresses (i.e. bits 1 and 0 are set to 0) and load or store four contiguous
bytes. However, there are some instructions that can manipulate part of the bit pattern
in a word, and a few that use double words.
A data item that is represented in two contiguous bytes, is referred to as a 16-bit
object. This can be stored, either in the least significant 16-bits of a word location or in
the most significant 16 bits, hence addresses of such locations are 16-bit aligned (i.e.
bit 0 is set to 0).
A data item that is represented in two contiguous words is referred to as a 64-bit
object or a double word.
Similarly, a data item represented in a single byte is sometimes referred to as an 8-bit
object.
2.3
Signed integers and sign extension
A signed integer is stored in twos-complement format and may be represented by an
N-bit object. Most commonly a signed integer is represented by a single word (32-bit
object), but as explained, it may be stored, for example, in a 64-bit object, a 16-bit
object, or an 8-bit object. In each of these formats, all the bits within the object contain
useful information.
Consider the example shown in Figure 2.2, which shows how the value -10 is stored in
a 32-bit register, firstly as an 8-bit object and secondly as a 32-bit object. Obser ve that
bits 31 to 8 are meaningful for a 32-bit object but not for an 8-bit object. These bits are
set to 1 in the 32-bit object to preserve the negative sign of the integer being
represented.
these bit values not related to integer value
bit position
31
1 1 1 1 0 1 1 0
8 7
0
signed integer value (-10) stored as an 8-bit object (byte)
1 1
bit position
...
31
1 1 1 1 1 0 1 1 0
8 7
signed integer value (-10) stored as a 32-bit object (word)
Figure 2.2 Storing a signed integer in different length objects
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0
The length of the object that stores a signed integer can be increased (i.e. the object
size can be increased). This operation is known as ‘sign extension’. The extra bits that
are allocated for the larger object, are meaningful to the value of the signed integer.
They must therefore be set to the appropriate value. The value for all these extra bits
is in fact the same as the value of the most significant bit - i.e. the sign bit - of the
smaller object. The ST20 provides instructions that sign extend byte and half-word to
word, and 32 bits to 64 bits.
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3
Registers
3.1
Machine registers
This section introduces the ST20 processor registers that are visible to the
programmer. Firstly the set of registers known as state registers are presented and
discussed. These fully define the state of the executing process. Secondly the other
registers of interest to the programmer, are presented.
3.1.1
Process state registers
The state of a executing process at any instant is defined b y the contents of the
machine registers listed in Table 3.1. The ‘register’ column gives the abbreviated
name of the register. The ‘full name / description’ column provides the full textual
name which is usually used when referencing a register in this manual; and where
unclear, a brief description of the information contained in this register.
register
full name / description process modes
Status
status register
Wptr
workspace pointer - contains the address of the workspace of the currently executing process
Iptr
instruction pointer register - pointer to next instruction to be executed
Areg
integer stack register A
Breg
integer stack register B
Creg
integer stack register C
Table 3.1 Process state registers
In addition there is a small number of registers used to implement block moves.
Status register
The Status register contains status bits which describe the current state of the
process and any errors which may have occurred. The contents of the Status register
are shown in Table 3.2.
‘Shadow’ registers
When a high priority process interrupts a low priority process, the state of the currently
executing process needs to be saved. For this purpose, two sets of process state
registers are provided, one each for high and low priority. On interrupt, the processor
switches to using the high priority registers, leaving the low priority registers to
preserve the low priority state.
A high priority process may manipulate the low priority ‘shadow’ registers with the
instructions ldshadow and stshadow. In the definitions of these instructions, the
process state registers have a subscript (e.g. Areg[LowPriority]) indicating the priority.
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bit number
full name / description
0
breakpoint trap status bit
1
integer error trap status bit
2
integer overflow trap status bit
3
illegal opcode trap status bit
4
load trap trap status bit
5
store trap trap status bit
6
internal channel trap status bit
7
external channel trap status bit
8
timer trap status bit
9
timeslice trap status bit
10
run trap status bit
11
signal trap status bit
12
process interrupt trap status bit
13
queue empty trap status bit
14
reserved
15
causeerror status bit
17-16
Scheduler trap return priority status bits:
00 - high priority
01 - low priority
19-18
Trap group status bits:
00 - Breakpoint
01 - Error
10 - System
11 - Scheduler
20
timeslice enable bit
25-21
reserved
30-26
Interrupted operation status bits:
00000 - None
00001 - move
00010 - devmove
00011 - move2dall
00100 - move2dzero
00101 - move2dnonzero
00110 - in
00111 - out
01000 - tin
01001 - tin restart
01010 - taltwt
01011 - taltwt restart
01100 - dist
01101 - dist restart
01110 - enbc
01111 - disc
10000 - resetch
31
status valid
Table 3.2 Status register
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If the process state registers are referred to without subscripts then the current priority
is implied.
3.1.2
Other machine registers
There are several other registers which the programmer should know about, but which
are not part of the process state. These are presented in Table 3.3.
register
full name / description
ProcQueueFPtr[0]
high priority front pointer register - contains pointer to first process on the high
priority scheduling list
ProcQueueFPtr[1]
low priority front pointer register - contains pointer to first process on the low
priority scheduling list
ProcQueueBPtr[0]
high priority back pointer register - contains pointer to last process on the high
priority scheduling list
ProcQueueBPtr[1]
low priority back pointer register - contains pointer to last process on the low
priority scheduling list
ClockReg[0]
high priority clock register - contains current value of high priority clock
ClockReg[1]
low priority clock register - contains current value of low priority clock
TptrReg[0]
high priority timer list pointer register - contains pointer to the first process on
the high priority timer list
TptrReg[1]
low priority timer list pointer register - contains pointer to the first process on the
low priority timer list
TnextReg[0]
high priority alarm register - contains the time of the first process on the high
priority timer queue
TnextReg[1]
low priority alarm register - contains the time of the first process on the low
priority timer queue
Enables
trap and global interrupt enables register
Table 3.3 Other machine registers
Enables register
The Enables register contains:
•
TrapEnables bits (0..15) which can be used to control the taking of traps;
•
GlobalInterruptEnables bits (16..31) which are used to control timeslicing and
interruptibility. These are normally set to 1.
Bits of TrapEnables may be set using the trapenb instruction and cleared using
trapdis. Bits of GlobalInterruptEnables may be set using the instruction gintenb and
disabled using gintdis.
The contents of the Enables register are shown in Table 3.4.
ClockEnables
ClockEnables is a pair of flags which enab le the timers ClockReg to tick. Bit zero of
ClockEnables controls ClockReg[0] and bit 1 controls ClockReg[1]. In each case,
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bit number
full name / description
0
breakpoint trap enable bit
1
integer error trap enable bit
2
integer overflow trap enable bit
3
illegal opcode trap enable bit
4
load trap trap enable bit
5
store trap trap enable bit
6
internal channel trap enable bit
7
external channel trap enable bit
8
timer trap enable bit
9
timeslice trap enable bit
10
run trap enable bit
11
signal trap enable bit
12
process interrupt trap enable bit
13
queue empty trap enable bit
15-14
reserved
16
low priority process interrupt enable bit
17
low priority timeslice enable bit
18
low priority external event enable bit
19
low priority timer alarm enable bit
20
high priority process interrupt enable bit
21
high priority timeslice enable bit
22
high priority external event enable bit
23
high priority timer alarm enable bit
31-24
reserved
Table 3.4 Enables register
the timer will tick if the ClockEnables bit is set to1. ClockEnables can be set using the
clockenb instruction and cleared using clockdis.
Error fla gs
The other machine flags referred to in the instruction definitions are listed in Table 3.4.
fla g name
ErrorFlag
HaltOnErrorFlag
description
Untrapped arithmetic error flags
Halt the processor if the ErrorFlag is set
Table 3.5 Error flags
ErrorFlag is a pair of flags , one for each priority, set by the processor if an integer error
or integer overflow error occurs and the corresponding trap is not enabled. The
processor will immediately halt if the HaltOnError flag is also set, or will contin ue
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otherwise. The ErrorFlags may also be set by the seterr instruction or tested and
cleared by the testerr instruction. The stoperr instruction stops the current process if
the ErrorFlag is set. The low priority ErrorFlag is copied to the high priority when the
processor switches from low to high priority. The HaltOnError flag ma y be set by the
sethalterr instruction, cleared by clrhalterr and tested by testhalterr.
3.2
The process descriptor and its associated register fields
In order to identify a process completely it is necessary to know: its workspace
address (in which the byte selector is always 0), and its priority (high or low). This
information is contained in the process descriptor. The workspace address of the
currently executing process is held in the workspace pointer register (Wptr) and the
priority is held in the flag Priority.
Wptr points to the current process workspace, which is always word-aligned. Priority
is the priority of the currently executing process where the value 1 indicates low
priority and 0 indicates high priority.
The process descriptor is formed from a pointer to the process workspace or-ed with
the priority flag at bit 0. Bit 1 is always set to 0.
Wdesc is defined so that the following invariants are obeyed:
Wptr = Wdesc ∧ WordSelectMask
Priority = Wdesc ∧ 1
Workspace address
31
2
Figure 3.1 Constituents of a process descriptor
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0
Priority
1
0
4
Instruction representation
The instruction encoding is designed so that the most commonly executed instructions
occupy the least number of bytes. This chapter describes the encoding mechanism
and explains how it achieves this.
A sequence of single byte instruction components is used to encode an instruction.
The ST20 interprets this sequence at the instruction fetch stage of execution. Most
users (working at the level of microprocessor assembly language or high-level
languages) need not be aware of the existence of instruction components and do not
need to think about the encoding. The first section (4.1) has been included to provide
a background. The following section (4.2) need only concern the reader that wants to
implement a code generator.
4.1
Instruction encoding
4.1.1
An instruction component
Each instruction component is one byte long, and is divided into two 4-bit parts. The
four most significant bits of the b yte are a function code, and the four least significant
bits are used to build an instruction data value as shown in Figure 4.1.
function code
7
4
data
3
0
Figure 4.1 Instruction format
The representation provides for sixteen instruction components (one for each
function), each with a data field ranging from 0 to 15.
There are three categories of instruction component. Firstly there are those that
specify the instruction directly in the function field. These are used to implement
primary instructions. Secondly there are the instruction components that are used to
extend the instruction data value - this process of extension is referred to as prefixing.
Thirdly there is the instruction component operate (opr) which specifies the instr uction
indirectly using the instruction data value. opr is used to implement secondary
instructions.
4.1.2
The instruction data value and prefixing
The data field of an instr uction component is used to create an instruction data value’
Primary instructions interpret the instruction data value as the operand of the
instruction. Secondary instructions interpret it as the operation code for the instruction
itself.
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The instruction data value is a signed integer that is represented as a 32-bit word. For
each new instruction sequence, the initial value of this integer is zero. Since there are
only 4 bits in the data field of a single instruction component, it is only possible for
most instruction components to initially assign an instruction data value in the range 0
to 15. However two instruction components are used to extend the range of the
instruction data value. Hence one or more prefixing components may be needed to
create the correct instruction data value. These are shown in Table 4.1 and explained
below.
mnemonic
name
pfix n
prefix
nfix n
negative prefix
Table 4.1 Prefixing instr uction components
All instruction components initially load the four data bits into the least significant four
bits of the instruction data value.
pfix loads its four data bits into the instruction data value, and then shifts this value up
four places. nfix is similar, except that it complements the instruction data value†
before shifting it up. Consequently, a sequence of one or more prefixes can be
included to extend the value. Instruction data values in the range -256 to 255 can be
represented using one prefix instr uction.
When the processor encounters an instruction component other than pfix or nfix , it
loads the data field into the instr uction data value. The instruction encoding is now
complete and the instruction can be executed. When the processor is ready to fetch
the next instruction component, it starts to create a new instruction data value.
4.1.3
Primary Instructions
Research has shown that computers spend most of the time executing instructions
such as: instructions to load and store from a small number of ‘local’ variables,
instructions to add and compare with small constants, and instructions to jump to or
call other parts of the program. For efficiency therefore, these are encoded directly as
primary instructions using the function field of an instr uction component.
Thirteen of the instruction components are used to encode the most important
operations performed by any computer executing a high level language. These are
used (in conjunction with zero or more prefixes) to implement the primary instructions.
Primary instructions interpret the instruction data value as an operand for the
instruction. The mnemonic for a primary instruction will therefore normally include a
this operand - n - when referenced.
The mnemonics and names for the primary instructions are listed in Table 4.2.
mnemonic
name
adc n
add constant
Table 4.2 Primary instructions
† Note that it inverts all 32 bits of the instruction data value.
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mnemonic
name
ajw n
adjust workspace
call n
call
cj n
conditional jump
eqc n
equals constant
jn
jump
ldc n
load constant
ldl n
load local
ldlp n
load local pointer
ldnl n
load non-local
ldnlp n
load non-local pointer
stl n
store local
stnl n
store non-local
Table 4.2 Primary instructions
4.1.4
Secondary instructions
The ST20 encodes all other instructions (secondary instructions) indirectly using the
instruction data value.
mnemonic
name
opr
operate
Table 4.3 Operate instruction
The instruction component opr causes the instruction data value to be interpreted as
the operation code of the instruction to be executed. This selects an operation to be
performed on the values held in the integer stack. This allows a further 16 operations
to be encoded in a single byte instruction. However the prefix instr uctions can be used
to extend the instruction data value, allowing any number of operations to be
performed.
Secondary instructions do not have an operand specified b y the encoding, because
the instruction data value has been used to specify the operation.
To ensure that programs are represented as compactly as possible, the operations are
encoded in such a way that the most frequent secondary instructions are represented
without using prefix instr uctions.
4.1.5
Summary of encoding
The encoding mechanism has important consequences.
•
Firstly, it simplifies language compilation, b y providing a completely uniform
way of allowing a primary instruction to take an operand of any size up to the
processor word-length.
•
Secondly, it allows these operands to be represented in a form independent of
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the word-length of the processor.
•
Thirdly, it enables any number of secondary instructions to be implemented.
The following provides some simple examples of encoding:
•
The instruction ldc 17 is encoded with the sequence:
pfix 1; ldc 1
•
The instruction add is encoded by:
opr 5
•
The instruction and is encoded by:
opr 70
which is in turn encoded with the sequence:
pfix 4; opr 6
To aid clarity and brevity, prefix sequences and the use of opr are not explicitly shown
in this guide. Each instruction is represented by a mnemonic, and for primary
instructions an item of data, which stands for the appropriate instruction component
sequence. Hence in the above examples, these are just shown as: ldc 17, add, and
and. (Also, where appropriate, an expression may be placed in a code sequence to
represent the code needed to evaluate that expression.
4.2
Generating prefix sequences
Prefixing is intended to be performed by a compiler or assembler. Prefixing b y hand is
not advised.
Normally a value can be loaded into the instruction data value by a variety of different
prefix sequences . It is important to use the shortest possible sequence as this
enhances both code compaction and execution speed. The best method of optimizing
object code so as to minimize the number of prefix instructions needed is shown
below.
4.2.1
Prefixing a constant
The algorithm to generate a constant instruction data value e for a function op is
described by the following recursive function.
prefix( op , e ) = IF
e < 16 AND e 0
op( e )
e 16
prefix( pfix, e >> 4 ); op( e ∧ # F )
e < 0
prefix( nfix, (~e) >> 4 ); op( e ∧ # F )
where ( op, e ) is the instruction component with function code op and data field
e, ~ is a bitwise NOT, and >> is a logical right shift.
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4.2.2
Evaluating minimal symbol offsets
Several primary instructions have an operand that is an offset between the current
value of the instruction pointer and some other part of the code. Generating the
optimal prefix sequence to create the instruction data value for one of these
instructions is more complicated. This is because two, or more, instructions with offset
operands can interlock so that the minimal prefix sequences for each instruction is
dependent on the prefixing sequences used for the others.
For example consider the interlocking jumps below which can be prefixed in two
distinct ways. The instructions j and cj are respectively jump and conditional jump.
These are explained in more detail later. The sequence:
cj +16; j -257
can be coded as
pfix 1; cj 0; pfix 1; nfix 0; j 15
but this can be optimized to be
cj 15; nfix 15; j 1
which is the encoding for the sequence
cj +15; j -255
This is because when the two offsets are reduced, their prefixing sequences take 1
byte less so that the two interlocking jumps will still transfer control to the same
instructions as before. This compaction of non-optimal prefix sequences is difficult to
perform and a better method is to slowly build up the prefix sequences so that the
optimal solution is achieved. The following algorithm performs this.
1
Associate with each jump instruction or offset load an ‘estimate’ of the number
of bytes required to code it and initially set them all to 0.
2
Evaluate all jump and load offsets under the current assumptions of the size of
prefix sequences to the jumps and offset loads
3
For each jump or load offset set the number of bytes needed to the number in
the shortest sequence that will build up the current offset.†
4
If any change was made to the number of bytes required then go back to 2 otherwise the code has reached a stable state.
The stable state that is achieved will be the optimal state.
Steps 2 and 3 can be combined so that the number of bytes required by each jump is
updated as the offset is calculated. This does mean that if an estimate is increased
then some previously calculated offsets may have been invalidated, but step 4 forces
another loop to be performed when those offsets can be corrected.
By initially setting the estimated size of offsets to zero, all jumps whose destination is
the next instruction are optimized out.
† Where the code being analyzed has alignment directives, then it is possible that this algorithm will not reach a stable state. One
solution to this, is to allow the algorithm to increase the instruction size but not allow it to reduce the size. This is achieved by
modifying stage 3 to choose the larger of: the currently calculated length, and the previously calculated length. This approach
does not always lead to minimal sized code, but it guarantees termination of the algorithm.
29/212
Knowledge of the structure of code generated by the compiler allows this process to
be performed on individual blocks of code rather than on the whole program. For
example it is often possible to optimize the prefixing in the code for the subcomponents of a programming language construct before the code for the construct is
optimized. When optimizing the construct it is known that the sub-components are
already optimal so they can be considered as an unshrinkable block of code.
This algorithm may not be efficient for long sections of code whose underlying
structure is not known. If no knowledge of the structure is available (e.g. in an
assembler), all the code must be processed at once. In this case a code shrinking
algorithm where in step one the initial number of bytes is set to twice the number of
bytes per word is used. The prefix sequences then shr ink on each iteration of the loop.
1 or 2 iterations produce fairly good code although this method will not always produce
optimal code as it will not correctly prefix the pathological example given above.
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5
Instruction Set Reference
31/212
adc n
adc n
add constant
Code: Function 8
Description: Add a constant to Areg, with checking for overflow.
Definition:
Areg′ ← Areg + checked n
Error signals:
IntegerOverflow can be signalled by + checked
Comments:
Primary instruction.
See also: add ldnlp sum
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add
add
add
Code: F5
Description: Add Areg and Breg, with checking for overflow.
Definition:
Areg′ ← Breg + checked Areg
Breg′
Creg′
← Creg
← undefined
Error signals:
IntegerOverflow can be signalled by +checked
Comments:
Secondary instruction.
See also: adc sum
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ajw n
ajw n
adjust workspace
Code: Function B
Description: Move the workspace pointer by the number of words specified in the
operand, in order to allocate or de-allocate the workspace stack.
Definition:
Wptr′ ← Wptr @ n
Error signals: none
Comments:
Primary instruction.
See also: call gajw
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alt
alt
alt start
Code: 24 F3
Description: Start of a non-timer alternative sequence. The pw.State location of the
workspace is set to Enabling.p.
Definition:
word′[Wptr @ pw.State]
← Enabling.p
Enter alternative sequence
Error signals: none
Comments:
Secondary instruction.
See also: altend altwt disc diss dist enbc enbs enbt talt taltwt
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altend
altend
alt end
Code: 24 F5
Description: End of alternative sequence. Jump to start of selected process.
Definition:
Terminate alternative sequence
Iptr′
← next instruction + word [Wptr @ pw.Temp]
Error signals: none
Comments:
Secondary instruction.
Uses the pw.Temp slot in the process workspace.
See also: alt altwt disc diss dist enbc enbs enbt talt taltwt
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altwt
altwt
alt wait
Code: 24 F4
Description: Wait until one of the enabled guards of an alternative has become
ready, and initialize workspace for use during the disabling sequence.
Definition:
if (word[Wptr @ pw.State] ≠ Ready.p)
{
word′[Wptr @ pw.State]
← Waiting.p
Deschedule process and wait for one of the guards to become ready
}
word′[Wptr @ pw.Temp]
Areg′
Breg′
Creg′
← NoneSelected.o
← undefined
← undefined
← undefined
Error signals: none
Comments:
Secondary instruction.
Instruction is a descheduling point.
Uses the pw.Temp slot in the process workspace.
See also: alt altend disc diss dist enbc enbs enbt talt taltwt
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and
and
and
Code: 24 F6
Description: Bitwise and of Areg and Breg.
Definition:
Areg′ ← Breg ∧ Areg
Breg′
Creg′
← Creg
← undefined
Error signals: none
Comments:
Secondary instruction.
See also: not or xor
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bcnt
bcnt
byte count
Code: 23 F4
Description: Produce the length, in bytes, of a multiword data object. Converts the
value in Areg, representing a number of words, to the equivalent number of bytes.
Definition:
Areg′ ← Areg × BytesPerWord
Error signals: none
Comments:
Secondary instruction.
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bitcnt
bitcnt
count bits set in word
Code: 27 F6
Description: Count the number of bits set in Areg and add this to the value in Breg.
Definition:
Areg′ ← Breg + number of bits set to 1 in Areg
Breg′
Creg′
← Creg
← undefined
Error signals: none
Comments:
Secondary instruction.
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bitrevnbits
bitrevnbits
reverse bottom n bits in word
Code: 27 F8
Description: Reverse the order of the bottom Areg bits of Breg.
Definition:
if (0 ≤ Areg) and (Areg ≤ BitsPerWord)
{
Areg′0..Areg-1
← reversed Breg0..Areg-1
Areg′Areg..BitsPerWord-1 ← 0
}
else
Undefined effect
Breg′
Creg′
← Creg
← undefined
Error signals: none
Comments:
Secondary instruction.
The effect of the instruction is undefined if the n umber of bits specified is more
than the word length.
See also: bitrevword
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bitrevword
bitrevword
reverse bits in word
Code: 27 F7
Description: Reverse the order of all the bits in Areg.
Definition:
Areg′ ← reversed Areg
Error signals: none
Comments:
Secondary instruction.
See also: bitcnt bitrevnbits
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bsub
bsub
byte subscript
Code: F2
Description: Generate the address of the element which is indexed by Breg, in the
byte array pointed to by Areg.
Definition:
Areg′ ← Areg + Breg
Breg′
Creg′
← Creg
← undefined
Error signals: none
Comments:
Secondary instruction.
See also: ssub sum wsub wsubdb
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call n
call n
call
Code: Function 9
Description: Adjust workspace pointer, save evaluation stack, and call subroutine at
specified b yte offset.
Definition:
Wptr′ ← Wptr @ -4
word′[Wptr′ @
word′[Wptr′ @
word′[Wptr′ @
word′[Wptr′ @
0]
1]
2]
3]
←
←
←
←
Iptr
Areg
Breg
Creg
Iptr′
← next instruction + n
Areg′
Breg′
Creg′
← Iptr
← undefined
← undefined
Error signals: none
Comments:
Primary instruction.
See also: ajw gcall ret
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causeerror
causeerror
cause error
Code: 62 FF
Description: Take a trap with the trap type set to the value in Areg. Only one bit in
Areg should be set; the position of the bit indicates the trap to be signalled. When the
trap is taken the causeerror bit in the status register is set to indicate a user generated
trap.
In the case of a scheduler trap being set then the bottom bit of Breg is used to
determine the priority of the scheduler trap. In addition when the scheduler trap is
trapping a process scheduling operation (e.g. the run trap) the Breg is interpreted as
the process descriptor to be scheduled.
Definition:
if (Areg=2i) and (trap type i is enabled)
{
set causeerror bit in Status
cause trap type i
}
else
Undefined effect
Error signals: The causeerror bit is set and the indicated trap signalled if enabled.
Comments:
Secondary instruction.
Sets traps independently of trap enables state.
See also: tret sttraph ldtrap
45/212
cb
cb
check byte
Code: 2B FA
Description: Check that the value in Areg can be represented as an 8-bit signed
integer.
Definition:
if (Areg < -27) or (Areg ≥ 27)
IntegerError
Error signals:
IntegerError signalled if Areg is not in range.
Comments:
Secondary instruction.
See also: cbu cir ciru cs csu
46/212
cbu
cbu
check byte unsigned
Code: 2B FB
Description: Check that the value in Areg can be represented as an 8-bit unsigned
integer.
Definition:
if (Areg < 0) or (Areg ≥ 28)
IntegerError
Error signals:
IntegerError signalled if Areg is not in range.
Comments:
Secondary instruction.
See also: cb cir ciru cs csu
47/212
ccnt1
ccnt1
check count from 1
Code: 24 FD
Description: Check that Breg is in the range 1..Areg inclusive, interpreting Areg and
Breg as unsigned numbers.
Definition:
if (Breg = 0) or (Bregunsigned > Aregunsigned)
IntegerError
Areg′
Breg′
Creg′
← Breg
← Creg
← undefined
Error signals:
IntegerError signalled if Areg is not in range.
Comments:
Secondary instruction.
See also: csub0
48/212
cflerr
cflerr
check floating point error
Code: 27 F3
Description: Checks if Areg represents an Inf or NaN.
Definition:
if (Areg ∧ #7F800000 = #7F800000)
IntegerError
Error signals:
IntegerError signalled if Areg represents an Inf or NaN.
Comments:
Secondary instruction.
See also: unpacksn roundsn postnormsn ldinf
49/212
cir
cir
check in range
Code: 2C F7
Description: Check that Creg is in the range Areg..Breg inclusive.
Definition:
if (Creg < Areg) or (Creg > Breg)
IntegerError
Areg′
Breg′
Creg′
← Creg
← undefined
← undefined
Error signals:
IntegerError signalled if Creg is not in range.
Comments:
Secondary instruction.
See also: ciru
50/212
ciru
ciru
check in range unsigned
Code: 2C FC
Description: Check that Creg is the range Areg..Breg inclusive, treating all as
unsigned values.
Definition:
if (Cregunsigned < Aregunsigned) or (Cregunsigned > Bregunsigned)
IntegerError
Areg′
Breg′
Creg′
← Creg
← undefined
← undefined
Error signals: IntegerError signalled if Creg is not in range.
Comments:
Secondary instruction.
See also: cir
51/212
cj n
cj n
conditional jump
Code: Function A
Description: Jump if Areg is 0 (i.e. jump if false). The destination of the jump is
expressed as a byte offset from the instruction following.
Definition:
if (Areg = 0)
Iptr′
←
else
{
Iptr′
←
Areg′ ←
Breg′ ←
Creg′ ←
}
next instruction + n
next instruction
Breg
Creg
undefined
Error signals: none
Comments:
Primary instruction.
See also: j lend
52/212
clockdis
clockdis
clock disable
Code: 64 FE
Description: Stops the clocks specified in bits 0 and 1 of Areg where bit 0 indicates
the high priority clock and bit 1 the low priority clock. The original values of these two
clock enable bits are returned in Areg.
Definition:
Areg′ 1..0
← ClockEnables
← 0
Areg′31..2
ClockEnables′ ← ClockEnables ∧ ∼Areg
Error signals: none
Comments:
Secondary instruction.
See also: clockenb
53/212
clockenb
clockenb
clock enable
Code: 64 FF
Description: Starts or restarts the clocks specified in bits 0 and 1 of Areg, where bit
0 indicates the high priority clock and bit 1 indicates the low priority clock. The original
values of these two clock enable bits are returned in Areg.
Definition:
Areg′1..0
← ClockEnables
← 0
Areg′31..2
ClockEnables′ ← ClockEnables ∨ Areg
Error signals: none
Comments:
Secondary instruction.
See also: clockdis
54/212
clrhalterr
clrhalterr
clear halt-on-error
Code: 25 F7
Description: Clear the HaltOnError flag.
Definition:
HaltOnErrorFlag′
← clear
Error signals: none
Comments:
Secondary instruction.
See also: sethalterr testhalterr
55/212
crcbyte
crcbyte
calculate CRC on byte
Code: 27 F5
Description: Generate a CRC (cyclic redundancy check) checksum from the most
significant b yte of Areg. Breg contains the previously accumulated checksum and
Creg the polynomial divisor (or ‘generator’). The new CRC checksum, the polynomial
remainder, is calculated by repeatedly (8 times) shifting the accumulated checksum
left, shifting in successive bits from the Areg and if the bit shifted out of the checksum
was a 1, then the generator is exclusive-ored into the checksum.
Definition:
Areg′ ← temp(8)
Breg′ ← Creg
Creg′ ← undefined
where
temp(0) = Breg
for i = 1 .. 8
temp(i) = (temp(i -1) << 1) + AregBitsPerWord-i)
⊗ (Creg × temp(i −1)BitsPerWord-1)
Error signals: none
Comments:
Secondary instruction.
See also: crcword
56/212
crcword
crcword
calculate CRC on word
Code: 27 F4
Description: Generate a CRC (cyclic redundancy check) checksum from Areg. Breg
contains the previously accumulated checksum and Creg the polynomial divisor (or
‘generator’). The new CRC checksum, the polynomial remainder, is calculated by
repeatedly (BitsPerWord times) shifting the accumulated checksum left, shifting in
successive bits from the Areg and if the bit shifted out of the checksum was a 1, then
the generator is exclusive-ored into the checksum.
Definition:
Areg′ ← temp(BitsPerWord)
Breg′ ← Creg
Creg′ ← undefined
where
temp(0) = Breg
for i = 1 .. 32
temp(i) = (temp(i -1) << 1) + AregBitsPerWord-i)
⊗ (Creg × temp(i −1)BitsPerWord-1)
Error signals: none
Comments:
Secondary instruction.
See also: crcbyte
57/212
cs
cs
check sixteen
Code: 2F FA
Description: Check that the value in Areg can be represented as a 16-bit signed
integer.
Definition:
if (Areg < -215) or (Areg ≥ 215)
IntegerError
Error signals:
IntegerError signalled if Areg is not in range.
Comments:
Secondary instruction.
See also: cb cbu cir ciru csngl csu cword
58/212
csngl
csngl
check single
Code: 24 FC
Description: Check that the two word signed value in Areg and Breg (most
significant w ord in Breg) can be represented as a single length signed integer.
Definition:
if ((Areg ≥ 0) and (Breg ≠ 0)) or ((Areg < 0) and (Breg ≠ −1))
IntegerError
Error signals:
IntegerError signalled if Areg is not in range.
Comments:
Secondary instruction.
See also: cb cbu cir ciru cs csu cword
59/212
csu
csu
check sixteen unsigned
Code: 2F FB
Description: Check that the value in Areg can be represented as a 16-bit unsigned
integer.
Definition:
if (Areg < 0) or (Areg ≥ 216)
IntegerError
Error signals:
IntegerError signalled if Areg is not in range.
Comments:
Secondary instruction.
See also: cb cbu cir ciru cs csngl cword
60/212
csub0
csub0
check subscript from 0
Code: 21 F3
Description: Check that Breg is in the range 0..(Areg-1), interpreting Areg and Breg
as unsigned numbers.
Definition:
if (Bregunsigned ≥ Aregunsigned)
Integer Error
Areg′
Breg′
Creg′
← Breg
← Creg
← undefined
Error signals:
IntegerError signalled if Breg is not in range.
Comments:
Secondary instruction.
See also: ccnt1
61/212
cword
cword
check word
Code: 25 F6
Description: Check that the value in Breg can be represented as an N-bit signed
integer. Areg contains 2(N-1) to indicate the value of N (i.e. bit N-1 of Areg is set to 1
and all other bits are set to zero).
Definition:
if (Breg < −Areg) or (Breg ≥ Areg)
IntegerError
Areg′
Breg′
Creg′
← Breg
← Creg
← undefined
Error signals:
IntegerError signalled if Breg is not in range.
Comments:
The result of the instruction is undefined if Areg is not an integral power of 2.
Undefined if Areg has more than one bit set.
Secondary instruction.
See also: cb cs csngl xword
62/212
devlb
devlb
device load byte
Code: 2F F0
Description: Perform a device read from memory, a memory-mapped device or a
peripheral. The byte addressed by Areg is read into Areg as an unsigned value. The
memory access performed by this instruction is guaranteed to be correctly sequenced
with respect to other device-access instructions. Also the instruction is guaranteed to
be executed after all normal memory load instructions that appear before it in the code
sequence, and before all normal memory loads that appear later.
Definition:
if (PeripheralStart ≤ Areg ≤ PeripheralEnd)
Areg′0..7
← PeripheralByte[Areg]
else
Areg′0..7
← byte[Areg]
Areg′8..31
← 0
Error signals: none
Comments:
Secondary instruction.
See also: devls devlw devsb lb
63/212
devls
devls
device load sixteen
Code: 2F F2
Description: Perform a device read from memory, a memory-mapped device or a
peripheral. The 16-bit object addressed by Areg is read into Areg as an unsigned
value. The memory access performed by this instruction is guaranteed to be correctly
sequenced with respect to other device-access instructions. Also the instruction is
guaranteed to be executed after all normal memory load instructions that appear
before it in the code sequence, and before all normal memory loads that appear after
it.
Definition:
if (PeripheralStart ≤ Areg ≤ PeripheralEnd)
Areg′0..15 ← PeripheralSixteen[Areg]
else
Areg′0..15 ← sixteen[Areg]
Areg′16..31
← 0
Error signals: none
Comments:
Secondary instruction.
See also: devlb devlw devsb ls
64/212
devlw
devlw
device load word
Code: 2F F4
Description: Perform a device read from memory, a memory-mapped device or a
peripheral. The word addressed by Areg is read into Areg. The memory access
performed by this instruction is guaranteed to be correctly sequenced with respect to
other device-access instructions. Also the instruction is guaranteed to be executed
after all normal memory load instructions that appear before it in the code sequence,
and before all normal memory loads that appear after it.
Definition:
if (PeripheralStart ≤ Areg ≤ PeripheralEnd)
Areg′ ← PeripheralWord[Areg]
else
Areg′ ← word[Areg]
Error signals: none
Comments:
Secondary instruction.
See also: devlb devls devsw ldnl
65/212
devmove
devmove
device move
Code: 62 F4
Description: Perform a device copy between memory or memory-mapped devices.
Copies Areg bytes to address Breg from address Creg. Only the minimum number of
reads and writes required to copy the data will be performed. Each read will be to a
strictly higher (more positive) address than the one before and each write will be to a
strictly higher byte address than the one before. There is no guarantee of the relative
ordering of read and write cycles, except that a write cannot occur until the
corresponding read has been performed. The memory accesses performed by this
instruction are guaranteed to be correctly sequenced with respect to other deviceaccess instructions. Also the instruction is guaranteed to be executed after all normal
memory access instructions that appear before it in the code sequence, and before all
normal memory accesses that appear after it.
Definition:
if (source and destination overlap)
Undefined effect
else for i = 0 .. (Aregunsigned − 1)
byte′[Breg + i] ← byte[Creg + i]
Areg′
Breg′
Creg′
← undefined
← undefined
← undefined
Error signals: none
Comments:
Secondary instruction.
The effect of the instruction is undefined if the source and destination overlap.
Instruction is interruptible.
Devmove will not operate from or to peripheral addresses.
See also: move
66/212
devsb
devsb
device store byte
Code: 2F F1
Description: Perform a device write from memory, a memory-mapped device or a
peripheral. Store the least significant byte of Breg into the byte addressed by Areg.
The memory access performed by this instruction is guaranteed to be correctly
sequenced with respect to other device-access instructions. Also the instruction is
guaranteed to be executed after all normal memory store instructions that appear
before it in the code sequence, and before all normal memory stores that appear after
it.
Definition:
if (PeripheralStart ≤ Areg ≤ PeripheralEnd)
PeripheralByte′[Areg] ← Breg0..7
else
byte′[Areg] ← Breg0..7
Areg′
Breg′
Creg′
← Creg
← undefined
← undefined
Error signals: none
Comments:
Secondary instruction.
See also: devlb devss devsw sb
67/212
devss
devss
device store sixteen
Code: 2F F3
Description: Perform a device write from memory, a memory-mapped device or a
peripheral. Store bits 0..5 of Breg into the sixteen bits addressed by Areg. A memory
access performed by this instruction is guaranteed to be correctly sequenced with
respect to other device-access instructions. Also the instruction is guaranteed to be
executed after all normal memory store instructions that appear before it in the code
sequence, and before all normal memory stores that appear after it.
Definition:
if (PeripheralStart ≤ Areg ≤ PeripheralEnd)
PeripheralSixteen′[Areg]← Breg0..15
else
sixteen′[Areg] ← Breg0..15
Areg′
Breg′
Creg′
← Creg
← undefined
← undefined
Error signals: none
Comments:
Secondary instruction.
See also: devls devsb devsw ss
68/212
devsw
devsw
device store word
Code: 2F F5
Description: Perform a device write from memory, a memory-mapped device or a
peripheral. Store Breg into the word of memory addressed by Areg. The memory
access performed by this instruction is guaranteed to be correctly sequenced with
respect to other device-access instructions. Also the instruction is guaranteed to be
executed after all normal memory store instructions that appear before it in the code
sequence, and before all normal memory stores that appear after it.
Definition:
if (PeripheralStart ≤ Areg ≤ PeripheralEnd)
PeripheralWord′[Areg] ← Breg
else
word′[Areg] ← Breg
Areg′
Breg′
Creg′
← Creg
← undefined
← undefined
Error signals: none
Comments:
Secondary instruction.
See also: devlw devsb devss stnl
69/212
diff
diff
difference
Code: F4
Description: Subtract Areg from Breg, without checking for overflow.
Definition:
Areg′ ← Breg − Areg
Breg′
Creg′
← Creg
← undefined
Error signals: none
Comments:
Secondary instruction.
See also: sub
70/212
disc
disc
disable channel
Code: 22 FF
Description: Disable a channel guard in an alternative sequence. Areg is the offset
from the byte following the altend to the start of the guarded process, Breg is the
boolean guard and Creg is a pointer to the channel. If this is the first ready guard then
the value in Areg is stored in workspace and Areg is set to true, otherwise Areg is set
to false. Note that this instruction should be used as part of an alternative sequence
following an altwt or taltwt instruction.
Definition:
if (Breg = false)
– boolean guard is false
Areg′ ← false
else if (Creg is internal channel)
{
if (word[Creg] = NotProcess.p)
– guard already disabled
Areg′ ← false
else if (word[Creg] = Wdesc)
– this guard is not ready
{
word′[Creg]
← NotProcess.p
Areg′
← false
}
else if (word[Wptr @ pw.Temp] = NoneSelected.o)
{
– this is the first ready guard
word′[Wptr @ pw.Temp]
← Areg
Areg′
← true
}
else
– a previous guard selected
Areg′ ← false
}
else if (Creg is external channel)
{
Disable comms subsystem and receive status
if (channel not ready)
– channel not waiting
Areg′ ← false
else if (word[Wptr @ pw.Temp] = NoneSelected.o)
{
– this is the first ready guard
word′[Wptr @ pw.Temp]
← Areg
Areg′
← true
}
else
- a previous guard selected
Areg′ ← false
}
Breg′
Creg′
← undefined
← undefined
71/212
disc
Error signals: none
Comments:
Secondary instruction.
Uses the pw.Temp slot in the process workspace.
See also: alt altend altwt enbc talt taltwt
72/212
diss
diss
disable skip
Code: 23 F0
Description: Disable a ‘skip’ guard in an alternative sequence. Areg is the offset
from the byte following the altend to the start of the guarded process and Breg is the
boolean guard. If this is the first ready guard then the value in Areg is stored in
workspace and Areg is set to true, otherwise Areg is set to false. Note that this
instruction should be used as part of an alternative sequence following an altwt or
taltwt instruction.
Definition:
if (Breg = false)
– boolean guard is false
Areg′ ← false
else if (word[Wptr @ pw.Temp] = NoneSelected.o)
Areg′ ← false
– this is the first ready guard
else
– another guard was selected
{
word′[Wptr @ pw.Temp]
← Areg
Areg′
← true
}
Breg′
Creg′
← Creg
← undefined
Error signals: none
Comments:
Secondary instruction.
Uses the pw.Temp slot in the process workspace.
See also: alt altend altwt enbs talt taltwt
73/212
dist
dist
disable timer
Code: 22 FE
Description: Disable a timer guard in an alternative sequence. Areg is the offset
from the byte following the altend to the start of the guarded process, Breg is the
boolean guard and Creg is the time after which this guard will be ready. If this is the
first ready guard then the value in Areg is stored in pw.Temp, and Areg is set to true.
Note that this instruction should be used as part of an alternative sequence following a
taltwt instruction.
Definition:
if (Breg = false)
– boolean guard is false
Areg′ ← false
else if (word[Wptr @ pw.TLink] = TimeNotSet.p)
– no timer is ready
Areg′ ← false
else if (word[Wptr @ pw.TLink]= TimeSet.p)
– a timer is ready
{
if not (word[Wptr @ pw.Time] after Creg)
– but not this one
Areg′ ← false
else if (word[Wptr @ pw.Temp] = NoneSelected.o)
– this is the first ready guard
{
word′[Wptr @ pw.Temp]
← Areg
Areg′ ← true
}
else
– a previous guard selected
Areg′ ← false
}
else
Areg′ ← false
Remove this process from the timer list
Breg′
Creg′
← undefined
← undefined
Error signals: none
Comments:
Secondary instruction.
Instruction is interruptible.
Uses the pw.Temp slot in the process workspace.
See also: altend enbt talt taltwt
74/212
div
div
divide
Code: 22 FC
Description: Divide Breg by Areg, with checking for overflow. The result when not
exact is rounded towards zero.
Definition:
if (Areg = 0) or ((Breg = MostNeg) and (Areg = -1))
{
Areg′ ← undefined
IntegerOverflow
}
else
Areg′ ← Breg / Areg
Breg′
Creg′
← Creg
← undefined
Error signals:
IntegerOverflow can be signalled.
Comments:
Secondary instruction.
See also: rem
75/212
dup
dup
duplicate top of stack
Code: 25 FA
Description: Duplicate the top of the integer stack.
Definition:
Areg′ ← Areg
Breg′ ← Areg
Creg′ ← Breg
Error signals: none
Comments:
Secondary instruction.
See also: pop rev
76/212
enbc
enbc
enable channel
Code: 24 F8
Description: Enable a channel guard in an alternative sequence. Areg is the
boolean guard and Breg is a pointer to the channel. Note that this instruction should
only be used as part of an alternative sequence following an alt or talt instruction.
Definition:
if (Areg ≠ false)
{
if (Breg is internal channel)
{
if (word[Breg] = NotProcess.p)
– not ready
word′[Breg]
← Wdesc
else if (word[Breg] ≠ Wdesc)
– not previously enabled
word′[Wptr @ pw.State]
← Ready.p
}
else if (Breg is external channel)
{
Request Comms Subsystem to enable external channel
and receive current status of channel
if (channel ready)
word′[Wptr @ pw.State]
← Ready.p
}
}
Breg′
Creg′
← Creg
← undefined
Error signals: none
Comments:
Secondary instruction.
See also: alt altend altwt disc talt taltwt
77/212
enbs
enbs
enable skip
Code: 24 F9
Description: Enable a ‘skip’ guard in an alternative sequence. Areg is the boolean
guard. Note that this instruction should only be used as part of an alternative
sequence following an alt or talt instruction.
Definition:
if (Areg ≠ false)
word′[Wptr @ pw.State]
← Ready.p
Error signals: none
Comments:
Secondary instruction.
See also: alt altend altwt diss talt taltwt
78/212
enbt
enbt
enable timer
Code: 24 F7
Description: Enable a timer guard in an alternative sequence. Areg is the boolean
guard and Breg is the time after which the guard may be selected. Note that this
instruction should only be used as part of an alternative sequence following a talt
instruction; in this case the location pw.State will have been initialized to Enabling.p
and the pw.Tlink slot initialized to TimeNotSet.p.
Definition:
if (Areg ≠ false)
{
if (word[Wptr @ pw.TLink] = TimeNotSet.p)
– this is the first enbt
{
word′[Wptr @ pw.TLink]
← TimeSet.p
word′[Wptr @ pw.Time]
← Breg
}
else if (word[Wptr @ pw.TLink] = TimeSet.p)
– this is not the first enbt
{
if (word[Wptr @ pw.Time] after Breg)
– this enbt has earlier time
word′[Wptr @ pw.Time] ← Breg
}
}
Breg′
Creg′
← Creg
← undefined
Error signals: none
Comments:
Secondary instruction.
See also: altend dist talt taltwt
79/212
endp
endp
end process
Code: F3
Description: Synchronize the termination of a parallel construct. When all branches
have executed an endp instruction a ‘successor’ process then executes. Areg points
to the workspace of this successor process. This workspace contains a data structure
which holds the instruction pointer of the successor process and the number of
processes still active.
Definition:
if (word[Areg @ pp.Count] = 1)
{
Iptr′
← word[Areg @ pp.IptrSucc]
Wptr′ ← Areg
}
else
word′[Areg @ pp.Count]
← word[Areg @ pp.Count]−1
start next process
Areg′
Breg′
Creg′
← undefined
← undefined
← undefined
Error signals: none
Comments:
Secondary instruction.
Instruction is a descheduling point.
See also: startp stopp
80/212
eqc n
eqc n
equals constant
Code: Function C
Description: Compare Areg to a constant.
Definition:
if (Areg = n)
Areg′ ← true
else
Areg′ ← false
Error signals: none
Comments:
Primary instruction.
81/212
fmul
fmul
fractional multiply
Code: 27 F2
Description: Multiply Areg by Breg treating the values as fractions, rounding the
result. The values in Areg and Breg are interpreted as fractions in the range greater
than or equal to -1 and less than 1 - i.e. the integer values divided by 2BitsPerWord-1.
The result is rounded. The rounding mode used is analogous to IEEE round nearest;
that is the result produced is the fraction which is nearest to the exact product, and, in
the event of the product being equidistant between two factions, the fraction with least
significant bit 0 is produced.
Definition:
if (Areg = MostNeg) and (Breg = MostNeg)
– MostNeg interpreted as -1
{
Areg′ ← undefined
IntegerOverflow
}
else
Areg′ ← (Breg × Areg) /roundnearest 2BitsPerWord-1
Breg′
Creg
← Creg
← undefined
Error signals:
IntegerOverflow can occur.
Comments:
Secondary instruction.
82/212
fptesterr
fptesterr
test for FPU error
Code: 29 FC
Description: Test for an error in the FPU, if present. This instruction always returns
true on a processor without an FPU.
Definition:
Areg′ ← true
Breg′ ← Areg
Creg′ ← Breg
Error signals: none
Comments:
Secondary instruction.
83/212
gajw
gajw
general adjust workspace
Code: 23 FC
Description: Set the workspace pointer to the address in Areg, saving the previous
value in Areg.
Definition:
Wptr′ ← Areg
Areg′ ← Wptr
Error signals: none
Comments:
Secondary instruction.
Areg should be word aligned.
See also: ajw call gcall
84/212
gcall
gcall
general call
Code: F6
Description: Jump to the address in Areg, saving the previous address in Areg.
Definition:
Iptr′
← Areg
Areg′ ← Iptr
Error signals: none
Comments:
Secondary instruction.
See also: ajw call gajw ret
85/212
gintdis
gintdis
global interrupt disable
Code: 2C FD
Description: Disable the global interrupt events specified in the bit mask in Areg.
This allows parts of the built-in scheduler, such as response to external events,
timeslicing etc., to be disabled by software. The original value of the global interrupt
enable register is returned in Areg.
Definition:
GlobalInterruptEnables′ ← GlobalInterruptEnables ∧ ∼Areg7..0
Areg′7..0
← GlobalInterruptEnables
Areg′31..8 ← 0
Error signals: none
Comments:
Secondary instruction.
See also: gintenb
86/212
gintenb
gintenb
global interrupt enable
Code: 2C FE
Description: Enable the global interrupt events specified in the bit mask in Areg.
Definition:
GlobalInterruptEnables′ ← GlobalInterruptEnables ∨ Areg7..0
Areg′7..0
← GlobalInterruptEnables
Areg′8..31 ← 0
Error signals: none
Comments:
Secondary instruction.
See also: gintdis
87/212
gt
gt
greater than
Code: F9
Description: Compare the top two elements of the stack, returning true if Breg is
greater than Areg.
Definition:
if (Breg > Areg)
Areg′ ← true
else
Areg′ ← false
Breg′
Creg′
← Creg
← undefined
Error signals: none
Comments:
Secondary instruction.
88/212
gtu
gtu
greater than unsigned
Code: 25 FF
Description: Compare the top two elements of the stack, treating both as unsigned
integers, returning true if Breg is greater than Areg.
Definition:
if (Bregunsigned > Aregunsignded)
Areg′ ← true
else
Areg′ ← false
Breg′
Creg′
← Creg
← undefined
Error signals: none
Comments:
Secondary instruction.
89/212
in
in
input message
Code: F7
Description: Input a message. The corresponding output is performed by an out,
outword or outbyte instruction, and must specify a message of the same length. Areg
is the unsigned length in bytes, Breg is a pointer to the channel and Creg is a pointer
to where the message is to be stored. The process executing in will be descheduled if
the channel is external or is not ready, and is rescheduled when the communication is
complete.
Definition:
Synchronize, and input Aregunsigned bytes from channel Breg to address Creg
Areg′
Breg′
Creg′
← undefined
← undefined
← undefined
Error signals: Can cause InternalChannel or ExternalChannel trap to be signalled (if
enabled) when the process is rescheduled after synchronization.
Comments:
Secondary instruction.
Instruction is a descheduling point.
Instruction is interruptible.
See also: out
90/212
insertqueue
insertqueue
insert at front of scheduler queue
Code: 60 F2
Description: Insert a list of processes at the front of the scheduling list of priority
indicated by Areg, where 0 indicates high priority and 1 indicates low priority. Breg
and Creg are the front and back, respectively, of the list to be inserted.
Definition:
if (Breg ≠ NotProcess.p)
{
ProcQueueFPtr′[Areg]←Breg
if (ProcQueueFPtr[Areg] = NotProcess.p)
ProcQueueBPtr′[Areg]←Creg
else
word′[Creg @ pw.Link] ← ProcQueueFPtr[Areg]
}
Areg′
Breg′
Creg′
← undefined
← undefined
← undefined
Error signals: none
Comments:
Secondary instruction.
See also: swapqueue
91/212
intdis
intdis
(localised) interrupt disable
Code: 2C F4
Description: Disable interruption by high priority processes until either an intenb
instruction is executed or the process deschedules. Timeslicing does not occur while
interrupts are disabled. This instruction is only meaningful for low priority processes.
Definition:
Disable high priority interrupts
Error signals: none
Comments:
Secondary instruction.
See also: intenb settimeslice
92/212
intenb
intenb
(localised) interrupt enable
Code: 2C F5
Description: Enable interruption by high priority processes. This instruction is only
meaningful for low priority processes.
Definition:
Enable high priority interrupts
Error signals: none
Comments:
Secondary instruction.
See also: intdis settimeslice
93/212
iret
iret
interrupt return
Code: 61 FF
Description: Return from external interrupt. Signal iret to interrupt handler and return
to the context of the interrupted process and resume execution. The interrupted high
priority state is recovered from the workspace – if this does not contain a running
process the processor switches to the interrupted low priority state held in the shadow
registers.
Definition:
Status′
← word[Wptr]
if (Status has valid bit set)
{
Wptr′ ← word[Wptr + 1]
Iptr′
← word[Wptr + 2]
Areg′ ← word[Wptr + 3]
Breg′ ← word[Wptr + 4]
Creg′ ← word[Wptr + 5]
}
else
Return to interrupted low priority state
Error signals: none
Comments:
Secondary instruction.
94/212
jn
jn
jump
Code: Function 0
Description: Unconditional relative jump. The destination of the jump is expressed as
a byte offset from the first byte after the current instruction. j 0 causes a breakpoint.
Definition:
if (n = 0)
Take a breakpoint trap
else
Iptr′
← next instruction + n
Areg′
Breg′
Creg′
← undefined
← undefined
← undefined
Error signals: j 0 can cause a breakpoint trap to be signalled.
Comments:
Primary instruction.
Instruction is a descheduling point.
Instruction is a timeslicing point.
See also: cj lend
95/212
ladd
ladd
long add
Code: 21 F6
Description: Add with carry in and check for overflow. The result of the operation is
the sum of Areg, Breg and bit 0 of Creg.
Definition:
if (sum > MostPos)
{
Areg′ ← sum − 2BitsPerWord
IntegerOverflow
}
else if (sum < MostNeg)
{
Areg′ ← sum + 2BitsPerWord
IntegerOverflow
}
else
Areg′ ← sum
Breg′
Creg′
← undefined
← undefined
where
sum = Areg + Breg + Creg0
– the value of sum is calculated to unlimited precision
Error signals: IntegerOverflow can be signalled.
Comments:
Secondary instruction.
See also: lsum
96/212
lb
lb
load byte
Code: F1
Description: Load the unsigned byte addressed by Areg into Areg.
Definition:
← byte[Areg]
Areg′0..7
Areg′8..BitsPerWord-1
← 0
Error signals: none
Comments:
Secondary instruction.
See also: bsub devlb lbx ls ldul
97/212
lbx
lbx
load byte and sign extend
Code: 2B F9
Description: Load the byte addressed by Areg into Areg and sign extend to a word.
Definition:
← byte[Areg]
Areg′0..7
Areg′8..BitsPerWord-1 ← Areg′7
Error signals: none
Comments:
Secondary instruction.
See also: bsub devlb lb xbword lsx ldul
98/212
ldc n
ldc n
load constant
Code: Function 4
Description: Load constant into Areg.
Definition:
Areg′ ← n
Breg′
Creg′
← Areg
← Breg
Error signals: none
Comments:
Primary instruction.
See also: adc mint
99/212
ldclock
ldclock
load clock
Code: 64 FD
Description: Load into Areg the current value of ClockReg, of the priority selected
by Areg, where 0 indicates high priority and 1 indicates low priority.
Definition:
Areg′ ← ClockReg[Areg]
Error signals: none
Comments:
Secondary instruction.
See also: stclock
100/212
lddevid
lddevid
load device identity
Code: 21 27 FC
Description: See ldprodid. This instruction may be removed in future so ldprodid
should be used instead.
Definition:
Areg′ ← ProductId
Breg′
Creg′
← Areg
← Breg
Error signals: none
Comments:
Secondary instruction.
101/212
ldiff
ldiff
long diff
Code: 24 FF
Description: Subtract unsigned numbers with borrow in. Subtract Areg from Breg
minus borrow in from Creg, producing difference in Areg and borrow out in Breg,
without checking for overflow.
Definition:
if (diff ≥ 0)
{
Areg′unsigned
←
Breg′
←
}
else
{
Areg′unsigned
←
Breg′
←
}
Creg′ ← undefined
diff
0
diff + 2BitsPerWord
1
where diff = Bregunsigned − Aregunsigned − Creg0
– the value of diff is calculated to unlimited precision
Error signals: none
Comments:
Secondary instruction.
See also: lsub
102/212
ldinf
ldinf
load infinity
Code: 27 F1
Description: Load the single length floating point number +infinity onto the stack.
Definition:
Areg′ ← #7F800000
Breg′
Creg′
← Areg
← Breg
Error signals: none
Comments:
Secondary instruction.
See also: cflerr
103/212
ldiv
ldiv
long divide
Code: 21 FA
Description: Divide the double length unsigned integer in Breg and Creg (most
significant word in Creg) by an unsigned integer in Areg. The quotient is put into Areg
and the remainder into Breg. Overflow occurs if either the quotient is not
representable in a single word, or if a division by zero is attempted; the condition for
overflow is equivalent to Cregunsigned ≥ Aregunsigned.
Definition:
if (Cregunsigned ≥ Aregunsigned)
IntegerOverflow
else
{
Areg′unsigned
← long / Aregunsigned
Breg′unsigned
← long rem Aregunsigned
}
Creg′
← undefined
where long = (Cregunsigned × 2BitsPerWord) + Bregunsigned
– the value of long is calculated to unlimited precision
Error signals:
IntegerOverflow can occur.
Comments:
Secondary instruction.
See also: lmul
104/212
ldl n
ldl n
load local
Code: Function 7
Description: Load into Areg the local variable at the specified word offset in
workspace.
Definition:
Areg′ ← word[Wptr @ n]
Breg′
Creg′
← Areg
← Breg
Error signals: none
Comments:
Primary instruction.
See also: ldnl stl
105/212
ldlp n
ldlp n
load local pointer
Code: Function 1
Description: Load into Areg the address of the local variable at the specified offset in
workspace.
Definition:
Areg′
Breg′
Creg′
← Wptr @ n
← Areg
← Breg
Definition:
Error signals: none
Comments:
Primary instruction.
See also: ldl ldnlp stlp
106/212
ldmemstartval
ldmemstartval
load value of MemStart address
Code: 27 FE
Description: Load into Areg the address of the first free memor y location (as defined
in the MemStart configur ation register).
Definition:
Areg′ ← MemStart
Breg′
Creg′
← Areg
← Breg
Error signals: none
Comments:
Secondary instruction.
107/212
ldnl n
ldnl n
load non-local
Code: Function 3
Description: Load into Areg the non-local variable at the specified word offset from
Areg.
Definition:
Areg′ ← word[Areg @ n]
Error signals: none
Comments:
Primary instruction.
Areg should be word aligned.
See also: ldl ldnlp stnl
108/212
ldnlp n
ldnlp n
load non-local pointer
Code: Function 5
Description: Load into Areg the address at the specified word offset from the
address in Areg.
Definition:
Areg′ ← Areg @ n
Error signals: none
Comments:
Primary instruction.
See also: ldlp ldnl wsub
109/212
ldpi
ldpi
load pointer to instruction
Code: 21 FB
Description: Load into Areg an address relative to the current instruction pointer.
Areg contains a byte offset which is added to the address of the first byte following
this instruction.
Definition:
Areg′ ← next instruction + Areg
Error signals: none
Comments:
Secondary instruction.
110/212
ldpri
ldpri
load current priority
Code: 21 FE
Description: Load the current process priority into Areg, where 0 indicates high
priority and 1 indicates low priority.
Definition:
Areg′ ← Priority
Breg′
Creg′
← Areg
← Breg
Error signals: none
Comments:
Secondary instruction.
111/212
ldprodid
ldprodid
load product identity
Code: 68 FC
Description: Load a value indicating the product identity into Areg. Each product in
the ST20 family has a unique product identity code.
Definition:
Areg′ ← ProductId
Breg′
Creg′
← Areg
← Breg
Error signals: none
Comments:
Secondary instruction.
Different ST20 products may use the same processor type, but return different
product identity codes. However a product indentity code uniquely defines the
processor type used in that product.
112/212
ldshadow
ldshadow
load shadow registers
Code: 60 FC
Description: Selectively load (depending on Areg) the shadow registers of the
priority determined by Breg from the block of store addressed by Creg. This
instruction should only be used with Breg not equal to the current priority.
Definition:
if (Breg ≠ Priority)
{
if (Areg0 = 1)
{
GlobalInterruptEnables′
← word[Creg]16..23
TrapEnables′[Breg]
← word[Creg]0..13
}
if (Areg1 = 1)
{
Status′[Breg] ← word[Creg @ 1]
Wptr′[Breg]
← word[Creg @ 2]
Iptr′[Breg
← word[Creg @ 3]
}
if (Areg2 = 1)
{
Areg′[Breg]
← word[Creg @ 4]
Breg′[Breg]
← word[Creg @ 5]
Creg′[Breg]
← word[Creg @ 6]
}
if (Areg3 = 1)
{
Load block move registers for priority Breg from
word′[Creg @ 7] .. word′[Creg @ 11]
}
}
else
Undefined effect
Areg′
Breg′
Creg′
← undefined
← undefined
← undefined
Error signals: none
113/212
ldshadow
Comments:
Secondary instruction.
The effect of this instruction is undefined if the items other than the block move
registers are loaded into the current priority.
This instruction is abortable.
See also: stshadow restart
114/212
ldtimer
ldtimer
load timer
Code: 22 F2
Description: Load the value of the current priority timer into Areg.
Definition:
Areg′ ← ClockReg[Priority]
Breg′
Creg′
← Areg
← Breg
Error signals: none
Comments:
Secondary instruction.
See also: sttimer tin
115/212
ldtraph
ldtraph
load trap handler
Code: 26 FE
Description: Install the trap handler structure to be found at the address in Breg into
the trap handler location for the trap group given by Areg and priority given by Creg,
where 0 indicates high priority and 1 indicates low priority.
Definition:
word′[traphandler @
word′[traphandler @
word′[traphandler @
word′[traphandler @
Areg′
Breg′
Creg′
0]
1]
2]
3]
←
←
←
←
word[Breg @
word[Breg @
word[Breg @
word[Breg @
0]
1]
2]
3]
← undefined
← undefined
← undefined
where traphandler = the address of the trap handler for the trap group Areg
and priority Creg.
Error signals: Can cause a load trap trap to be signalled.
Comments:
Secondary instruction.
See also: ldtrapped sttraph sttrapped
116/212
ldtrapped
ldtrapped
load trapped process status
Code: 2C F6
Description: Install the trapped process structure, to be found at the address in
Breg, into the trapped process location for the trap group given by Areg and priority
given by Creg, where 0 indicates high priority and 1 indicates low priority.
Definition:
word′[trapped @
word′[trapped @
word′[trapped @
word′[trapped @
Areg′
Breg′
Creg′
0]
1]
2]
3]
←
←
←
←
word[Breg @
word[Breg @
word[Breg @
word[Breg @
0]
1]
2]
3]
← undefined
← undefined
← undefined
where trapped = the address of the stored trapped process for the trap group
Areg and priority Creg.
Error signals: Can cause a load trap trap to be signalled.
Comments:
Secondary instruction.
See also: ldtraph sttraph sttrapped
117/212
lend
lend
loop end
Code: 22 F1
Description: Adjust loop count and index, and do a conditional jump. Initially Areg
contains the byte offset from the first byte following this instruction to the loop start and
Breg contains a pointer to a loop end data structure, the first word of which is the loop
index and the second is the loop count. The count is decremented and, if the result is
greater than zero, the index is incremented and a jump to the start of the loop is taken.
The offset to the start of the loop is given as a positive number that is subtracted from
the instruction pointer.
Definition:
if (word[Breg @ le.Count] > 1)
{
word′[Breg @ le.Count] ← word[Breg @ le.Count] − 1
word′[Breg @ le.Index] ← word[Breg @ le.Index] + 1
Iptr′
← next instruction − Areg
}
Areg′
Breg′
Creg′
← undefined
← undefined
← undefined
Error signals: none
Comments:
Secondary instruction.
Instruction is a descheduling point.
Instruction is a timeslice point.
See also: cj j
118/212
lmul
lmul
long multiply
Code: 23 F1
Description: Form the double length product of Areg and Breg, with Creg as carry
in, treating the initial values as unsigned.
Definition:
Areg′unsigned
Breg′unsigned
Creg′
← prod rem 2BitsPerWord
← prod / 2BitsPerWord
← undefined
where prod = (Bregunsigned × Aregunsigned) + Cregunsigned
– the value of prod is calculated to unlimited precision
Error signals: none
Comments:
Secondary instruction.
See also: ldiv
119/212
ls
ls
load sixteen
Code: 2C FA
Description: Load the unsigned 16-bit object addressed by Areg into Areg.
Definition:
← sixteen[Areg]
Areg′0..15
Areg′16..BitsPerWord-1← 0
Error signals: none
Comments:
Secondary instruction.
See also: devls lsx ss ssub lt ldul
120/212
lshl
lshl
long shift left
Code: 23 F6
Description: Logical shift left the double word value in Creg and Breg (most
significant w ord in Creg) by the number of places specified in Areg. Only defined if the
shift length is less than twice the wordlength.
Definition:
if (0 ≤ Areg < 2 × BitsPerWord)
{
Areg′ ← (long << Aregunsigned) rem 2BitsPerWord
Breg′
}
else {
Areg′
Breg′
}
Creg′
← ((long << Aregunsigned) / 2BitsPerWord) rem 2BitsPerWord
← undefined
← undefined
← undefined
where long = (Cregunsigned × 2BitsPerWord) + Bregunsigned
– the value of long is calculated to double word precision
Error signals: none
Comments:
Secondary instruction.
The behavior for shift lengths outside the stated range is implementation
dependent.
See also: lshr norm
121/212
lshr
lshr
long shift right
Code: 23 F5
Description: Logical shift right the double word value in Creg and Breg (most
significant word in Creg) by the number of places specified in Areg. This instruction is
only defined if the shift length is less than twice the word length.
Definition:
if (0 ≤ Areg < 2 × BitsPerWord)
{
Areg′ ← (long >> Aregunsigned) rem 2BitsPerWord
Breg′
} else {
Areg′
Breg′
}
Creg′
← ((long >> Aregunsigned) / 2BitsPerWord) rem 2BitsPerWord
← undefined
← undefined
← undefined
where long = (Cregunsigned × 2BitsPerWord) + Bregunsigned
– the value of long is calculated to double word precision
Error signals: none
Comments:
Secondary instruction.
The behavior for shift lengths outside the stated range is implementation
dependent.
See also: lshl
122/212
lsub
lsub
long subtract
Code: 23 F8
Description: Subtract with borrow in and check for overflow. The result of the
operation, put into Areg, is Breg minus Areg, minus bit 0 of Creg.
Definition:
if (diff > MostPos)
{
Areg′ ← diff − 2BitsPerWord
IntegerOverflow
}
else if (diff < MostNeg)
{
Areg′ ← diff + 2BitsPerWord
IntegerOverflow
}
else
Areg′ ← diff
Breg′
Creg′
← undefined
← undefined
where diff = (Breg − Areg) − Creg0
– the value of diff is calculated to unlimited precision
Error signals: IntegerOverflow can be signalled.
Comments:
Secondary instruction.
See also: ldiff
123/212
lsum
lsum
long sum
Code: 23 F7
Description: Add unsigned numbers with carry in and carry out. Add Breg to Areg
(treated as unsigned numbers) plus carry in from Creg, producing the sum in Areg
and carry out in Breg, without checking for overflow.
Definition:
if (sum > MostPosUnsigned)
{
Areg′unsigned
← sum − 2BitsPerWord
Breg′
← 1
}
else
{
← sum
Areg′unsigned
Breg′
← 0
}
Creg′
← undefined
where sum = Aregunsigned + Bregunsigned + Creg0
– the value of sum is calculated to unlimited precision
Error signals: none
Comments:
Secondary instruction.
See also: ladd
124/212
lsx
lsx
load sixteen and sign extend
Code: 2F F9
Description: Load the 16-bit object addressed by Areg into Areg and sign extend to
a word.
Definition:
Areg′0..15
← sixteen[Areg]
Areg′16..BitsPerWord-1 ← Areg′15
Error signals: none
Comments:
Secondary instruction.
See also: devls ls ss xsword ltx ldnl
125/212
mint
mint
minimum integer
Code: 24 F2
Description: Load the most negative integer into Areg.
Definition:
Areg′ ← MostNeg
Breg′
Creg′
← Areg
← Breg
Error signals: none
Comments:
Secondary instruction.
126/212
move
move
move message
Code: 24 FA
Description: Copy Areg bytes to address Breg from address Creg. The copy is
performed using the minimum number of word reads and writes.
Definition:
if (source and destination overlap)
Undefined effect
else for i = 0..(Aregunsigned − 1)
byte′[Breg + i] ← byte[Creg + i]
Areg′
Breg′
Creg′
← undefined
← undefined
← undefined
Error signals: none
Comments:
Secondary instruction.
See also: devmove in move2dall out
127/212
move2dall
move2dall
2D block copy
Code: 25 FC
Description: Copy a 2D block of memory to another, non-overlapping, area using
parameters set up by move2dinit. The copy is performed using the minimum number
of word reads and writes. Areg is the number of bytes in each row, Breg is the
address of the destination, and Creg is the address of the source.
Definition:
if (source and destination overlap)
Undefined effect
else for y = 0 .. (count − 1)
{
for x = 0 .. (Aregunsigned − 1)
byte′[Breg + (y × dstStride) + x] ← byte[Creg + (y × srcStride) + x]
}
Areg′
Breg′
Creg′
← undefined
← undefined
← undefined
where
count
dstStride
srcStride
= Move2dBlockLength
= Move2dDestStride
= Move2dSourceStride
Error signals: none
Comments:
Secondary instruction.
Instruction is interruptible.
See also: move2dinit move2d nonzero move2dzero1
128/212
move2dinit
move2dinit
initialize data for 2D block move
Code: 25 FB
Description: Set up the first three par ameters for a 2D block move: Areg is the
number of rows to copy, Breg is the width of the destination array, and Creg is the
width of the source array. This instruction must be executed before each 2D block
move.
Definition:
Move2dBlockLength′
Move2dDestStride′
Move2dSourceStride′
Areg′
Breg′
Creg′
← Areg
← Breg
← Creg
← undefined
← undefined
← undefined
Error signals: none
Comments:
Secondary instruction.
See also: move2dall move2dnonzero move2dzero stmove2dinit
129/212
move2dnonzero
move2dnonzero
2D block copy non-zero bytes
Code: 25 FD
Description: Copy non-zero valued bytes from a 2D block of memory to another,
non-overlapping, area using parameters set up by move2dinit. The copy is performed
using the minimum number of word reads and writes. Areg is the number of bytes in
each row, Breg is the address of the destination, and Creg is the address of the
source.
Definition:
if (source and destination overlap)
Undefined effect
else for y = 0 .. (count − 1)
for x = 0 .. (Aregunsigned − 1)
if (byte[Creg + (y × srcStride) + x] ≠ 0)
byte′[Breg + (y × dstStride) + x] ← byte[Creg + (y × srcStride) + x]
Areg′
Breg′
Creg′
← undefined
← undefined
← undefined
where
count
dstStride
srcStride
=
=
=
Move2dBlockLength
Move2dDestStride
Move2dSourceStride
Error signals: none
Comments:
Secondary instruction.
Instruction is interruptible.
See also: move2dinit move2dzero move2dall
130/212
move2dzero
move2dzero
2D block copy zero bytes
Code: 25 FE
Description: Copy zero valued bytes from a 2D block of memory to another, nonoverlapping, area using parameters set up by move2dinit. The copy is performed
using the minimum number of word reads. Areg is the number of bytes in each row,
Breg is the address of the destination, and Creg is the address of the source.
Definition:
if (source and destination overlap)
Undefined effect
else for y = 0 .. (count − 1)
for x = 0 .. (Aregunsigned − 1)
if (byte[Creg + (y × srcStride) + x] = 0)
byte′[Breg + (y × dstStride) + x] ← byte[Creg + (y × srcStride) + x]
Areg′
Breg′
Creg′
← undefined
← undefined
← undefined
where
count
dstStride
srcStride
=
=
=
Move2dBlockLength
Move2dDestStride
Move2dSourceStride
Error signals: none
Comments:
Secondary instruction.
Instruction is interruptible.
See also: move2dinit
131/212
mul
mul
multiply
Code: 25 F3
Description: Multiply Areg by Breg, with checking for overflow.
Definition:
Areg′ ← Areg ×checked Breg
Breg′
Creg′
← Creg
← undefined
Error signals:
IntegerOverflow can be signalled by ×checked
Comments:
Secondary instruction.
See also: prod
132/212
nop
nop
no operation
Code: 63 F0
Description: Perform no operation.
Definition:
no effect
Error signals: none
Comments:
Secondary instruction.
133/212
norm
norm
normalize
Code: 21 F9
Description: Normalize the unsigned double length number stored in Breg and Areg
(most significant word in Breg). The value is shifted left until the most significant bit is
a one. The number of places shifted is returned in Creg. This instruction is used as
the first instr uction in the single length floating point rounding code sequence , norm;
postnormsn; roundsn.
Definition:
if ((Bregunsigned = 0) and (Aregunsigned = 0))
Creg′ ← 2 × BitsPerWord
else
{
Creg′
← number of most significant zero bits in long
← (long << Creg′) rem 2BitsPerWord
Areg′unsigned
Breg′unsigned
← ((long << Creg′) / 2BitsPerWord) rem 2BitsPerWord
}
where long = (Bregunsigned × 2BitsPerWord) + Aregunsigned
– the value of long is calculated to double word precision
Error signals: none
Comments:
Secondary instruction.
See also: lshl lshr postnormsn roundsn shl shr
134/212
not
not
not
Code: 23 F2
Description: Complement bits in Areg.
Definition:
Areg′ ← ∼Areg
Error signals: none
Comments:
Secondary instruction.
135/212
or
or
or
Code: 24 FB
Description: Bitwise or of Areg and Breg.
Definition:
Areg′ ← Breg ∨ Areg
Breg′
Creg′
← Creg
← undefined
Error signals: none
Comments:
Secondary instruction.
136/212
out
out
output message
Code: FB
Description: Output a message (where the corresponding input is performed by an
in instruction, and must specify a message of the same length). Areg is the unsigned
length, Breg is a pointer to the channel, and Creg is a pointer to the message. The
process executing out will be descheduled if the channel is external or is not ready; it
is rescheduled when the communication is complete. This instruction is also used to
synchronize with an alternative.
Definition:
Synchronize, and output Aregunsigned bytes to channel Breg from address
Creg
Areg′
Breg′
Creg′
← undefined
← undefined
← undefined
Error signals: Can cause InternalChannel or ExternalChannel trap to be signalled (if
enabled) when the process is rescheduled on synchronization.
Comments:
Secondary instruction.
See also: altwt enbc in outbyte outword
137/212
outbyte
outbyte
output byte
Code: FE
Description: Output the least significant byte of Areg to the channel pointed to by
Breg (where the corresponding input is performed by an in instruction, and must
specify a single byte message). The process executing outbyte will be descheduled if
the channel is external or is not ready; it is rescheduled when the communication is
complete. This instruction is also used to synchronize with an alternative.
Definition:
Synchronize, and output least significant b yte of Areg to channel Breg
word′[Wptr @ pw.Temp]
Areg′
Breg′
Creg′
←
←
←
←
undefined
undefined
undefined
undefined
Error signals: Can cause InternalChannel or ExternalChannel trap to be signalled (if
enabled) when process is rescheduled on synchronization.
Comments:
Secondary instruction.
Instruction is a descheduling point.
Instruction is interruptible.
Uses the pw.Temp slot in the process workspace.
See also: altwt enbc in out outword
138/212
outword
outword
output word
Code: FF
Description: Output the word in Areg to the channel pointed to by Breg (the
corresponding input is performed by an in instruction, and must specify a four byte
message). The process executing outword will be descheduled if the channel is
external or is not ready; it is rescheduled when the communication is complete. This
instruction is also used to synchronize with an alternative.
Definition:
Synchronize, and output Areg to channel Breg
word′[Wptr @ pw.Temp]
Areg′
Breg′
Creg′
←
←
←
←
undefined
undefined
undefined
undefined
Error signals: Can cause InternalChannel or ExternalChannel trap to be signalled (if
enabled) when the process is rescheduled on synchronization.
Comments:
Secondary instruction.
Instruction is a descheduling point.
Instruction is interruptible.
Uses the pw.Temp slot in the process workspace.
See also: altwt enbc in out outbyte
139/212
pop
pop
pop processor stack
Code: 27 F9
Description: Pop top element of integer stack.
Definition:
Areg′ ← Breg
Breg′ ← Creg
Creg′ ← undefined
Error signals: none
Comments:
Secondary instruction.
See also: dup rev
140/212
postnormsn
postnormsn
post-normalize correction of single
length fp number
Code: 26 FC
Description: Perform the post normalised correction on a floating point number,
where initially the normalised fraction is in Areg, Breg and Creg as left by the
instruction norm, and the exponent is in location pw.Temp in the workspace. This
instruction is only intended to be used in the single length rounding code sequence
immediately after norm and before roundsn.
Definition:
Areg′ ← post-normalised guardword
Breg′ ← post-normalised fractionword
Creg′ ← post-normalised exponent
Error signals: none
Comments:
Secondary instruction.
This instruction uses location pw.Temp in the workspace.
See also: roundsn norm
141/212
prod
prod
product
Code: F8
Description: Multiply Areg by Breg without checking for overflow.
Definition:
Areg′ ← Areg × Breg
Breg′
Creg′
← Creg
← undefined
Error signals: none
Comments:
Secondary instruction.
See also: mul
142/212
reboot
reboot
reboot
Code: 68 FD
Description: Perform a cold boot. Reset all machine states to the initial state and
execute the boot microcode. This examines the state of the BootFromRom pin and
reboots accordingly.
Error signals:
Reboot the machine and either listen for a boot protocol on link or jump to ROM
entry point
Error signals: none
Comments:
Secondary instruction.
143/212
rem
rem
remainder
Code: 21 FF
Description: Calculate the remainder when Breg is divided by Areg. The sign of the
remainder is the same as the sign of Breg.
The remainder, r = x rem y, is defined b y r = x − (y × (x / y)).
Definition:
if (Areg = 0)
{
Areg′ ← undefined
IntegerOverflow
}
else
Areg′ ← Areg rem Breg
Breg′
Creg′
← Creg
← undefined
Error signals:
IntegerOverflow signalled when a remainder by zero is attempted.
Comments:
Secondary instruction.
See also: div
144/212
resetch
resetch
reset channel
Code: 21 F2
Description: Reset the channel pointed to by Areg. Returns the channel to the
empty state. If the channel address points to a hard channel, then the link hardware is
reset. Areg returns the process descriptor of the process waiting on the channel.
Definition:
if (Areg points to external channel)
reset link hardware
word′[Areg]
Areg′
← NotProcess.p
← word[Areg]
Error signals: none
Comments:
Secondary instruction.
This instruction is abortable.
145/212
restart
restart
restart
Code: 62 FE
Description: Restart execution of a saved process in place of the current process.
Areg is a pointer to a processor state data structure which will have been obtained
using stshadow.
Definition:
GlobalInterruptEnables′ ← word[Areg @ 0]16..23
TrapEnables′
← word[Areg @ 0]0..13
Status′
← word[Areg @ 1]
Wptr′
← word[Areg @ 2]
Iptr′
← word[Areg @ 3]
Areg′
← word[Areg @ 4]
Breg′
← word[Areg @ 5]
Creg′
← word[Areg @ 6]
Load block move registers for current priority from
word′[Areg @ 7] .. word′[Areg @ 11]
Error signals: none
Comments:
Secondary instruction.
See also: ldshadow stshadow
146/212
ret
ret
return
Code: 22 F0
Description: Return from a subroutine and de-allocate workspace.
Definition:
Iptr′
← word[Wptr @ 0]
Wptr′ ← Wptr @ 4
Error signals: none
Comments:
Secondary instruction.
See also: ajw call
147/212
rev
rev
reverse
Code: F0
Description: Swap the top two elements of the evaluation stack.
Definition:
Areg′ ← Breg
Breg′ ← Areg
Error signals: none
Comments:
Secondary instruction.
See also: dup pop
148/212
roundsn
roundsn
round single length floating point number
Code: 26 FD
Description: Round an unpacked result of a floating point oper ation into Areg.
Rounding is performed in round-to-nearest mode, as defined b y IEEE-754. Initially the
post-normalised guardword, fractionword and exponent are in Areg, Breg, and Creg,
as left by the instruction postnormsn. This instruction is only intended to be used in
the single length rounding code sequence immediately after postnormsn.
Definition:
Areg′ ← rounded and packed fp number
Breg′ ← undefined
Creg′ ← undefined
Error signals: none
Comments:
Secondary instruction.
See also: postnormsn unpacksn
149/212
runp
runp
run process
Code: 23 F9
Description: Schedule a (descheduled) process. The process descriptor of the
process is in Areg; this identifies the process workspace and priority. The instruction
pointer is loaded from the process’ workspace data structure.
Definition:
Put process Areg onto the back of the appropriate scheduling list
Areg′
Breg′
Creg′
← undefined
← undefined
← undefined
Error signals: none
Comments:
Secondary instruction.
See also: endp startp stopp
150/212
satadd
satadd
saturating add
Code: 26 F8
Description: Perform addition using ‘saturating arithmetic’ i.e. signed arithmetic
where overflowing results do not wrap round but return MostPos or MostNeg
according to the sign of the result. This instruction is used for clipping algorithms in
signal processing.
Definition:
if (sum > MostPos)
Areg′ ← MostPos
else if (sum < MostNeg)
Areg′ ← MostNeg
else
Areg′ ← sum
Breg′
Creg′
← Creg
← undefined
where sum = Breg + Areg
– sum is calculated to unlimited precision
Error signals: none
Comments:
Secondary instruction.
See also: satsub satmul
151/212
satmul
satmul
saturating multiply
Code: 26 FA
Description: Perform multiplication using ‘saturating arithmetic’ i.e. signed arithmetic
where overflowing results do not wrap round but return MostPos or MostNeg
according to the sign of the result. This instruction is used for clipping algorithms in
signal processing.
Definition:
if (prod > MostPos)
Areg′ ← MostPos
else if (prod < MostNeg)
Areg′ ← MostNeg
else
Areg′ ← prod
Breg′
Creg′
← Creg
← undefined
where prod = Breg × Areg
– prod is calculated to unlimited precision
Error signals: none
Comments:
Secondary instruction.
See also: satadd satsub
152/212
satsub
satsub
saturating subtract
Code: 26 F9
Description: Perform subtraction using ‘saturating arithmetic’ i.e. signed arithmetic
where overflowing results do not wrap round but return MostPos or MostNeg
according to the sign of the result. This instruction is used for clipping algorithms in
signal processing.
Definition:
if (diff > MostPos)
Areg′ ← MostPos
else if (diff < MostNeg)
Areg′ ← MostNeg
else
Areg′ ← diff
Breg′
Creg′
← Creg
← undefined
where diff = Breg − Areg
– diff is calculated to unlimited precision
Error signals: none
Comments:
Secondary instruction.
See also: satadd satmul
153/212
saveh
saveh
save high priority queue registers
Code: 23 FE
Description: Save high priority queue pointers. Stores the contents of the high
priority scheduling registers in the block given by the address in Areg.
This instruction has been superceded by insertqueue and swapqueue which should
be used instead.
Definition:
word′[Areg @ 0]
word′[Areg @ 1]
Areg′
Breg′
Creg′
← ProcQueueFPtr[HighPriority]
← ProcQueueBPtr[HighPriority]
← Breg
← Creg
← undefined
Error signals: none
Comments:
Secondary instruction.
See also: savel insertqueue swapqueue
154/212
savel
savel
save low priority queue registers
Code: 23 FD
Description: Save low priority queue pointers. Stores the contents of the low priority
scheduling registers in the block given by the address in Areg.
This instruction has been superceded by insertqueue and swapqueue which should
be used instead.
Definition:
word′[Areg @ 0]
word′[Areg @ 1]
Areg′
Breg′
Creg′
← ProcQueueFPtr[LowPriority]
← ProcQueueBPtr[LowPriority]
← Breg
← Creg
← undefined
Error signals: none
Comments:
Secondary instruction.
See also: saveh insertqueue swapqueue
155/212
sb
sb
store byte
Code: 23 FB
Description: Store the least significant b yte of Breg into the byte of memory
addressed by Areg.
Definition:
byte′[Areg] ← Breg0..7
Areg′
Breg′
Creg′
← Creg
← undefined
← undefined
Error signals: none
Comments:
Secondary instruction.
See also: bsub devsb lb lbx ss stnl
156/212
seterr
seterr
set error flags
Code: 21 F0
Description: Unconditionally set the error flag for the current priority.
Definition:
ErrorFlag′[Priority] ← set
Error signals:
The error flag is set by this instruction.
Comments:
Secondary instruction.
See also: stoperr testerr
157/212
sethalterr
sethalterr
set halt-on-error flag
Code: 25 F8
Description: Set the HaltOnError flag to put the processor into halt-on-error mode.
Definition:
HaltOnErrorFlag′
← set
Error signals: none
Comments:
Secondary instruction.
See also: clrhalterr tsthalterr
158/212
settimeslice
settimeslice
set timeslicing status
Code: 2B F0
Description: Enable or disable timeslicing of the current process, depending on the
value of Areg, and set Areg to indicate whether timeslicing was enabled or disabled
prior to execution of the instruction. If Areg is initially false timeslicing is disabled until
either the process deschedules or timeslicing is enabled. If Areg is initially true
timeslicing is enabled. This instruction is only meaningful when run at low priority.
Definition:
if (Areg = false)
Disable timeslicing
else if (Areg = true)
Enable timeslicing
else
Undefined effect
(timeslicing was previously enabled)
Areg′ ← true
else
Areg′ ← false
if
Error signals: none
Comments:
Secondary instruction.
See also: intdis intenb
159/212
shl
shl
shift left
Code: 24 F1
Description: Logical shift left Breg by Areg places, filling with z ero bits. If the initial
Areg is not between 0 and 31 inclusive then the result is zero. The result is only
defined for shift lengths less than the word length.
Definition:
if (0 ≤ Areg < BitsPerWord)
Areg′ ← Breg << Areg
else
Areg′ ← undefined
Breg′
Creg′
← Creg
← undefined
Error signals: none
Comments:
Secondary instruction.
The behavior for shift lengths outside the stated range is implementation
dependent.
See also: lshl lshr norm shr
160/212
shr
shr
shift right
Code: 24 F0
Description: Logical shift right Breg by Areg places, filling with z ero bits. If the initial
Areg is not between 0 and 31 inclusive then the result is zero. The result is only
defined for shift lengths less than the word length.
Definition:
if (0 ≤ Areg < BitsPerWord)
Areg′ ← Breg >> Areg
else
Areg′ ← undefined
Breg′
Creg′
← Creg
← undefined
Error signals: none
Comments:
Secondary instruction.
The behavior for shift lengths the outside stated range is implementation
dependent.
See also: lshl lshr norm shl
161/212
signal
signal
signal
Code: 60 F4
Description: Signal (or V) on the semaphore pointed to by Areg. If no process is
waiting then the count is incremented, otherwise the first process on the semaphore
list is rescheduled.
Definition:
if (word[Areg @ s.Front] = NotProcess.p)
word′[Areg @ s.Count] ← word[Areg @ s.Count] + 1
else
Remove the process from the front of the semaphore list and put it on the
scheduling list
Areg′
Breg′
Creg
← undefined
← undefined
← undefined
Error signals: Can cause the Signal trap to be signalled if a process is rescheduled.
Comments:
Secondary instruction.
Count increment is unchecked.
See also: wait
162/212
slmul
slmul
signed long multiply
Code: 26 F4
Description: Perform signed long multiplication. This instruction forms the double
length product of Areg and Breg, with Creg as carry in, treating the initial values Areg
and Breg as signed.
Definition:
Areg′
Breg′
Creg′
unsigned
← prod rem 2BitsPerWord
← prod / 2BitsPerWord
← undefined
where prod = (Breg × Areg) + Cregunsigned
– the value of prod is calculated to unlimited precision
Error signals: none
Comments:
Secondary instruction.
See also: lmul sulmul
163/212
ss
ss
store sixteen
Code: 2C F8
Description: Store bits 0..15 of Breg into the sixteen bits of memory addressed by
Areg.
Definition:
sixteen′[Areg] ← Breg0..15
Areg′
Breg′
Creg′
← Creg
← undefined
← undefined
Error signals: none
Comments:
Secondary instruction.
See also: devss ldlp ldnlp ls lsx sb stl stnl ssub
164/212
ssub
ssub
sixteen subscript
Code: 2C F1
Description: Generate the address of the element which is indexed by Breg, in an
array of 16-bit objects pointed to by Areg.
Definition:
Areg′ ← Areg + (2 × Breg)
Breg′ ← Creg
Creg′ ← undefined
Error signals: none
Comments:
Secondary instruction.
See also: bcnt bsub wcnt wsub wsubdb
165/212
startp
startp
start process
Code: FD
Description: Create and schedule a process at the current priority. Initially Areg is a
pointer to the workspace of the new process and Breg is the offset from the next
instruction to the instruction pointer of the new process.
Definition:
word′[Areg @ pw.Iptr]
← next instruction + Breg
Put the process Areg onto the back of the scheduling list for the current priority
Areg′
Breg′
Creg′
← undefined
← undefined
← undefined
Error signals: none
Comments:
Secondary instruction.
See also: endp runp
166/212
stclock
stclock
store clock register
Code: 64 FC
Description: Store the contents of Breg into the clock register of priority Areg.
Definition:
ClockReg[Areg]
Areg′
Breg′
Creg′
← Breg
← Creg
← undefined
← undefined
Error signals: none
Comments:
Secondary instruction.
See also: ldclock
167/212
sthb
sthb
store high priority back pointer
Code: 25 F0
Description: Store the contents of Areg into the back pointer of the high priority
queue.
This instruction has been superceded by insertqueue and swapqueue which should
be used instead.
Definition:
ProcQueueBPtr[HighPriority]
← Areg
Error signals: none
Comments:
Secondary instruction.
See also: insertqueue sthf stlb stlf swapqueue
168/212
sthf
sthf
store high priority front pointer
Code: 21 F8
Description: Store the contents of Areg into the front pointer of the high priority
queue.
This instruction has been superceded by insertqueue and swapqueue which should
be used instead.
Definition:
ProcQueueFPtr[HighPriority]
← Areg
Error signals: none
Comments:
Secondary instruction.
See also: insertqueue sthb stlb stlf swapqueue
169/212
stl n
stl n
store local
Code: Function D
Description: Store the contents of Areg into the local variable at the specified w ord
offset in workspace.
Definition:
word′[Wptr @ n]
Areg′
Breg′
Creg′
← Areg
← Breg
← Creg
← undefined
Error signals: none
Comments:
Primary instruction.
See also: devsw ldl ldlp sb ss stnl
170/212
stlb
stlb
store low priority back pointer
Code: 21 F7
Description: Store the contents of Areg into the back pointer of the low priority
queue.
This instruction has been superceded by insertqueue and swapqueue which should
be used instead.
Definition:
ProcQueueBPtr[LowPriority]
← Areg
Error signals: none
Comments:
Secondary instruction.
See also: insertqueue sthb sthf stlf swapqueue
171/212
stlf
stlf
store low priority front pointer
Code: 21 FC
Description: Store the contents of Areg into the front pointer of the low priority
queue.
This instruction has been superceded by insertqueue and swapqueue which should
be used instead.
Definition:
ProcQueueFPtr[LowPriority]
← Areg
Error signals: none
Comments:
Secondary instruction.
See also: insertqueue sthb sthf stlb swapqueue
172/212
stnl n
stnl n
store non-local
Code: Function E
Description: Store the contents of Breg into the non-local variable at the specified
word offset from Areg.
Definition:
word′[Areg @ n]
Areg′
Breg′
Creg′
← Breg
← Creg
← undefined
← undefined
Error signals: none
Comments:
Primary instruction.
See also: devsw ldlp ldnlp sb ss stl
173/212
stoperr
stoperr
stop on error
Code: 25 F5
Description: Deschedule the current process if the ErrorFlag is set.
Definition:
if (ErrorFlag[Priority] = set)
word′[Wptr @ pw.Iptr] ← next instruction
Stop process
Error signals: none
Comments:
Secondary instruction.
See also: seterr testerr
174/212
stopp
stopp
stop process
Code: 21 F5
Description: Terminate the current process, saving the current Iptr for later use.
Definition:
word′[Wptr @ pw.Iptr]
Areg′
Breg′
Creg′
← next instruction
← undefined
← undefined
← undefined
Error signals: none
Comments:
Secondary instruction.
See also: endp runp startp
175/212
stshadow
stshadow
store shadow registers
Code: 60 FD
Description: Selectively store shadow registers of priority Breg into the block of store
addressed by Creg. This instruction is normally used in high priority with Breg set to 1
for low priority. Storing high priority registers from low priority will give undefined
values.
Definition:
if (Areg0 = 1)
{
← GlobalInterruptEnables
word′[Creg]16..23
word′[Creg]0..13
← TrapEnables[Breg]
}
if (Areg1 = 1)
{
word′[Creg @ 1]
← Status[Breg]
word′[Creg @ 2]
← Wptr[Breg]
word′[Creg @ 3]
← Iptr[Breg]
}
if (Areg2 = 1)
{
word′[Creg @ 4]
← Areg[Breg]
word′[Creg @ 5]
← Breg[Breg]
word′[Creg @ 6]
← Creg[Breg]
}
if (Areg3 = 1)
Store block move registers for priority Breg in
word′[Creg @ 7] .. word′[Creg @ 11]
Areg′
Breg′
Creg′
← undefined
← undefined
← undefined
Error signals: none
Comments:
Secondary instruction.
See also: ldshadow restart
176/212
sttimer
sttimer
store timer
Code: 25 F4
Description: Initialize the timers. Set the low and high priority clock registers to the
value in Areg and start them ticking and scheduling ready processes.
Definition:
Clockreg′[0]
Clockreg′[1]
Start timers
Areg′
Breg′
Creg′
← Areg
← Areg
← Breg
← Creg
← undefined
Error signals: none
Comments:
Secondary instruction.
See also: clockenb clockdis ldclock
177/212
sttraph
sttraph
store trap handler
Code: 26 FF
Description: Store the trap handler structure from the trap handler location for the
trap group given by Areg and priority given by Creg, where 0 indicates high priority
and 1 indicates low priority, to the block of memory pointed to by Breg.
Definition:
word′[Breg
word′[Breg
word′[Breg
word′[Breg
Areg′
Breg′
Creg′
@ 0]
@ 1]
@ 2]
@ 3]
← word[traphandler @ 0]
← word[traphandler @ 1]
← word[traphandler @ 2]
← word[traphandler @ 3]
← undefined
← undefined
← undefined
where traphandler is the address of the traphandler for the trap group
Areg and priority Creg.
Error signals:
Will cause a StoreTrap trap if enabled.
Comments:
Secondary instruction.
See also: ldtraph ldtrapped sttrapped
178/212
sttrapped
sttrapped
store trapped process
Code: 2C FB
Description: Store the trapped process structure from the trapped process location
for the trap group given by Areg and priority given by Creg, where 0 indicates high
priority and 1 indicates low priority, to the block of memory pointed to by Breg.
Definition:
word′[Breg
word′[Breg
word′[Breg
word′[Breg
Areg′
Breg′
Creg′
@ 0]
@ 1]
@ 2]
@ 3]
← word[trapped @ 0]
← word[trapped @ 1]
← word[trapped @ 2]
← word[trapped @ 3]
← undefined
← undefined
← undefined
where trapped is the address of the stored trapped process for the trap group
Areg and priority Creg.
Error signals:
Will cause a StoreTrap trap if enabled.
Comments:
Secondary instruction
See also: ldtrph ldtrapped sttraph
179/212
sub
sub
subtract
Code: FC
Description: Subtract Areg from Breg, with checking for overflow.
Definition:
Areg′ ← Breg −checked Areg
Breg′
Creg′
← Creg
← undefined
Error signals:
IntegerOverflow can be signalled by −checked
Comments:
Secondary instruction.
See also: diff add
180/212
sulmul
sulmul
signed times unsigned long multiply
Code: 26 F5
Description: Perform signed long multiplication. This instruction forms the double
length product of Areg and Breg, with Creg as carry in, treating the initial value Areg
as signed and Breg as unsigned.
Definition:
Areg′unsigned
← prod rem 2BitsPerWord
Breg′
← prod / 2BitsPerWord
Creg′
← undefined
where prod = (Bregunsigned × Areg) + Cregunsigned
– the value of prod is calculated to unlimited precision
Error signals: none
Comments:
Secondary instruction.
See also: lmul slmul
181/212
sum
sum
sum
Code: 25 F2
Description: Add Areg and Breg, without checking for overflow.
Definition:
Areg′ ← Breg + Areg
Breg′
Creg′
← Creg
← undefined
Error signals: none
Comments:
Secondary instruction.
See also: add bsub diff
182/212
swapqueue
swapqueue
swap scheduler queue
Code: 60 F0
Description: Swap the scheduling list of priority indicated by Areg, where 0 indicates
high priority and 1 indicates low priority. Breg and Creg are the front and back
pointers, respectively, of the list to be inserted. The old front and back pointers are
returned in Areg and Breg, respectively.
Definition:
Areg′
Breg′
ProcQueueFPtr′[Areg]
ProcQueueBPtr′[Areg]
Creg′
←
←
←
←
ProcQueueFPtr[Areg]
ProcQueueBPtr[Areg]
Breg
Creg
← undefined
Error signals: none
Comments:
Secondary instruction.
See also: insertqueue swaptimer
183/212
swaptimer
swaptimer
swap timer queue
Code: 60 F1
Description: Swap the timer list of priority indicated by Areg and update the alarm
register for the new list. An initial Areg of value 0 indicates high priority and 1 indicates
low priority. Breg is the front pointer of the list to be inserted. The old front pointer is
returned in Areg.
Definition:
if (Breg ≠ NotProcess.p)
Tnextreg′[Areg]
← word[Breg @ pw.Time]
Areg′
Tptrreg′[Areg]
Breg′
Creg′
← TptrReg[Areg]
← Breg
← undefined
← undefined
Error signals: none
Comments:
Secondary instruction.
See also: swapqueue
184/212
talt
talt
timer alt start
Code: 24 FE
Description: Start a timer alternative sequence. The pw.State location of the
workspace is set to Enabling.p, and the pw.TLink location is set to TimeNotSet.p.
Definition:
Enter alternative sequence
word′[Wptr @ pw.State]
word′[Wptr @ pw.TLink]
← Enabling.p
← TimeNotSet.p
Error signals: none
Comments:
Secondary instruction.
See also: alt altend altwt disc disg diss dist enbc enbg enbs enbt taltwt
185/212
taltwt
taltwt
timer alt wait
Code: 25 FI
Description: Wait until one of the enabled guards of a timer alternative is ready and
initialize pw.Temp for use during the disabling sequence. If the alternative has no
ready guard but may become ready due to a timer, place the process onto the timer
list.
Definition:
if (word[Wptr @ pw.State] = Ready.p)
word′[Wptr @ pw.Time]
← ClockReg[Priority]
else if (word[Wptr @ pw.Tlink] = TimeNotSet.p)
{
word′[Wptr @ pw.State]
← Waiting.p
deschedule process and wait for one of the guards to become ready
}
else if (word[Wptr @ pw.Tlink] = TimeSet.p)
{
if (ClockReg[Priority] after word[Wptr @ pw.Time]
{
word′[Wptr @ pw.State]
← Ready.p
word′[Wptr @ pw.Time]
← ClockReg[Priority]
}
else
{
word′[Wptr @ pw.Time]
← (word[Wptr @ pw.Time] + 1)
insert this process into timer list with alarm time (word[Wptr @ pw.Time] + 1)
if (no guards ready)
{
word′[Wptr @ pw.State] ← Waiting.p
deschedule process and wait for one of the guards to become ready
}
}
}
else
Undefined effect
word′[Wptr @ pw.Temp]
Areg′
Breg′
Creg′
← NoneSelected.o
← undefined
← undefined
← undefined
Error signals: none
186/212
taltwt
Comments:
Secondary instruction.
Instruction is a descheduling point.
Instruction is interruptible.
Uses the pw.Temp and pw.State slots in the process workspace.
See also: alt altend altwt disc diss dist enbc enbs enbt talt
187/212
testerr
testerr
test error flag
Code: 22 F9
Description: Test the error flag at the current pr iority, returning false in Areg if error is
set, true otherwise. It also clears the error flag.
Definition:
if (ErrorFlag[Priority] = set)
Areg′ ← false
else
Areg′ ← true
ErrorFlag′[Priority] ← clear
Error signals: none
Comments:
Secondary instruction.
See also: seterr stoperr
188/212
testhalterr
testhalterr
test halt-on-error flag
Code: 25 F9
Description: Test HaltOnError mode. If HaltOnError is set then Areg is set to true
otherwise Areg is set to false.
Definition:
if (HaltOnError = set)
Areg′ ← true
else
Areg′ ← false
Breg′
Creg′
← Areg
← Breg
Error signals: none
Comments:
Secondary instruction.
See also: clrhalterr sethalterr
189/212
testpranal
testpranal
test processor analysing
Code: 22 FA
Description: Push true onto the stack if the processor was analyzed when the
processor was last reset, or false otherwise.
Definition:
if (analyse asserted on last reset)
Areg′ ← true
else
Areg′ ← false
Breg′
Creg′
← Areg
← Breg
Error signals: none
Comments:
Secondary instruction.
190/212
timeslice
timeslice
timeslice
Code: 60 F3
Description: Cause a timeslice, putting the current process on the back of the
scheduling list and executing the next process. If the scheduling list is empty then this
instruction acts as a no-operation.
Definition:
if (scheduling list empty)
no effect
else
{
Put current process on back of list
Start next process
}
Areg′
Breg′
Creg′
← undefined
← undefined
← undefined
Error signals: Can cause a timeslice trap to be signalled.
Comments:
Secondary instruction.
This instruction works at high and low priorities.
This instruction is unaffected by disabling timeslice.
Instruction is a descheduling point.
191/212
tin
tin
timer input
Code: 22 FB
Description: If Areg is after the value of the current priority clock, deschedule until
the current priority clock is after the time in Areg.
Definition:
if not (ClockReg[Priority] after Areg)
{
word′[Wptr @ pw.State]
← Enabling.p
word′[Wptr @ pw.Time]
← (Areg + 1)
Insert process into timer list with time of (Areg + 1) and start next process
}
Areg′
Breg′
Creg′
← undefined
← undefined
← undefined
Error signals: none
Comments:
Secondary instruction.
Instruction is a descheduling point.
Instruction is interruptible.
Uses pw.State slot in the process workspace.
See also: enbt dist ldtimer talt taltwt
192/212
trapdis
trapdis
trap disable
Code: 60 F6
Description: Disable those traps selected by the mask in Areg at the priority
selected by Breg, where 0 indicates high priority and 1 indicates low priority. The
original value of TrapEnables is returned in Areg.
Definition:
TrapEnables′[Breg]
← TrapEnables[Breg] ∧ ∼Areg
Areg′13..0
← TrapEnables[Breg]
← 0
Areg′31..14
Breg′
Creg′
← undefined
← undefined
Error signals: none
Comments:
Secondary instruction.
See also: trapenb
193/212
trapenb
trapenb
trap enable
Code: 60 F7
Description: Enable those traps selected by the mask in Areg at the priority selected
by Breg, where 0 indicates high priority and 1 indicates low priority. The original value
of TrapEnables is returned in Areg.
Definition:
TrapEnables′[Breg]
← TrapEnables[Breg] ∨ Areg
Areg′13..0
← TrapEnables[Breg]
← 0
Areg′31..14
Breg′
Creg′
← undefined
← undefined
Error signals: none
Comments:
Secondary instruction
See also: trapdis
194/212
tret
tret
trap return
Code: 60 FB
Description: Return from a trap handler.
Definition:
GlobalInterruptEnables′ ←
TrapEnables[Priority] ←
Status′
←
Wptr′
←
Iptr′
←
word[traphandler @
word[traphandler @
word[traphandler @
word[traphandler @
word[traphandler @
0]16..23
0]0..13
1]
2]
3]
where traphandler is the address of the traphandler for the trap group
of the current handler and the current priority.
Error signals: none
Comments:
Secondary instruction.
See also: ldtraph sttraph
195/212
unpacksn
unpacksn
unpack single length fp number
Code: 26 F3
Description: Unpack a packed IEEE single length floating point n umber. Areg
initially holds the packed number, and the instruction returns the exponent in Breg and
the fractional field in Areg, not including the implied most significant bit for normalised
numbers. In addition a code indicating the type of number is added to 4 times the
initial value of Breg and left in Creg. The codes are:
0
1
2
3
if Areg is zero
if Areg is a denormalised or normalised number
if Areg is an infinity
if Areg is not-a-number
Definition:
Areg′ ← fractional field contents of Areg
Breg′ ← exponent field contents of Areg
Creg′ ← 4 × Breg + ‘code’ of type of Areg (see above)
Error signals: none
Comments:
Secondary instruction.
See also: roundsn postnormsn
196/212
wait
wait
wait
Code: 60 F5
Description: Wait (or P) on the semaphore pointed to by Areg. If the semaphore
count is greater than zero then the count is decremented and the process continues;
otherwise the current process is descheduled and added to the back of the
semaphore list.
Definition:
if (word[Areg @ s.Count] = 0)
{
Put process on back of semaphore list
Start next process
}
else
word′[Areg @ s.Count] ← word[Areg @ s.Count] − 1
Areg′
Breg′
Creg′
← undefined
← undefined
← undefined
Error signals: none
Comments:
Secondary instruction.
Instruction is a descheduling point.
See also: signal
197/212
wcnt
wcnt
word count
Code: 23 FF
Description: Convert the byte offset in Areg to a word offset and a byte selector.
Definition:
Areg′ ← (Areg ∧ WordSelectMask) / BytesPerWord
Breg′ ← Areg ∧ ByteSelectMask
Creg′
← Breg
Error signals: none
Comments:
Secondary instruction.
198/212
wsub
wsub
word subscript
Code: FA
Description: Generate the address of the element which is indexed by Breg, in the
word array pointed to by Areg.
Definition:
Areg′ ← Areg @ Breg
Breg′
Creg′
← Creg
← undefined
Error signals: none
Comments:
Secondary instruction.
See also: bsub ldlp ldnlp ssub wcnt wsubdb
199/212
wsubdb
wsubdb
form double word subscript
Code: 28 F1
Description: Generate the address of the element which is indexed by Breg, in the
double word array pointed to by Areg.
Definition:
Areg′ ← Areg @ (2 × Breg)
Breg′
Creg′
← Creg
← undefined
Error signals: none
Comments:
Secondary instruction.
See also: bsub ssub wcnt wsub
200/212
xbword
xbword
sign extend byte to word
Code: 2B F8
Description: Sign-extend the value in the least significant byte of Areg into a signed
integer.
Definition:
Areg′0..7
Areg′8..BitsPerWord-1
← Areg0..7
← Areg7
Error signals: none
Comments:
Secondary instruction.
201/212
xdble
xdble
extend to double
Code: 21 FD
Description: Sign extend the integer in Areg into a double length signed integer.
Definition:
if (Areg ≥ 0)
Breg′ ← 0
else
Breg′ ← −1
Creg′
← Breg
Error signals: none
Comments:
Secondary instruction.
202/212
xor
xor
exclusive or
Code: 23 F3
Description: Bitwise exclusive or of Areg and Breg.
Definition:
Areg′ ← Breg ⊗ Areg
Breg′
Creg′
← Creg
← undefined
Error signals: none
Comments:
Secondary instruction.
203/212
xsword
xsword
sign extend sixteen to word
Code: 2F F8
Description: Sign extend the value in the least significant 16 bits of Areg to a signed
integer.
Definition:
Areg′0..15
Areg′16..BitsPerWord-1
← Areg0..15
← Areg15
Error signals: none
Comments:
Secondary instruction.
See also: xbword
204/212
xword
xword
extend to word
Code: 23 FA
Description: Sign extend an N-bit signed number in Breg into a full word. To indicate
the value of N, bit N-1 of Areg is set to 1; all other bits must be 0.
Definition:
if (Areg is a not power of 2)
Areg′ ← undefined
else if (Areg = MostNeg)
Areg′ ← Breg
else if (Breg ≥ 0) and (Breg < Areg)
Areg′ ← Breg
else if (Breg ≥ Areg) and ((Breg >> 1) < Areg)
Areg′ ← Breg − (Areg << 1)
else
Areg′ ← undefined
Breg′
Creg′
– N is BitsPerWord
– Breg N bits and positive
– Breg N bits and negative
– Breg more than N bits
← Creg
← undefined
Error signals: none
Comments:
Secondary instruction.
See also: xbword xsword
205/212
xword
206/212
Index
addressing, 17
selector, 17
ByteSelectMask, 12
BytesPerWord, 12
Symbols
+ (plus), 15
+checked (plus checked), 15
.. (ellipsis), 8
/ (divide), 15
< (less than), 15
= (equals), 15
> (greater than), 15
@ (word offset), 10
{ } (braces), 15
′ (prime), 10
C
call, 44
causeerror, 45
cb, 46
cbu, 47
ccnt1, 48
cflerr, 49
checked arithmetic, 14
cir, 50
cj, 27, 52
cj n, 27
clockdis, 53
ClockEnables, 22
clockenb, 54
ClockReg0..1, 22
clocks
clock registers, 22
clrhalterr, 55
code
in instruction descriptions, 5
coding of instruction, 5, 25
comments
in instruction descriptions, 5, 7, 8
conditions
in instruction descriptions, 14
configuration registers, 11
constants
machine constant definitions, 13
used in instruction descriptions, 12
conversion
type, 14
crcbyte, 56
crcword, 57
Creg, 20
cs, 58
csngl, 59
csu, 60
csub0, 61
cword, 62
A
adc, 26
add, 33
address
calculation, 10
addressing, 17
after, 15
ajw, 27, 34
alarm registers, 22
alt, 35
altend, 36
altwt, 37
and
boolean operator, 15
instruction, 38
Areg, 20
arithmetic
checked integer, 14
modulo, 13
unchecked integer, 13
B
back pointer registers, 22
bcnt, 39
BITAND, 15
bitcnt, 40
BITNOT, 15
BITOR, 15
bitrevnbits, 41
bitrevword, 42
BitsPerByte, 12
BitsPerWord, 12
BITXOR, 15
BptrReg0..1, 22
Breg, 20
bsub, 43
byte
D
data representation, 17
definition
in instruction descriptions, 5, 6
descheduling points, 7
207/212
Index
description
in instruction descriptions, 5, 6
DeviceId, 13
devlb, 63
devls, 64
devlw, 65
devmove, 66
devsb, 67
devss, 68
devsw, 69
diff, 70
Disabling.p, 13
disc, 71
diss, 73
dist, 74
div, 75
dup, 76
I
identity
of device, 13
if, 14
in, 90
insertqueue, 91
instruction
component, 25
data value, 25
encoding, 5, 25
instructions, 13
intdis, 92
integer length conversion, 18
IntegerError, 7
IntegerOverflow, 7
intenb, 93
interruptible instructions, 7
IptrReg, 20
iret, 94
E
else, 14
Enables, 22
Enabling.p, 13
enbc, 77
enbs, 78
enbt, 79
encoding of instructions, 5, 25
endp, 80
eqc, 27, 81
error signals, 7
in instruction descriptions, 5, 7
ErrorFlag, 23
J
j, 27, 95
L
ladd, 96
lb, 97
lbx, 98
ldc, 27, 99
ldclock, 100
lddevid, 101
values returned, 13
ldiff, 102
ldinf, 103
ldiv, 104
ldl, 27, 105
ldlp, 27, 106
ldmemstartval, 107
ldnl, 27, 108
ldnlp, 27, 109
ldpi, 110
ldpri, 111
ldprodid, 112
values returned, 13
ldshadow, 113
ldtimer, 115
ldtraph, 116
ldtrapped, 117
le.Count, 12
le.Index, 12
lend, 118
little–endian, 17
lmul, 119
ls, 120
lshl, 121
lshr, 122
lsub, 123
F
false, 13
fmul, 82
fptesterr, 83
FptrReg0..1, 22
front pointer registers, 22
function code, 5, 25
functions
in instruction descriptions, 14
G
gajw, 84
gcall, 85
gintdis, 86
gintenb, 87
GlobalInterruptEnables, 22
gt, 88
gtu, 89
H
HaltOnErrorFlag, 23
208/212
Index
lsum, 124
lsx, 125
primary instructions, 7, 25, 26
prime notation
in instruction descriptions, 10
Priority, 20, 22
priority, 8
process
descriptor, 8, 20, 22
priority, 8
process state, 8, 20
in instruction descriptions, 6
prod, 142
product identity, 13
pw.Iptr, 11
pw.Link, 11
pw.Pointer, 11
pw.State, 11
pw.Temp, 11
pw.Time , 11
pw.TLink, 11
M
memory
code, 5
representation of, 9
mint, 126
modulo arithmetic, 13
MostNeg, 12
MostPos, 12
MostPosUnsigned, 12
move, 127
move2dall, 128
move2dinit, 129
move2dnonzero, 130
move2dzero, 131
mul, 132
N
R
next instruction, 9
nfix, 26
NoneSelected.o, 13
nop, 133
norm, 134
not
boolean operator, 15
instruction, 135
NotProcess.p, 13
Ready.p, 13
reboot, 143
registers, 20
in instruction descriptions, 6
other, 22
state, 20
rem
arithmetic operator, 15
instruction, 144
representing memory
in instruction descriptions, 9
resetch, 145
restart, 146
ret, 147
rev, 148
roundsn, 149
runp, 150
O
objects, 9
operands
in instruction descriptions, 5
primary instructions, 26
operate, 25
operation code, 5, 25, 27
operators, 13
in instruction descriptions, 14
opr, 7, 27
or
boolean operator, 15
instruction, 136
out, 137
outbyte, 138
outword, 139
S
s.Back, 12
s.Count, 12
s.Front , 12
satadd, 151
satmul, 152
satsub, 153
saveh , 154
savel, 155
sb, 156
secondary instructions, 7, 25, 27
seterr, 157
sethalterr, 158
settimeslice , 159
shadow
state, 20
shl, 160
shr, 161
P
PeripheralEnd, 12
PeripheralStart, 12
pfix, 26
pop, 140
postnormsn, 141
pp.Count, 12
pp.IptrSucc, 12
prefixing, 25, 28
209/212
Index
sign extension, 18
signal, 162
slmul, 163
special pointer values, 17
ss, 164
ssub, 165
start next process, 8
startp, 166
StatusReg, 20
stclock, 167
sthb, 168
sthf, 169
stl, 27, 170
stlb, 171
stlf, 172
stnl, 27, 173
stoperr, 174
stopp, 175
stshadow, 176
sttimer, 177
sttraph, 178
sttrapped, 179
sub, 180
subscripts
in instruction descriptions, 9
sulmul, 181
sum, 182
swapqueue, 183
swaptimer, 184
unpacksn, 196
unsign(), 14
unsigned, 9
W
wait, 197
Waiting.p, 13
wcnt, 198
Wdesc, 20, 22, 24
word address, 17
WordSelectMask, 12
workspace, 20, 22
address, 8
Wptr, 20, 22, 24
wsub, 199
wsubdb, 200
X
xbword, 201
xdble, 202
xor, 203
xsword, 204
xword, 205
T
talt, 185
taltwt, 186
testerr, 188
testhalterr, 189
testpranal, 190
TimeNotSet.p, 13
timer
list pointer registers, 22
TimeSet.p, 13
timeslice, 191
timeslicing
points, 7
tin, 192
TnextReg0..1, 22
TptrReg0..1, 22
trapdis, 193
TrapEnables, 22
trapenb, 194
tret, 195
true, 13
type conversion, 14
U
unchecked arithmetic, 13
undefined, 9
values, 9
210/212
Index
211/212
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no
responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights
of SGS-THOMSON Microelectronics. Specifications mentioned in this pub lication are subject to change without notice.
This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of
SGS-THOMSON Microelectronics.
1995 SGS-THOMSON Microelectronics - All Rights Reserved
IMS, occam and DS-Link
are trademarks of SGS-THOMSON Microelectronics Limited.
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
Document number: 72-TRN-273-01
212/212