19-1991; Rev 0; 4/01 KIT ATION EVALU E L B A AVAIL Quad LVDS Line Driver Features ♦ Pin Compatible with DS90LV031A ♦ Guaranteed 800Mbps Data Rate ♦ 250ps Maximum Pulse Skew ♦ Conforms to TIA/EIA-644 LVDS Standard ♦ Single +3.3V Supply ♦ 16-Pin TSSOP and SO Packages Ordering Information PART TEMP. RANGE PIN-PACKAGE MAX9124EUE -40°C to +85°C 16 TSSOP MAX9124ESE -40°C to +85°C 16 SO Applications Digital Copiers DSLAMs Laser Printers Network Switches/Routers Cell Phone Base Stations Add/Drop Muxes Backplane Interconnect Digital Cross-Connects Clock Distribution Typical Applications Circuit LVDS SIGNALS MAX9126 MAX9124 Pin Configuration TX 115Ω RX TX 115Ω RX LVTTL/LVCMOS DATA INPUT TOP VIEW IN1 1 16 VCC OUT1+ 2 15 IN4 OUT1- 3 14 OUT4+ EN 4 MAX9124 TX 115Ω RX TX 115Ω RX 13 OUT4- OUT2- 5 12 EN OUT2+ 6 11 OUT3- IN2 7 10 OUT3+ GND 8 LVTTL/LVCMOS DATA OUTPUT 9 IN3 TSSOP/SO 100Ω SHIELDED TWISTED CABLE OR MICROSTRIP PC BOARD TRACES * Future product—contact factory for availability. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9124 General Description The MAX9124 quad low-voltage differential signaling (LVDS) line driver is ideal for applications requiring high data rates, low power, and low noise. The MAX9124 is guaranteed to transmit data at speeds up to 800Mbps (400MHz) over controlled impedance media of approximately 100Ω. The transmission media may be printed circuit (PC) board traces, backplanes, or cables. The MAX9124 accepts four LVTTL/LVCMOS input levels and translates them to LVDS output signals. Moreover, the MAX9124 is capable of setting all four outputs to a high-impedance state through two enable inputs, EN and EN, thus dropping the device to an ultra-low-power state of 16mW (typ) during high impedance. The enables are common to all four transmitters. Outputs conform to the ANSI TIA/EIA-644 LVDS standard. The MAX9124 operates from a single +3.3V supply and is specified for operation from -40°C to +85°C. It is available in 16-pin TSSOP and SO packages. Refer to the MAX9125/ MAX9126 data sheet for quad LVDS line receivers. MAX9124 Quad LVDS Line Driver ABSOLUTE MAXIMUM RATINGS VCC to GND ...........................................................-0.3V to +4.0V IN_, EN, EN to GND....................................-0.3V to (VCC + 0.3V) OUT_+, OUT_- to GND..........................................-0.3V to +3.9V Short-Circuit Duration (OUT_+, OUT_-) .....................Continuous Continuous Power Dissipation (TA = +70°C) 16-Pin TSSOP (derate 9.4mW/°C above +70°C) .........755mW 16-Pin SO (derate 8.7mW/°C above +70°C)................696mW Storage Temperature Range .............................-65°C to +150°C Maximum Junction Temperature .....................................+150°C Operating Temperature Range ...........................-40°C to +85°C Lead Temperature (soldering, 10s) .................................+300°C ESD Protection Human Body Model, OUT_+, OUT_- ..............................±6kV Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, RL = 100Ω ±1%, TA = -40°C to +85°C. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 250 368 450 mV 1 25 mV 1.25 1.375 V 4 25 mV LVDS OUTPUT (OUT_+, OUT_-) Differential Output Voltage VOD Figure 1 ∆VOD Figure 1 VOS Figure 1 Change in Magnitude of VOS Between Complementary Output States ∆VOS Figure 1 Output High Voltage VOH Output Low Voltage VOL Differential Output Short-Circuit Current (Note 3) IOSD Change in Magnitude of VOD Between Complementary Output States Offset Voltage 1.125 1.6 0.90 V V Enabled, VOD = 0 -9 mA -9 mA Output Short-Circuit Current IOS OUT_+ = 0 at IN_ = VCC or OUT_- = 0 at IN_ = 0, enabled Output High-Impedance Current IOZ EN = low and EN = high, OUT_+ = 0 or VCC, OUT_- = 0 or VCC , RL = ∞ -10 10 µA Power-Off Output Current IOFF VCC = 0 or open, OUT_+ = 0 or 3.6V, OUT_= 0 or 3.6V, RL = ∞ -10 10 µA -3.8 INPUTS (IN_, EN, EN) High-Level Input Voltage VIH 2.0 VCC V Low-Level Input Voltage VIL GND 0.8 V Input Current IIN IN_, EN, EN = 0 or VCC -20 20 µA No-Load Supply Current ICC RL = ∞, IN_ = VCC or 0 for all channels 9.2 11 mA Loaded Supply Current ICCL 22.7 30 mA Disabled Supply Current ICCZ RL = 100Ω, IN_ = VCC or 0 for all channels Disabled, IN_ = VCC or 0 for all channels, EN = 0, EN = VCC 4.9 6 mA SUPPLY CURRENT 2 _______________________________________________________________________________________ Quad LVDS Line Driver (VCC = +3.0V to +3.6V, RL = 100Ω ±1%, CL = 10pF, TA = -40°C to +85°C. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Notes 4, 5, 6) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Differential Propagation Delay High to Low tPHLD Figures 2 and 3 0.8 1.42 2.0 ns Differential Propagation Delay Low to High tPLHD Figures 2 and 3 0.8 1.44 2.0 ns Differential Pulse Skew (Note 7) tSKD1 Figures 2 and 3 0.02 0.25 ns Differential Channel-to-Channel Skew (Note 8) tSKD2 Figures 2 and 3 0.35 ns Differential Part-to-Part Skew (Note 9) tSKD3 Figures 2 and 3 0.8 ns Differential Part-to-Part Skew (Note 10) tSKD4 1.2 ns ns Rise Time Figures 2 and 3 tTLH Figures 2 and 3 0.1 0.35 0.7 Fall Time tTHL Figures 2 and 3 0.1 0.35 0.7 ns Disable Time High to Z tPHZ Figures 4 and 5 5 ns Disable Time Low to Z tPLZ Figures 4 and 5 5 ns Enable Time Z to High tPZH Figures 4 and 5 5 ns Enable Time Z to Low tPZL Figures 4 and 5 5 ns Maximum Operating Frequency (Note 11) fMAX 400 MHz Note 1: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are 100% tested at TA = +25°C. Note 2: Currents into the device are positive, and current out of the device is negative. All voltages are referenced to ground except VOD. Note 3: Guaranteed by correlation data. Note 4: AC parameters are guaranteed by design and characterization. Note 5: CL includes probe and jig capacitance. Note 6: Signal generator conditions for dynamic tests: VOL = 0, VOH = 3V, f = 100MHz, 50% duty cycle, RO = 50Ω, tR ≤ 1ns, tF ≤ 1ns (0% to 100%). Note 7: tSKD1 is the magnitude difference of differential propagation delay. tSKD1 = |tPHLD - tPLHD|. Note 8: tSKD2 is the magnitude difference of tPHLD or tPLHD of one channel to the tPHLD or tPLHD of another channel on the same device. Note 9: tSKD3 is the magnitude difference of any differential propagation delays between devices at the same VCC and within 5°C of each other. Note 10: tSKD4 is the magnitude difference of any differential propagation delays between devices operating over the rated supply and temperature ranges. Note 11: fMAX signal generator conditions: VOL = 0, VOH = 3V, f = 400MHz, 50% duty cycle, RO = 50Ω, tR ≤ 1ns, tF ≤ 1ns (0% to 100%). Transmitter output criteria: duty cycle = 45% to 55%, VOD ≥ 250mV. _______________________________________________________________________________________ 3 MAX9124 SWITCHING CHARACTERISTICS Typical Operating Characteristics (TA = +25°C) SINGLE-ENDED OUTPUT VOLTAGE vs. LOAD RESISTANCE (RL = 50Ω TO 400Ω) 1.70 OUT_+ 1.50 VCC = +3.6V _VCC = +3.0V 1.30 1.10 0.90 OUT_- 0.70 0.50 0.30 50 100 150 200 250 300 350 400 RL (Ω) MAX9124 toc02 1.90 SINGLE-ENDED OUTPUT VOLTAGE (V) SINGLE-ENDED OUTPUT VOLTAGE vs. LOAD RESISTANCE (RL = 0 TO 7kΩ) MAX9124 toc01 2.10 SINGLE-ENDED OUTPUT VOLTAGE (V) MAX9124 Quad LVDS Line Driver 2.40 2.20 2.00 1.80 1.60 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0 DOUT+ VCC = +3.6V _VCC = +3.0V DOUT0 1000 2000 3000 4000 5000 6000 7000 RL (Ω) Pin Description 4 PIN NAME FUNCTION 1, 7, 9, 15 IN_ 2, 6, 10, 14 OUT_+ Noninverting LVDS Driver Outputs 3, 5, 11, 13 OUT_- Inverting LVDS Driver Outputs 4, 12 EN, EN Driver Enable Inputs. The driver is disabled and in high impedance when EN is low and EN is high. For other combinations of EN and EN, the outputs are active. 8 GND Ground 16 VCC Power-Supply Input. Bypass VCC to GND with 0.1µF and 0.001µF ceramic capacitors. LVTTL/LVCMOS Driver Inputs _______________________________________________________________________________________ Quad LVDS Line Driver The MAX9124 is an 800Mbps quad differential LVDS driver that is designed for high-speed, point-to-point, and low-power applications. This device accepts LVTTL/LVCMOS input levels and translates them to LVDS output signals. The MAX9124 generates a 2.5mA to 4.0mA output current using a current-steering configuration. This currentsteering approach induces less ground bounce and no shoot-through current, enhancing noise margin and system speed performance. The driver outputs are shortcircuit current limited and enter a high-impedance state when the device is not powered or is disabled. The current-steering architecture of the MAX9124 requires a resistive load to terminate the signal and complete the transmission loop. Because the device switches current and not voltage, the actual output voltage swing is determined by the value of the termination resistor at the input of an LVDS receiver. Logic states are determined by the direction of current flow through the termination resistor. With a typical 3.7mA output current, the MAX9124 produces an output voltage of 370mV when driving a 100Ω load. Termination Because the MAX9124 is a current-steering device, no output voltage will be generated without a termination resistor. The termination resistors should match the differential impedance of the transmission line. Output voltage levels depend upon the value of the termination resistor. The MAX9124 is optimized for point-to-point interface with 100Ω termination resistors at the receiver inputs. Termination resistance values may range between 90Ω and 132Ω, depending on the characteristic impedance of the transmission medium. Applications Information Power-Supply Bypassing Table 1. Input/Output Function Table ENABLES INPUTS OUTPUTS EN EN IN_ OUT_+ L H X Z Z L L H H H L All other combinations of ENABLE inputs OUT_ - close to the device as possible, with the smaller valued capacitor closest to VCC. Differential Traces Output trace characteristics affect the performance of the MAX9124. Use controlled-impedance traces to match trace impedance to the transmission medium. Eliminate reflections and ensure that noise couples as common mode by running the differential trace pairs close together. Reduce skew by matching the electrical length of the traces. Excessive skew can result in a degradation of magnetic field cancellation. Maintain the distance between the differential traces to avoid discontinuities in differential impedance. Avoid 90° turns and minimize the number of vias to further prevent impedance discontinuities. Cables and Connectors Transmission media should have a nominal differential impedance of 100Ω. To minimize impedance discontinuities, use cables and connectors that have matched differential impedance. Avoid the use of unbalanced cables such as ribbon or simple coaxial cable. Balanced cables, such as twisted pair, offer superior signal quality and tend to generate less EMI due to canceling effects. Balanced cables tend to pick up noise as common mode, which is rejected by the LVDS receiver. Board Layout For LVDS applications, a four-layer PC board that provides separate power, ground, LVDS signals, and input signals is recommended. Isolate the LVTTL/LVCMOS and LVDS signals from each other to prevent coupling. Chip Information TRANSISTOR COUNT: 2007 PROCESS: CMOS Bypass V CC with high-frequency, surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel as _______________________________________________________________________________________ 5 MAX9124 Detailed Description The LVDS interface standard is a signaling method intended for point-to-point communication over a controlled-impedance medium as defined by the ANSI/TIA/EIA-644 and IEEE 1596.3 standards. The LVDS standard uses a lower voltage swing than other common communication standards, achieving higher data rates with reduced power consumption while reducing EMI emissions and system susceptibility to noise. MAX9124 Quad LVDS Line Driver CL OUT_+ OUT_ + RL/2 VCC IN_ VOD VO GND IN_ GENERATOR S VOS RL/2 RL OUT_ - 50Ω CL OUT_- Figure 2. Driver Propagation Delay and Transition Time Test Circuit Figure 1. Driver VOD and VOS Test Circuit 3V IN_ 1.5V 1.5V tPLHD tPHLD 0 OUT_ - VOH 0 DIFFERENTIAL 0 OUT_+ VOL 80% VDIFF 80% VDIFF = (VOUT_+) - (VOUT_-) 0 50% 20% 0 20% tTLH tTHL Figure 3. Driver Propagation Delay and Transition Time Waveforms CL OUT_+ VCC IN_ RL/2 GND +1.2V EN GENERATOR RL/2 EN 50Ω OUT_1/4 MAX9124 CL Figure 4. Driver High-Impedance Delay Test Circuit 6 _______________________________________________________________________________________ Quad LVDS Line Driver MAX9124 3V EN WHEN EN = VCC 1.5V 1.5V 0 3V 1.5V 1.5V 0 EN WHEN EN = 0 tPZH tPHZ OUT_+ WHEN IN_ = VCC OUT_- WHEN IN_ = 0 VOH 50% 50% 1.2V 1.2V 50% OUT_+ WHEN IN_ = 0 OUT_- WHEN IN_ = VCC 50% VOL tPLZ tPZL Figure 5. Driver High-Impedance Delay Waveform Functional Diagram OUT1+ IN1 OUT1- OUT2+ IN2 OUT2- OUT3+ IN3 OUT3- OUT4+ IN4 OUT4- EN EN _______________________________________________________________________________________ 7 Quad LVDS Line Driver TSSOP,NO PADS.EPS MAX9124 Package Information 8 _______________________________________________________________________________________ Quad LVDS Line Driver SOICN.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9 © 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX9124 Package Information (continued)