a u s t ri a m i c r o s y s t e m s D a ta S he e t A S 11 5 2 Q u a d LV D S D r i v e r 1 General Description 2 Key Features The AS1152 is a Quad Flow-Through LVDS (Low-Voltage Differential Signaling) Line Driver which accepts and converts LVTTL/LVCMOS input levels into LVDS output signals. The device is perfect for low-power lownoise applications requiring high signaling rates and reduced EMI emissions. ! Flow-Through Pinout ! Guaranteed 500Mbps Data Rate (paired with AS1150) ! 350ps Pulse Skew (Max) The device is guaranteed to transmit data at speeds up to 500Mbps (250MHz) over controlled impedance media of approximately 100Ω. Supported transmission media are PCB traces, backplanes, and cables. ! Conforms to ANSI TIA/EIA-644 LVDS Standards ! Single +3.3V Supply ! Operating Temperature Range: -40 to +85°C ! 16-Pin TSSOP Package The AS1152 is capable of setting all four outputs to a high-impedance state through two Enable Inputs (EN and ENn – internally pulled down to GND), dropping the device to an ultra-low-power state of 16mW (typical) during high impedance. The Enable Inputs are common to all four drivers. 3 Applications Digital Copiers, Laser Printers, Cellular Phone Base Stations, Add/Drop Muxes, Digital Cross-Connects, DSLAMs, Network Switches/Routers, Backplane Interconnect, Clock Distribution Computers, Intelligent Instruments, Controllers, Critical Microprocessors and Microcontrollers, Power Monitoring, and Portable/Battery-Powered Equipment. Outputs conform to the ANSI TIA/EIA-644 LVDS standards. Flow-through pinout simplifies PC board layout and reduces crosstalk by separating the LVTTL/LVCMOS inputs and LVDS outputs. The AS1152 operates from a single +3.3V supply and is specified for operation from -40 to +85°C. Figure 1. Block Diagram VCC OUT1+ IN1 OUT1- OUT2+ IN2 OUT2- OUT3+ IN3 OUT3- OUT4+ IN4 OUT4- EN ENn AS1152 www.austriamicrosystems.com Revision 1.00 1 - 15 austriam i c r o systems AS1152 Data Sheet 4 Absolute Maximum Ratings Stresses beyond those listed in Table 1 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 1. Absolute Maximum Ratings Parameter Limits Units VCC to GND -0.3 to +5.0 V INx, EN, ENn to GND -0.3 to (VCC + 0.3) V OUTx+, OUTx- to GND -0.3 to +5 V Short Circuit Duration (OUTx+, OUTx-) Continuous Continuous Power Dissipation (TA = +70°C) 755 mW Storage Temperature Range -65 to +150 ºC Maximum Junction Temperature +150 ºC Operating Temperature Range -40 to +85 ºC Notes Derate 9.4mW/°C Above +70°C Package Body Temperature 260 ºC The reflow peak soldering temperature (body temperature) specified is in compliance with IPC/ JEDEC J-STD-020C “Moisture/ Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices”. ESD Protection ±4 kV Human Body Model, INx, OUTx+, OUTx-- www.austriamicrosystems.com Revision 1.00 2 - 15 austriam i c r o systems AS1152 Data Sheet DC Electrical Characteristics 5 Electrical Characteristics DC Electrical Characteristics (VCC = +3.0 to +3.6V, TA = -40 to +85°C , RL = 100Ω, f ≤ 150Mhz Typical values are at VCC = +3.3V, TA = +25°C, Unless Otherwise Noted.)1, 2 Table 2. DC Electrical Characteristics Parameter Symbol Conditions Min Typ Max Unit Differential Output Voltage VOD Figure 20 on page 12 250 370 450 mV Change in Magnitude of VOD Between Complementary Output States ∆VOD Figure 20 on page 12 1 35 mV Offset Voltage VOS Figure 20 on page 12 1.25 1.375 V Change in Magnitude of VOS Between Complementary Output States ∆VOS Figure 20 on page 12 4 25 mV Output High Voltage VOH 1.6 V Output Low Voltage VOL Differential Output Short-Circuit Current 3 IOSD Enabled, VOD = 0 Output Short-Circuit Current IOS OUTx+ = 0 at INx = VCC or OUTx- = 0 at INx = 0, enabled Output High-Impedance Current IOZ EN = low and ENn = high, OUTx+ = 0 or VCC, OUTx- = 0 or VCC, RL = ∞ Power-Off Output Current IOFF VCC = 0 or open, OUTx+ = 0 or 3.6V, OUTx- = 0 or 3.6V, RL = ∞ LVDS Output (OUtx+, OUTx-) 1.125 0.90 V -9 mA -9 mA -10 10 µA -20 20 µA -3.8 Inputs (INx, EN, ENn) High-Level Input Voltage VIH 2.0 VCC V Low-Level Input Voltage VIL GND 0.8 V Input Current IIN INx, EN, ENn = 0 or VCC -20 20 µA No-Load Supply Current ICC RL = ∞ , INx = VCC or 0 for all channels 4 6 mA Loaded Supply Current ICCL RL = 100Ω, INx = VCC or 0 for all channels 18 25 mA Disabled Supply Current ICCZ Disabled, INx = VCC or 0 for all channels, EN = 0, ENn = VCC 3.5 5.5 mA Supply Current Notes: 1. Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are 100% tested at TA = +25°C. 2. Currents into the device are positive, and current out of the device is negative. All voltages are referenced to ground except VOD. 3. Guaranteed by correlation data. www.austriamicrosystems.com Revision 1.00 3 - 15 austriam i c r o systems AS1152 Data Sheet Switching Characteristics Switching Characteristics (VCC = +3.0 to +3.6V, RL = 100Ω ±1%, f ≤ 150MHz, TA = -40 to +85°C Typical values are at VCC = +3.3V, TA = +25ºC, Unless Otherwise Noted.) 1, 2, 3 Table 3. Switching Characteristics Parameter Symbol Conditions Min Differential Propagation Delay, High-to-Low tPHLD Figure 18 on page 11 and Figure 19 on page 11 Differential Propagation Delay, Low-to-High tPLHD Figure 18 on page 11 and Figure 19 on page 11 Differential Pulse Skew 4 tSKD1 Figure 18 on page 11 and Figure 19 on page 11 Differential Channel-to-Channel Skew 5 tSKD2 Differential Part-to-Part Skew 6 Max Unit 1.1 1.7 ns 1.1 1.7 ns 0.04 0.35 ns Figure 18 on page 11 and Figure 19 on page 11 0.07 0.60 ns tSKD3 Figure 18 on page 11 and Figure 19 on page 11 0.13 0.8 ns Differential Part-to-Part Skew 7 tSKD4 Figure 18 on page 11 and Figure 19 on page 11 0.43 1.0 ns Rise Time tTLH Figure 18 on page 11 and Figure 19 on page 11 0.2 0.39 2.6 ns Fall Time tTHL Figure 18 on page 11 and Figure 19 on page 11 0.2 0.39 2.6 ns Disable Time, High-to-Z tPHZ Figure 21 on page 12 and Figure 22 on page 12 3 4 ns Disable Time, Low-to-Z tPLZ Figure 21 on page 12 and Figure 22 on page 12 3 4 ns Enable Time, Z-to-High tPZH Figure 21 on page 12 and Figure 22 on page 12 2 3 ns Enable Time, Z-to-Low tPZL Figure 21 on page 12 and Figure 22 on page 12 2 3 ns Maximum Operating Frequency 8, 9 fMAX 250 Typ MHz Notes: 1. Parameters are guaranteed by design and characterization. 2. CL includes probe and jig capacitance. 3. Signal generator conditions for dynamic tests: VOL = 0, VOH = 3V, f = 100MHz, 50% duty cycle, RO = 50Ω, tR ≤ 1ns, tF ≤ 1ns (0 to 100%). 4. tSKD1 is the magnitude difference of differential propagation delay. tSKD1 = |tPHLD - tPLHD|. 5. tSKD2 is the magnitude difference of tPHLD or tPLHD of one channel to the tPHLD or tPLHD of another channel on the same device. 6. tSKD3 is the magnitude difference of any differential propagation delays between devices at the same VCC and within 5°C of each other. 7. tSKD4 is the magnitude difference of any differential propagation delays between devices operating over the rated supply and temperature ranges. 8. fMAX signal generator conditions: VOL = 0, VOH = 3V, 50% duty cycle, RO = 50Ω, tR ≤ 1ns, tF ≤ 1ns (0 to 100%). 9. Conforms to ANSI TIA/EIA 644 LVDS Standards ≤150MHz. Maximum operating frequency of 250MHz is possible using an AS1150 receiver. www.austriamicrosystems.com Revision 1.00 4 - 15 austriam i c r o systems AS1152 Data Sheet Switching Characteristics 6 Typical Operating Characteristics VCC = +3.3V, VCM = +1.2V, |VID| = 0.2V, CLOAD = 15pF, Tamb = +25ºC, unless otherwise noted Figure 3. Output Low Voltage vs. VCC Figure 2. Output High Voltage vs. VCC 1.08 Output Low Voltage (V) . Output High Voltage (V) . 1.41 1.408 VOUT+ 1.406 VOUT- 1.404 1.402 1.4 1.075 VOUT- 1.07 VOUT+ 1.065 1.06 3 3.1 3.2 3.3 3.4 3.5 3 3.6 3.1 Power-Supply Voltage (V) 3.2 3.3 3.4 3.5 3.6 Power-Supply Voltage (V) Figure 4. Output Short-Circuit Current vs. VCC; VIN = VCC or GND Figure 5. Output High-Impedance State Current vs. VCC; VIN = VCC or GND 30 Output High-Z State Current (µA) . Output Short-Circuit Current (mA) . 3.700 3.675 29 3.650 28 3.625 3.600 27 3.575 26 3.550 25 3.525 3.500 24 3 3.1 3.2 3.3 3.4 3.5 3.6 3 Power-Supply Voltage (V) 3.1 3.2 3.3 3.4 3.5 3.6 Power-Supply Voltage (V) Figure 6. Differential Output Voltage vs. VCC Figure 7. Differential Output Voltage vs. Load Resistor 500 Differential Output Voltage (mV) Differential Output Voltage (V) . . 350 345 340 335 330 325 320 3 3.1 3.2 3.3 3.4 3.5 450 400 350 300 250 3.6 90 Power-Supply Voltage (V) www.austriamicrosystems.com 100 110 120 130 140 150 Load Resistor (Ohm) Revision 1.00 5 - 15 austriam i c r o systems AS1152 Data Sheet Switching Characteristics Figure 8. Offset Voltage vs. VCC Figure 9. Power Supply Current vs. Frequency; VIN = 0 to 3V 1.244 Power-Supply Current (mA) Offset Voltage (V) . . 60 1.243 1.242 1.241 1.24 50 40 30 All Channels 20 One Channels 10 3 3.1 3.2 3.3 3.4 3.5 3.6 0.1 1 Power-Supply Voltage (V) Figure 10. ICC vs. VCC; Freq = 1MHz 1000 . 22 . 19.25 Power-Supply Current (mA) Power-Supply Current (mA) 100 Figure 11. ICC vs. Temperature; Freq = 1MHz 19.5 19 18.75 18.5 18.25 18 3 3.1 3.2 3.3 3.4 3.5 21 20 19 18 17 -50 3.6 -30 Power-Supply Voltage (V) -10 10 30 50 70 90 Temperature(°C) Figure 12. Differential Propagation Delay vs. VCC; Freq = 1MHz Figure 13. Differential Propagation Delay vs. Temperature; Freq = 1MHz Diff. Propagation Delay (ns) . 1.6 . 1.6 Diff. Propagation Delay (ns) 10 Frequency (MHz) 1.5 1.4 tPHLD 1.3 tPLHD 1.2 1.1 3 3.1 3.2 3.3 3.4 3.5 3.6 1.5 tPHLD 1.4 1.2 1.1 -50 Power-Supply Voltage (V) www.austriamicrosystems.com tPLHD 1.3 -30 -10 10 30 50 70 90 Temperature (°C) Revision 1.00 6 - 15 austriam i c r o systems AS1152 Data Sheet Switching Characteristics Figure 14. Differential Skew vs. VCC; Freq = 1MHz Figure 15. Differential Skew vs. Temperature; Freq = 1MHz . 150 120 Diff. Pulse Skew (ps) Diff. Pulse Skew (ps) . 150 90 60 30 0 3 3.1 3.2 3.3 3.4 3.5 3.6 120 90 60 30 0 -50 Power Supply Voltage (V) www.austriamicrosystems.com -30 -10 10 30 50 70 90 Temperature (°C) Revision 1.00 7 - 15 austriam i c r o systems AS1152 Data Sheet Pin Assignments 7 Pinout and Packaging Pin Assignments Figure 16. AS1152 Pin Assignments (Top View) EN 1 16 OUT1- IN1 2 15 OUT1+ IN2 3 14 OUT2+ VCC 4 13 OUT2- GND 5 12 OUT3- IN3 6 11 OUT3+ IN4 7 10 OUT4+ ENn 8 9 OUT4- AS1152 TSSOP Pin Descriptions Table 4. AS1152 Pin Descriptions Pin Number Pin Name Description 1 EN Driver Enable Input. Internally pulled down to GND. When EN = high and ENn = low or open, the driver outputs are active. For other combinations of EN and ENn, the outputs are disabled and in high impedance. 2 IN1 LVTTL/LVCMOS Driver Input 3 IN2 LVTTL/LVCMOS Driver Input 4 VCC Power Supply Input. Bypass VCC to GND with 0.1µF and 0.001µF ceramic capacitors. 5 GND Ground 6 IN3 LVTTL/LVCMOS Driver Input 7 IN4 LVTTL/LVCMOS Driver Input 8 ENn Driver Enable Input. Internally pulled down to GND. When EN = high and ENn = low or open, the driver outputs are active. For other combinations of EN and ENn, the outputs are disabled and in high impedance. 9 OUT4- Inverting LVDS Driver Output 10 OUT4+ Noninverting LVDS Driver Output 11 OUT3+ Noninverting LVDS Driver Output 12 OUT3- Inverting LVDS Driver Output 13 OUT2- Inverting LVDS Driver Output 14 OUT2+ Noninverting LVDS Driver Output 15 OUT1+ Noninverting LVDS Driver Output 16 OUT1- Inverting LVDS Driver Output www.austriamicrosystems.com Revision 1.00 8 - 15 austriam i c r o systems AS1152 Data Sheet LVDS Interface 8 Detailed Description LVDS Interface The LVDS interface standard is a signaling method intended for point-to-point communication over a controlled-impedance medium as defined by the ANSI/TIA/EIA-644 and IEEE 1596.3 standards. The LVDS standard uses a lower voltage swing than other common communication standards, achieving higher data rates with reduced power consumption while reducing EMI emissions and system susceptibility to noise. The AS1152 is an 500Mbps quad differential LVDS driver that is designed for high-speed, point-to-point, low-power applications. This device accepts LVTTL/LVCMOS input levels and translates them to LVDS output signals. The AS1152 generates a 2.5mA to 4.5mA output current using a current-steering configuration. This current steering approach induces less ground bounce and no shoot-through current, enhancing noise margin and system speed performance. The driver outputs are short-circuit current limited, and enter a high-impedance state when the device is not powered or is disabled. The current-steering architecture of the AS1152 requires a resistive load to terminate the signal and complete the transmission loop. Because the device switches current and not voltage, the actual output voltage swing is determined by the value of the termination resistor at the input of an LVDS receiver (AS1150, AS1151). Logic states are determined by the direction of current flow through the termination resistor. With a typical 3.7mA output current, the AS1152 produces an output voltage of 370mV when driving a 100Ω load. Note: The AS1152 is conform to the ANSI TIA/EIA 644 LVDS Standards when operating ≤150MHz. Paired with the AS1150 the datarate can be increased to 500Mbps. While operating faster then 150MHz, the rise and fall time, as well as the setup and hold time are not conform to the ANSI TIA/EIA 644 LVDS Standards. Termination Because the AS1152 is a current-steering device, no output voltage will be generated without a termination resistor. The termination resistors should match the differential impedance of the transmission line. Output voltage levels depend upon the value of the termination resistor. The AS1152 is optimized for point-to-point interface with 100Ω termination resistors at the receiver inputs. Termination resistance values may range between 90 and132Ω, depending on the characteristic impedance of the transmission medium. www.austriamicrosystems.com Revision 1.00 9 - 15 austriam i c r o systems AS1152 Data Sheet Power-Supply Bypassing 9 Applications Table 5. Function Table Enable Pins Input Output EN ENn INx+ INx- OUTx H L or Open L L H H L or Open H H L Don’t Care Z Z Other Combinations of Enable Pin Settings Figure 17. Typical Application Circuit LVDS Signals Tx 107Ω Rx Tx 107Ω Rx LVTTL/LVCMOS Data Inputs LVTTL/LVCMOS Data Outputs Tx 107Ω Rx Tx 107Ω Rx AS1151 AS1152 Quad LVDS Receiver 100Ω Shielded Twisted Cable or Microstrip PC Board Traces Power-Supply Bypassing To bypass VCC, use high-frequency surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to pin VCC. Differential Traces Input trace characteristics can adversely affect the performance of the AS1152. ! Use controlled-impedance PC board traces to match the cable characteristic impedance. The termination resistor is also matched to this characteristic impedance. ! Eliminate reflections and ensure that noise couples as common mode by running the differential traces near each other. ! Reduce skew by using matched trace lengths. Tight skew control is required to minimize emissions and proper data recovery of the devices. ! Route each channel’s differential signals very close to each other for optimal cancellation of their respective external magnetic fields. Use a constant distance between the differential traces to avoid irregularities in differential impedance. ! Avoid 90° turns (use two 45° turns). ! Minimize the number of vias to further prevent impedance irregularities. www.austriamicrosystems.com Revision 1.00 10 - 15 austriam i c r o systems AS1152 Data Sheet Cables and Connectors Supported transmission media include printed circuit board traces, backplanes, and cables. ! Use cables and connectors with matched differential impedance (typically 100Ω) to minimize impedance mismatches. ! Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver. ! Avoid the use of unbalanced cables such as ribbon cable or simple coaxial cable. Board Layout The device should be placed as close to the interface connector as possible to minimize LVDS trace length. ! Keep the LVDS and any other digital signals separated from each other to reduce crosstalk. ! Use a four-layer PC board that provides separate power, ground, LVDS signals, and input signals. ! Isolate the input LVDS signals from each other and the output LVCMOS/LVTTL signals from each other to prevent coupling. ! Separate the input LVDS signals from the output signals planes with the power and ground planes for best results. Figure 18. Driver Propagation Delay and Transition Time Waveforms 1.5V 1.5V tPLHD tPHLD INx VOH OUTx0 Differential 0 OUTx+ VOL 80% 0 80% VDIFF = (VOUTx+) - (VOUTx-) 0 20% 20% tTLH tTHL Figure 19. Driver Propagation Delay and Transition Time Test Circuit OUTx+ Generator INx RL 50Ω OUTx- www.austriamicrosystems.com Revision 1.00 11 - 15 austriam i c r o systems AS1152 Data Sheet Figure 20. Driver VOD and VOS Test Circuit OUTx+ RL/2 VCC INx VOS VOD GND RL/2 OUTx- Figure 21. Driver High Impedance Delay Waveforms 3V EN when ENn = 0 or Open 1.5V 1.5V 0 3V 1.5V 1.5V 0 ENn when EN = VCC tPZH tPHZ OUTx+ When INx = VCC OUTx- When INx = 0 VOH 50% 50% 1.2V 1.2V 50% 50% OUTx+ When INx = 0 OUTx- When INx = VCC VOL tPZL tPLZ Figure 22. Driver High-Impedance Delay Test Circuit OUTx+ RL/2 VCC INx GND +1.2V RL/2 Generator EN OUTx50Ω ENn 1/4 AS1152 www.austriamicrosystems.com Revision 1.00 12 - 15 austriam i c r o systems AS1152 Data Sheet Board Layout 10 Package Drawings and Markings Figure 23. 16-pin TSSOP Package Notes: 1. All dimensions are in millimeters; angles in degrees. 2. Dimensioning and tolerancing per ASME Y14.5M – 1994. 3. Dimension D does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, and gate burrs shall not exceed 0.15mm per side. 4. Dimension E1 does not include interlead flash or protrusion. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. 6. Terminal numbers are for reference only. 7. Datums A and B to be determined at datum plane H. 8. Dimensions D and E1 are to be determined at datum plane H. 9. This dimension applies only to variations with an even number of leads per side. 10. Cross section A-A to be determined at 0.10 to 0.25mm from the leadtip. Symbol A A1 A2 L R R1 b b1 c c1 θ1 L1 aaa bbb ccc ddd e θ2 θ3 D E1 E e N www.austriamicrosystems.com Revision 1.00 Min 0.05 0.85 0.50 0.09 0.09 0.19 0.19 0.09 0.09 0º Typ 0.90 0.60 0.22 1.0REF 0.10 0.10 0.05 0.20 0.65BSC 12ºREF 12ºREF Variations 4.90 5.00 4.30 4.40 6.4BSC 0.65BSC 16 Max 1.10 0.15 0.95 0.75 0.30 0.25 0.20 0.16 8º Notes 1,2 1,2 1,2 1,2 1,2 1,2 1,2,5 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 5.10 4.50 1,2,3,8 1,2,4,8 1,2 1,2 1,2,6 13 - 15 austriam i c r o systems AS1152 Data Sheet Board Layout 11 Ordering Information Part Number Description Package Type Delivery Form AS1152 Quad low-voltage differential signaling driver 16-pin TSSOP Tube AS1152-T Quad low-voltage differential signaling driver 16-pin TSSOP Tape and Reel www.austriamicrosystems.com Revision 1.00 14 - 15 austriam i c r o systems AS1152 Data Sheet Board Layout Copyrights Copyright © 1997-2005, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG A-8141 Schloss Premstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com a u s t r i am i c r o s y s t e m s www.austriamicrosystems.com – a leap ahead in mixed signal Revision 1.00 15 - 15