19-2757; Rev 0; 1/03 670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers Features ♦ 1.0ps(RMS) Jitter (max) at 670MHz The MAX9176 has fail-safe LVDS inputs and an LVDS output. The MAX9177 has “anything” differential inputs (CML/LVDS/LVPECL) and an LVDS output. The output can be put into high impedance using the power-down input. The MAX9176 features fail-safe circuits that drive the output high when a selected input is open, undriven and shorted, or undriven and terminated. The MAX9177 has bias circuits that force the output high when a selected input is open. The mux select and powerdown inputs are compatible with standard LVTTL/ LVCMOS logic. ♦ Anything Inputs (MAX9177) Accept CML/LVDS/LVPECL The select and power-down inputs tolerate undershoot of -1V and overshoot of V CC + 1V. The MAX9176/ MAX9177 are available in 10-pin µMAX and 10-lead thin QFN packages, and operate from a single 3.3V supply over the -40°C to +85°C temperature range. ♦ 68ps(P-P) Jitter at 800Mbps Data Rate ♦ 3.3V Supply ♦ LVDS Fail-Safe Inputs (MAX9176) ♦ Select and Power-Down Inputs Tolerate -1.0V and VCC + 1.0V ♦ Low-Power CMOS Design ♦ 10-Lead µMAX and QFN Packages ♦ -40°C to +85°C Operating Temperature Range ♦ Conform to ANSI TIA/EIA-644 LVDS Standard ♦ IEC61000-4-2 Level 4 ESD Rating Applications Protection Switching Ordering Information TEMP RANGE PIN-PACKAGE Loopback MAX9176EUB PART -40°C to +85°C 10 µMAX Clock Distribution MAX9176ETB* -40°C to +85°C 10 Thin QFN-EP** MAX9177EUB -40°C to +85°C 10 µMAX MAX9177ETB* -40°C to +85°C 10 Thin QFN-EP** Functional Diagram appears at end of data sheet. *Future product—contact factory for availability. **EP = Exposed paddle. Pin Configurations TOP VIEW IN0+ 1 INO- 2 GND 3 IN1+ 4 IN1- 10 OUT+ MAX9176 5 9 OUT- INO- 2 8 VCC GND 3 7 PD IN1+ SEL IN1- 6 µMAX IN0+ 1 10 OUT+ 9 OUT- 8 VCC 4 7 PD 5 6 SEL EXPOSED PAD QFN (LEADS UNDER PACKAGE) ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9176/MAX9177 General Description The MAX9176/MAX9177 are 670MHz, low-jitter, lowskew 2:1 multiplexers ideal for protection switching, loopback, and clock distribution. The devices feature ultra-low 68ps peak-to-peak deterministic jitter that ensures reliable operation in high-speed links that are highly sensitive to timing errors. MAX9176/MAX9177 670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers ABSOLUTE MAXIMUM RATINGS VCC to GND ...........................................................-0.3V to +4.0V IN_+, IN_- to GND .................................................-0.3V to +4.0V OUT+, OUT- to GND .............................................-0.3V to +4.0V PD, SEL to GND .........................................-1.4V to (VCC + 1.4V) Single-Ended and Differential Output Short-Circuit Duration (OUT+, OUT-) ......................Continuous Continuous Power Dissipation (TA = +70°C) 10-Pin µMAX (derate 5.6mW/°C above +70°C) ............444mW 10-Lead Thin QFN (derate 24.4mW/°C above +70°C)..1951mW Operating Temperature Range ...........................-40°C to +85°C Maximum Junction Temperature .....................................+150°C Storage Temperature Range .............................-65°C to +150°C ESD Protection Human Body Model (RD = 1.5kΩ, CS = 100pF) (IN_+, IN_-, OUT+, OUT-) ...............................................+16kV IEC61000-4-2 Level 4 (RD = 330Ω, CS = 150pF) Contact Discharge (IN_+, IN_-, OUT+, OUT-).................+8 kV Air-Gap Discharge (IN_+, IN_-, OUT+, OUT-)................+15kV Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = 3.0V to 3.6V, RL = 100Ω, PD = high, SEL = high or low, differential input voltage |VID| = 0.05V to 1.2V, MAX9176 input common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, MAX9177 input common-mode voltage VCM = |VID/2| to VCC - |VID/2|, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3V, |VID| = 0.2V, VCM = 1.25V, TA = +25°C.) (Notes 1, 2, 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS +50 mV DIFFERENTIAL INPUTS (IN_+, IN_-) Differential Input High Threshold Differential Input Low Threshold Input Current Power-Off Input Current Fail-Safe Input Resistors (MAX9176) VTH VTL IIN+, IIN- IINO+, IINO- RIN1 RIN2 -50 Figure 1 MAX9176 VCC = 0 or open, Figure 1 MAX9177 VIN+ = 3.6V or 0, VIN- = 3.6V or 0, VCC = 0 or open, Figure 1 VCC = 3.6V, 0 or open, Figure 1 Input Resistors (MAX9177) RIN3 VCC = 3.6V, 0 or open, Figure 1 Input Capacitance CIN IN_+ or IN_- to GND (Note 4) mV -20 +20 µA -20 +20 µA 60 108 200 394 212 450 kΩ 4.5 pF kΩ LVTTL/LVCMOS INPUTS (SEL, PD) Input High Voltage VIH 2.0 Input Low Voltage VIL -1.0 Input Current IIN -1.0V ≤ SEL, PD ≤ 0V -1.5 0V ≤ SEL, PD ≤ VCC -20 VCC + 1.0 +0.8 V V mA +20 µA +1.5 mA 393 475 mV 1.0 15 mV 1.25 1.375 V VCC ≤ SEL, PD ≤ VCC + 1.0V LVDS OUTPUT (OUT+, OUT-) Differential Output Voltage Change in Differential Output Voltage Between Logic States Offset Voltage 2 VOD Figure 2 ∆VOD Figure 2 VOS Figure 3 250 1.125 _______________________________________________________________________________________ 670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers (VCC = 3.0V to 3.6V, RL = 100Ω, PD = high, SEL = high or low, differential input voltage |VID| = 0.05V to 1.2V, MAX9176 input common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, MAX9177 input common-mode voltage VCM = |VID/2| to VCC - |VID/2|, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3V, |VID| = 0.2V, VCM = 1.25V, TA = +25°C.) (Notes 1, 2, 3) PARAMETER SYMBOL CONDITIONS Change in Offset Voltage Between Logic States ∆VOS Figure 3 Fail-Safe Differential Output Voltage (MAX9176) VOD Figure 2 Differential Output Resistance RDIFF VCC = 3.6V or 0 Power-Down Single-Ended Output Current IPD PD = low Power-Off Single-Ended Output Current IOFF PD, SEL = low, VCC = 0 or open Output Short-Circuit Current IOS VOUT+ = open, VOUT- = 3.6V or 0 MIN TYP MAX UNITS 4 15 mV 250 393 475 mV 95 123 146 Ω -1.0 ±0.01 +1.0 µA -1.0 ±0.01 +1.0 µA +15 mA 15 mA 40 mA 20 µA 5.2 pF VOUT- = open, VOUT+ = 3.6V or 0 VOUT+ = open, VOUT- = 3.6V or 0 VOUT- = open, VOUT+ = 3.6V or 0 VID = +50mV or -50mV, VOUT+ = 0 or VCC VID = +50mV or -50mV, VOUT- = 0 or VCC -15 Differential Output Short-Circuit Current Magnitude IOSD VID = +50mV or -50mV, VOD = 0 (Note 4) Supply Current ICC RL = 100Ω, PD = VCC, SEL = VCC or 0 26 ICCPD RL = 100Ω, PD = 0, other inputs open 0.5 Power-Down Supply Current Output Capacitance CO OUT+ or OUT- to GND (Note 4) _______________________________________________________________________________________ 3 MAX9176/MAX9177 DC ELECTRICAL CHARACTERISTICS (continued) MAX9176/MAX9177 670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers AC ELECTRICAL CHARACTERISTICS (VCC = 3.0V to 3.6V, RL = 100Ω, CL = 5pF, differential input voltage |VID| = 0.15V to 1.2V, MAX9176 input common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, MAX9177 input common-mode voltage VCM = |VID/2| to VCC - |VID/2|, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3V, |VID| = 0.2V, VCM = 1.25V, TA = +25°C.) (Notes 5, 6, 7) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIFFERENTIAL INPUTS (IN_+, IN_-) High-to-Low Propagation Delay tPHL Figures 4, 5 1.33 2.46 3.23 ns Low-to-High Propagation Delay tPLH Figures 4, 5 1.33 2.49 3.31 ns Added Deterministic Jitter tDJ Figures 4, 5 (Notes 8, 12) 68 80 ps(P-P) Added Random Jitter tRJ Figures 4, 5 (Note 12) 0.7 1.0 ps(RMS) ps Pulse Skew tPLH - tPHL Part-to-Part Skew Figures 4, 5 27 142 tSKPP1 tSKP Figures 4, 5 (Note 9) 0.4 1.3 tSKPP2 Figures 4, 5 (Note 10) ns 2.0 Rise Time tR Figures 4, 5 217 320 383 ps Fall Time tF Figures 4, 5 157 340 360 ps 2.0 Select to Out Delay tPSO 2.7 ns Power-Down Time tPD Figures 7, 8 6.0 ns Power-Up Time tPU Figures 7, 8 35 µs Maximum Data Rate Maximum Switching Frequency Figure 6 DRMAX Figures 4, 5, VOD ≥ 250mV (Note 11) 800 fMAX Figures 4, 5, VOD ≥ 250mV (Note 11) 670 Switching Supply Current ICCSW PRBS Supply Current ICCPR Mbps MHz fIN = 670MHz 38 58 fIN = 155MHz 26 47 DR = 800Mbps, 223 - 1 PRBS input 27 49 mA mA Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VTH, VTL, VID, VOD, and ∆VOD. Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are 100% tested at TA = +25°C. Note 3: Tolerance on all external resistors (including figures) is ±1%. Note 4: Guaranteed by design and characterization. Note 5: AC parameters are guaranteed by design and characterization and not production tested. Limits are set at ±6 sigma. Note 6: CL includes scope probe and test jig capacitance. Note 7: Pulse-generator output for differential inputs IN_+, IN_- (unless otherwise noted): f = 670MHz, 50% duty cycle, RO = 50Ω, tR = 500ps, and tF = 500ps (0% to 100%). Pulse-generator output for single-ended inputs PD, SEL: tR = tF = 1.5ns (0.2VCC to 0.8VCC), 50% duty cycle, VOH = VCC + 1.0V settling to VCC, VOL = -1.0V settling to zero. Note 8: Pulse-generator output for tDJ: VOD = 0.15V, VOS = 1.25V, bit rate = 800Mbps, 223 - 1 PRBS, RO = 50Ω, tR = 500ps, and tF = 500ps (0% to 100%). Note 9: tSKPP1 is the magnitude of the difference of any differential propagation delays between devices operating under identical conditions. Note 10: tSKPP2 is the magnitude of the difference of any differential propagation delays between devices operating over rated conditions. Note 11: Meets all AC specifications. Note 12: Input jitter subtracted from output jitter. 4 _______________________________________________________________________________________ 670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers MAX9176/MAX9177 VCC VCC RIN2 RIN3 COMPARATOR IN_+ IN_+ RIN1 VCC TO MUX TO MUX 0.3V IN_RIN1 RIN3 LVDS RCVR IN_- MAX9177 INPUT MAX9176 FAIL-SAFE INPUT Figure 1. Input Structure 1.25V 1.20V 1.25V 1.20V VOD IN_- OUT- VTEST = 0 TO VCC RL PULSE GENERATOR 5kΩ OUT+ IN_+ 5kΩ OUT+ IN_+ IN_- VTEST = 0 TO VCC RL OUT- 5kΩ 50Ω 5kΩ 50Ω CL CL Figure 4. Transition Time and Propagation Delay Test Circuit Figure 2. VOD Test Circuit IN_OUT+ 1.25V IN_+ IN_+ RL/2 1.20V 1.25V 1.20V tPLH tPHL OUTRL/2 IN_- VOS OUT- OUT+ VOS = ((VOUT+) + (VOUT-))/2 80% VOD+ 0 (OUT+) - (OUT)- 20% 20% tR Figure 3. VOS Test Circuit 80% 0 VOD- tF Figure 5. Transition Time and Propagation Delay Timing _______________________________________________________________________________________ 5 MAX9176/MAX9177 670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers IN0- VCC VID = -0.2V INO+ IN1+ 1.25V VID = +0.2V 1.20V IN_+ VCC + 1.0V 1.25V IN_- VCC 1.20V IN1- 5pF 50Ω MAX9176 MAX9177 0.5 VCC 0.5 VCC OUT+ OUT+ 50Ω 0 SEL -1.0V tPSO tPSO PD GENERATOR OUT5pF 50Ω OUT- GND OUT+ Figure 7. Power-Up/Down Delay Test Circuit Figure 6. Select-to-Out Delay Timing 1.0V + VCC VCC 0.5VCC PD 0V -1.0V tPU tPD VOH 50% 50% OUT+ WHEN VID = +50mV OUT- WHEN VID = -50mV 1.25V OUT+ WHEN VID = -50mV OUT- WHEN VID = +50mV 1.25V 50% 50% VOL tPD tPU Figure 8. Power-Up/Down Delay Waveform 6 _______________________________________________________________________________________ OUT- 1.25V 670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers 30 25 500 400 300 MAX9176 toc03 600 400 RISE/FALL TIME (ps) 35 450 MAX9176 toc02 40 700 DIFFERENTIAL OUTPUT VOLTAGE (mV) MAX9176 toc01 45 tR 350 300 tF 200 250 100 fIN = 155MHz fIN = 155MHz -40 -15 10 35 60 -40 100 200 300 400 500 600 700 800 -15 10 35 TEMPERATURE (°C) DIFFERENTIAL PROPAGATION DELAY vs. TEMPERATURE SUPPLY CURRENT vs. FREQUENCY SUPPLY CURRENT vs. DATA RATE 2.50 tPLH 2.25 tPHL 2.00 40 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 30 20 MAX9176 toc06 2.75 50 MAX9176 toc05 50 85 60 FREQUENCY (MHz) MAX9176 toc04 40 30 20 1.75 23 PRBS 2 - 1 10 1.50 -15 10 35 60 10 0 85 100 200 300 400 500 600 700 800 0 100 200 300 400 500 600 700 800 TEMPERATURE (°C) FREQUENCY (MHz) FREQUENCY (Mbps) DC SUPPLY CURRENT vs. SUPPLY VOLTAGE OUTPUT RISE/FALL TIME vs. SUPPLY VOLTAGE DIFFERENTIAL PROPAGATION DELAY vs. SUPPLY VOLTAGE 27 26 25 24 395 fIN = 155MHz 375 355 tF 335 315 tR 295 3.0 DIFFERENTIAL PROPAGATION DELAY (ns) MAX9176 toc07 28 OUTPUT RISE/FALL TIME (ps) -40 MAX9176 toc08 DIFFERENTIAL PROPAGATION DELAY (ns) 0 85 TEMPERATURE (°C) 3.00 DC SUPPLY CURRENT (mA) 200 0 20 2.8 MAX9176 toc09 SUPPLY CURRENT (mA) OUTPUT RISE/FALL TIME vs. TEMPERATURE DIFFERENTIAL OUTPUT VOLTAGE vs. FREQUENCY SUPPLY CURRENT vs. TEMPERATURE tPLH 2.5 2.3 tPHL 2.0 1.8 fIN = 155MHz 23 275 3.0 3.1 3.2 3.3 3.4 SUPPLY VOLTAGE (V) 3.5 3.6 1.5 3.0 3.1 3.2 3.3 3.4 SUPPLY VOLTAGE (V) 3.5 3.6 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 7 MAX9176/MAX9177 Typical Operating Characteristics ((MAX9176) VCC = 3.3V, |VID| = 0.2V, VCM = 1.25V, RL = 100Ω, CL = 5pf, PD = VCC, SEL = 0V, IN1+, IN1- = open, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) ((MAX9176) VCC = 3.3V, |VID| = 0.2V, VCM = 1.25V, RL = 100Ω, CL = 5pf, PD = VCC, SEL = 0V, IN1+, IN1- = open, TA = +25°C, unless otherwise noted.) DIFFERENTIAL PROPAGATION DELAY vs. COMMON-MODE VOLTAGE DC DIFFERENTIAL OUTPUT VOLTAGE vs. LOAD RESISTOR 400 300 200 MAX9176 toc11 500 3.00 DIFFERENTIAL PROPAGATION DELAY (ns) MAX9176 toc10 600 DC DIFFERENTIAL OUTPUT VOLTAGE (mV) MAX9176/MAX9177 670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers 2.88 2.75 tPLH, tPHL (MAX9177) 2.63 2.50 2.38 tPHL (MAX9176) tPLH (MAX9176) 2.25 fIN = 155MHz 2.13 100 50 70 90 110 130 150 0.1 LOAD RESISTOR (Ω) 0.5 0.9 1.3 1.7 2.0 2.4 2.8 3.2 COMMON-MODE VOLTAGE (V) Pin Description PIN 8 NAME FUNCTION µMAX QFN 1 1 IN0+ Noninverting Differential Input 0 2 2 IN0- Inverting Differential Input 0 3 3 GND Ground 4 4 IN1+ Noninverting Differential Input 1 5 5 IN1- Inverting Differential Input 1 6 6 SEL LVTTL/LVCMOS Input Select. SEL = high selects differential input 1. SEL = low selects differential input 0. Internal pulldown resistor to GND. 7 7 PD LVTTL/LVCMOS Input. Device is powered down when PD is low. Internal pulldown resistor to GND. 8 8 VCC Power Supply 9 9 OUT- Inverting Differential Output 10 10 OUT+ Noninverting Differential Output — EP Exposed Pad Exposed Pad. Solder to ground. _______________________________________________________________________________________ 670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers INPUTS OUTPUT (IN_+) - (IN_-) (OUT+) - (OUT-) ≥ +50mV ≤ -50mV -50mV < VID < +50mV MAX9177 Open MAX9176 Open, undriven short, or undriven parallel termination Table 2. Input Select and Power-Down Function Table SEL PD OUT+, OUT- H H H IN1+, IN1- L L or open H IN0+, IN0- X L or open Indeterminate High impedance to ground and 123Ω (typ) differential output resistance H Detailed Description The MAX9176/MAX9177 are 670MHz, low-jitter, lowskew 2:1 multiplexers ideal for protection switching, loopback, and clock distribution. The devices feature ultra-low 68ps(P-P) deterministic jitter that ensures reliable operation in high-speed links that are highly sensitive to timing error. The MAX9176 has fail-safe LVDS inputs and an LVDS output. The MAX9177 has anything differential inputs (CML/LVDS/LVPECL) and an LVDS output. The output can be put into high impedance using the power-down input. The MAX9176 features fail-safe circuits that drive the output high when a selected input is open, undriven and shorted, or undriven and terminated. The MAX9177 has bias circuits that force the output high when a selected input is open. The mux select and power-down inputs are compatible with standard LVTTL/LVCMOS logic. The select and power-down inputs tolerate undershoot of -1V and overshoot of V CC + 1V. The MAX9176/ MAX9177 are available in 10-pin µMAX and 10-lead thin QFN packages, and operate from a single 3.3V supply over the -40°C to +85°C temperature range. Current-Mode LVDS Output The LVDS output uses a current-steering configuration. This approach results in less ground bounce and less output ringing, enhancing noise margin and system speed performance. A differential output voltage is produced by steering current through the parallel combination of the integrated differential output resistor and transmission line impedance/termination resistor. When driving a 100Ω load, a differential voltage of 250mV to 475mV is produced. For loads greater than 100Ω, the output voltage is larger, and for loads less than 100Ω, the output volt- age is smaller. See the Differential Output Voltage vs. Load Resistance curve in Typical Operating Characteristics for more information. The output is short-circuit current limited for single-ended and differential shorts. MAX9176 Input Fail-Safe The fail-safe feature of the MAX9176 sets the output high when the differential input is: • Open • Undriven and shorted • Undriven and terminated Without a fail-safe circuit, when the selected input is undriven, noise at the input may switch the output and it may appear to the system that data is being sent. Open or undriven terminated input conditions can occur when a cable is disconnected or cut, or when the driver output is in high impedance. A shorted input can occur because of a cable failure. When the selected input is driven with a differential signal of VID= 50mV to 1.2V within a voltage range of 0 to 2.4V, the fail-safe circuit is not activated. If the selected input is open, undriven and shorted, or undriven and terminated, an internal resistor in the fail-safe circuit pulls both inputs above VCC - 0.3V, activating the failsafe circuit and forcing the output high (Figure 1). Overshoot and Undershoot Voltage Protection The MAX9176/MAX9177 are designed to protect the select and power-down inputs (SEL and PD) against latchup due to transient overshoot and undershoot voltage. If the input voltage goes above V CC or below GND by up to 1V, an internal circuit limits input current to 1.5mA. _______________________________________________________________________________________ 9 MAX9176/MAX9177 Table 1. Function Table MAX9176/MAX9177 670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers Applications Information Power-Supply Bypassing Bypass the VCC pin with high-frequency surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to VCC. Differential Traces Input and output trace characteristics affect the performance of the MAX9176/MAX9177. Use controlledimpedance differential traces (100Ω typical). To reduce radiated noise and ensure that noise couples as common mode, route the differential input and output signals within a pair close together. Reduce skew by matching the electrical length of the two signal paths that make up the differential pair. Excessive skew can result in a degradation of magnetic field cancellation. Maintain a constant distance between the differential traces to avoid discontinuities in differential impedance. Minimize the number of vias to further prevent impedance discontinuities. and single-ended logic signals is recommended. Separate the differential signals from the logic signals with power and ground planes for best results. IEC 61000-4-2 Level 4 ESD Protection The IEC 61000-4-2 standard (Figure 10) specifies ESD tolerance for electronic systems. The IEC61000-4-2 model specifies a 150pF capacitor that is discharged into the device through a 330Ω resistor. The MAX9176/ MAX9177 differential inputs and outputs are rated for IEC61000-4-2 level 4 (±8kV Contact Discharge and ±15kV Air-Gap Discharge). The Human Body Model (HBM, Figure 9) specifies a 100pF capacitor that is discharged into the device through a 1.5kΩ resistor. IEC 61000-4-2 level 4 discharges higher peak current and more energy than the HBM due to the lower series resistance and larger capacitor. RC 1MΩ RD 1.5kΩ Cables and Connectors Interconnect for LVDS typically has a controlled differential impedance of 100Ω. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Avoid the use of unbalanced cables such as ribbon or simple coaxial cable. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver. Termination The MAX9176/MAX9177 require external input and output termination resistors. For LVDS, connect an input termination resistor across each differential input and at the far end of the interconnect driven by the LVDS output. Place the input termination resistor as close to the receiver input as possible. Termination resistors should match the differential impedance of the transmission line. Use 1% surface-mount resistors. The MAX9176/MAX9177 feature an integrated differential output resistor. This resistor reduces jitter by damping reflections produced by any mismatch between the transmission line and termination resistor at the far end of the interconnect. Board Layout CHARGE-CURRENT LIMIT RESISTOR HIGHVOLTAGE DC SOURCE Cs 100pF DISCHARGE RESISTANCE STORAGE CAPACITOR Figure 9. Human Body Test Model RC 50Ω TO 100Ω CHARGE-CURRENT LIMIT RESISTOR HIGHVOLTAGE DC SOURCE Cs 150pF RD 330Ω DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST Figure 10. IEC 61000_4-2 Contact Discharge Test Model Separate the differential and single-ended signals to reduce crosstalk. A four-layer printed circuit board with separate layers for power, ground, differential signals, 10 DEVICE UNDER TEST ______________________________________________________________________________________ 670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers MAX9176/MAX9177 Functional Diagram IN0+ IN0- OUT+ OUT- IN1+ IN1SEL PD Chip Information TRANSISTOR COUNT: 744 PROCESS: CMOS ______________________________________________________________________________________ 11 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) e 10LUMAX.EPS MAX9176/MAX9177 670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers 4X S 10 10 INCHES H ÿ 0.50±0.1 0.6±0.1 1 1 0.6±0.1 BOTTOM VIEW TOP VIEW D2 MILLIMETERS MAX DIM MIN 0.043 A 0.006 A1 0.002 A2 0.030 0.037 0.120 D1 0.116 0.118 0.114 D2 0.116 0.120 E1 E2 0.114 0.118 H 0.187 0.199 L 0.0157 0.0275 L1 0.037 REF b 0.007 0.0106 e 0.0197 BSC c 0.0035 0.0078 0.0196 REF S α 0∞ 6∞ MAX MIN 1.10 0.15 0.05 0.75 0.95 3.05 2.95 3.00 2.89 3.05 2.95 2.89 3.00 4.75 5.05 0.40 0.70 0.940 REF 0.177 0.270 0.500 BSC 0.090 0.200 0.498 REF 0∞ 6∞ E2 GAGE PLANE A2 c A b A1 α E1 D1 FRONT VIEW L L1 SIDE VIEW PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, 10L uMAX/uSOP APPROVAL DOCUMENT CONTROL NO. 21-0061 12 ______________________________________________________________________________________ REV. I 1 1 670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers 6, 8, &10L, QFN THIN.EPS PACKAGE OUTLINE, 6, 8 & 10L, QFN THIN (DUAL), EXPOSED PAD, 3x3x0.80 mm 21-0137 C ______________________________________________________________________________________ 13 MAX9176/MAX9177 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) MAX9176/MAX9177 670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) COMMON DIMENSIONS SYMBOL A MIN. MAX. 0.70 0.80 D 2.90 3.10 E 2.90 3.10 A1 0.00 0.05 L k 0.20 0.40 0.25 MIN A2 0.20 REF. PACKAGE VARIATIONS PKG. CODE N D2 E2 e JEDEC SPEC b T633-1 6 1.50±0.10 2.30±0.10 0.95 BSC MO229 / WEEA 0.40±0.05 1.90 REF T833-1 8 1.50±0.10 2.30±0.10 0.65 BSC MO229 / WEEC 0.30±0.05 1.95 REF T1033-1 10 1.50±0.10 2.30±0.10 0.50 BSC MO229 / WEED-3 0.25±0.05 2.00 REF [(N/2)-1] x e PACKAGE OUTLINE, 6, 8 & 10L, QFN THIN (DUAL), EXPOSED PAD, 3x3x0.80 mm 21-0137 C Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.