19-5036; Rev 0; 10/09 KIT ATION EVALU E L B A AVAIL 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs † The MAX11044/MAX11045/MAX11046 16-bit ADCs offer 4, 6, or 8 independent input channels. Featuring independent track and hold (T/H) and SAR circuitry, these parts provide simultaneous sampling at 250ksps for each channel. The MAX11044/MAX11045/MAX11046 accept a ±5V input. All inputs are overrange protected with internal ±20mA input clamps providing overrange protection with a simple external resistor. Other features include a 4MHz T/H input bandwidth, internal clock, and internal or external reference. A 20MHz, 16-bit, bidirectional, parallel interface provides the conversion results and accepts digital configuration inputs. The MAX11044/MAX11045/MAX11046 operate with a 4.75V to 5.25V analog supply and a separate flexible 2.7V to 5.25V digital supply for interfacing with the host without a level shifter. The MAX11044/MAX11045/MAX11046 are available in a 56-pin TQFN package and operate over the extended -40°C to +85°C temperature range. Applications Automatic Test Equipment Power-Factor Monitoring and Correction Power-Grid Protection Multiphase Motor Control Vibration and Waveform Analysis Features ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ 4-/6-/8-Channel 16-Bit ADC Single Analog and Digital Supply High-Impedance Inputs Up to 1GΩ On-Chip T/H Circuit for Each Channel Fast 3µs Conversion Time High Throughput: 250ksps for All 8 Channels 16-Bit, High-Speed, Parallel Interface Internal Clocked Conversions 10ns Aperture Delay 100ps Channel-to-Channel T/H Matching Low Drift, Accurate 4.096V Internal Reference Providing an Input Range of ±5V ♦ External Reference Range of 3.0V to 4.25V, Allowing Full-Scale Input Ranges of ±4.0V to ±5.2V ♦ 56-Pin TQFN Package (8mm x 8mm) ♦ Evaluation Kit Available Ordering Information PART PIN-PACKAGE 56 TQFN-EP* 4 MAX11045ETN+ 56 TQFN-EP* 6 MAX11046ETN+ 56 TQFN-EP* 8 Note: All devices are specified over the -40°C to +85°C operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. 8 x 16-BIT REGISTERS 16-BIT ADC DB4 DB3 DB0 RD CH1 AVDD 24 AVDD 23 AGNDS AGNDS 48 SHDN 22 RDC MAX11044 MAX11045 MAX11046 DVDD 51 21 DGND 20 DVDD WR 52 19 SHDN CS 53 18 CONVST 17 EOC RD 54 DB15 55 *EP + 16 DB0 15 DB1 9 10 11 12 13 14 DB2 8 DB3 7 DB4 6 DB5 5 DB6 4 DB7 3 DVDD 2 DB9 DGND 1 DB10 RDC DB11 DB14 56 REF BUF EXT REF AGND 25 AGND AVDD 47 DB12 BANDGAP REFERENCE CONVST EOC INT REF REFIO WR CS INTERFACE AND CONTROL CH2 AGND 46 DB13 AGND MAX11044 MAX11045 MAX11046 AGNDS 26 CH0 CH7 45 DGND 50 AGNDs REFIO 27 AGNDS AGNDS 44 RDC 49 CONFIGURATION REGISTERS CH4 AGNDS CH5 AGND 28 RDC RDC 43 DGND S/H 16-BIT ADC DB8 CLAMP S/H AVDD 42 41 40 39 38 37 36 35 34 33 32 31 30 29 DB15 CLAMP BIDIRECTIONAL DRIVERS CH7 DVDD CH6 TOP VIEW AVDD CH3 Pin Configuration Functional Diagram RDC †Patent pending. CH0 CHANNELS MAX11044ETN+ TQFN 8mm x 8mm ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX11044/MAX11045/MAX11046 General Description MAX11044/MAX11045/MAX11046 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs ABSOLUTE MAXIMUM RATINGS AVDD to AGND ........................................................-0.3V to +6V DVDD to AGND and DGND .....................................-0.3V to +6V DGND to AGND.....................................................-0.3V to +0.3V AGNDS to AGND...................................................-0.3V to +0.3V CH0–CH7 to AGND ...............................................-7.5V to +7.5V REFIO, RDC to AGND ..................................-0.3V to the lower of (AVDD + 0.3V) and +6V EOC, WR, RD, CS, CONVST to AGND.........-0.3V to the lower of (DVDD + 0.3V) and +6V DB0–DB15 to AGND ....................................-0.3V to the lower of (DVDD + 0.3V) and +6V Maximum Current into Any Pin Except AVDD, DVDD, AGND, DGND ...........................................................................±50mA Continuous Power Dissipation 56-Pin TQFN (derate 36mW/°C above +70°C) ..........2222mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVDD = +4.75V to +5.25V, DVDD = +2.70V to +5.25V, VAGNDS = VAGND = VDGND = 0V, VREFIO = internal reference, CRDC = 4 x 33µF, CREFIO = 0.1µF, CAVDD = 4 x 0.1µF || 10µF, CDVDD = 3 x 0.1µF || 10µF; all digital inputs at DVDD or DGND, unless otherwise noted, fSAMPLE = 250ksps. TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE (Note 1) Resolution N 16 (Note 2) Integral Nonlinearity Differential Nonlinearity INL DNL >-2 (Note 3) ±0.8 <+2 ±0.7 (Note 4) > -1 (Note 5) > -1 (Note 3) No Missing Codes Bits ±0.5 < +1.2 ±0.7 < +1.5 LSB LSB ±0.45 16 Offset Error Bits ±0.002 Channel Offset Matching Offset Temperature Coefficient ±0.01 %FSR ±0.01 %FSR ±2.4 µV/°C Gain Error ±0.03 %FSR Positive Full-Scale Error ±0.02 %FSR Negative Full-Scale Error ±0.02 %FSR Positive Full-Scale Error Matching ±0.02 %FSR Negative Full-Scale Error Matching ±0.02 %FSR ±0.03 %FSR Channel Gain-Error Matching Between all channels Gain Temperature Coefficient ±0.8 ppm/°C 92.3 dB DYNAMIC PERFORMANCE (Note 6) Signal-to-Noise Ratio SNR fIN = 10kHz, full-scale input 91 Signal-to-Noise and Distortion Ratio SINAD fIN = 10kHz, full-scale input 90.5 92 dB Spurious-Free Dynamic Range SFDR fIN = 10kHz, full-scale input 95 106 dB Total Harmonic Distortion THD fIN = 10kHz, full-scale input -105 -95 dB fIN = 60Hz, full scale and ground on adjacent channel (Note 7) -126 -100 dB Channel-to-Channel Crosstalk 2 _______________________________________________________________________________________ 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs (AVDD = +4.75V to +5.25V, DVDD = +2.70V to +5.25V, VAGNDS = VAGND = VDGND = 0V, VREFIO = internal reference, CRDC = 4 x 33µF, CREFIO = 0.1µF, CAVDD = 4 x 0.1µF || 10µF, CDVDD = 3 x 0.1µF || 10µF; all digital inputs at DVDD or DGND, unless otherwise noted, fSAMPLE = 250ksps. TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ±1.22 x VREFIO V +1 µA ANALOG INPUTS (CH0–CH7) Input-Voltage Range (Note 8) Input Leakage Current -1 Input Capacitance 15 Input-Clamp Protection Current Each input simultaneously pF -20 +20 mA 1 250 ksps 1000 µs TRACK AND HOLD Throughput Rate Per channel, 8 channels in 4µs Acquisition Time tACQ 1 -3dB point Full-Power Bandwidth 4 -0.1dB point MHz > 0.2 Aperture Delay 10 Aperture-Delay Matching 100 ns ps Aperture Jitter 50 psRMS INTERNAL REFERENCE REFIO Voltage VREF 4.073 REFIO Temperature Coefficient 4.096 4.119 ±5 V ppm/°C EXTERNAL REFERENCE Input Current REF Voltage-Input Range VREF -10 +10 µA 3.00 4.25 V REF Input Capacitance 15 pF DIGITAL INPUTS (DB0–DB15, RD, WR, CS, CONVST) Input Voltage High VIH VDVDD = 2.7V to 5.25V Input Voltage Low VIL VDVDD = 2.7V to 5.25V Input Capacitance CIN Input Current IIN VIN = 0V or VDVDD Output Voltage High VOH ISOURCE = 1.2mA Output Voltage Low VOL ISINK = 1mA 2 V 0.8 10 V pF ±10 µA DIGITAL OUTPUTS (DB0–DB15, EOC) Three-State Leakage Current DB0–DB15, VRD ≥ VIH or VCS ≥ VIH Three-State Output Capacitance DB0–DB15, VRD ≥ VIH or VCS ≥ VIH VDVDD 0.4 V 0.25 0.4 V 10 µA 15 pF POWER SUPPLIES Analog Supply Voltage AVDD Digital Supply Voltage DVDD Analog Supply Current IAVDD 4.75 5.25 V 2.70 5.25 V MAX11046, AVDD = 5V MAX11045, AVDD = 5V 48 42 MAX11044, AVDD = 5V 36 mA _______________________________________________________________________________________ 3 MAX11044/MAX11045/MAX11046 ELECTRICAL CHARACTERISTICS (continued) MAX11044/MAX11045/MAX11046 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs ELECTRICAL CHARACTERISTICS (continued) (AVDD = +4.75V to +5.25V, DVDD = +2.70V to +5.25V, VAGNDS = VAGND = VDGND = 0V, VREFIO = internal reference, CRDC = 4 x 33µF, CREFIO = 0.1µF, CAVDD = 4 x 0.1µF || 10µF, CDVDD = 3 x 0.1µF || 10µF; all digital inputs at DVDD or DGND, unless otherwise noted, fSAMPLE = 250ksps. TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL Digital Supply Current Shutdown Current Power-Supply Rejection Ratio IDVDD MAX UNITS MAX11046, DVDD = 3.3V (Note 9) CONDITIONS MIN TYP 7.3 mA MAX11045, DVDD = 3.3V (Note 9) 6.3 mA MAX11044, DVDD = 3.3V (Note 9) 5.5 mA IDVDD 10 IAVDD 12 PSRR VAVDD = 4.9V to 5.1V (Note 10) CONVST Rise to EOC tCON Conversion time (Note 11) Acquisition Time tACQ µA LSB ±3 TIMING CHARACTERISTICS (Note 9) 1 3 µs 1000 µs CS Rise to CONVST Rise tQ CONVST Rise to EOC Rise t0 EOC Fall to CONVST Fall t1 CONVST mode B0 = 0 only (Note 12) 0 ns CONVST Low Time t2 CONVST mode B0 = 1 only 20 ns CS Fall to WR Fall t3 0 ns WR Low Time t4 20 ns CS Rise to WR Rise t5 0 ns Input Data Setup Time t6 10 ns Input Data Hold Time t7 1 ns CS Fall to RD Fall t8 0 ns RD Low Time t9 30 ns RD Rise to CS Rise t10 0 ns RD High Time t11 10 ns RD Fall to Data Valid t12 RD Rise to Data Hold Time t13 Sample quiet time (Note 11) 500 ns 47 140 35 (Note 12) 5 ns ns ns Note 1: See the Definitions section at the end of the data sheet. Note 2: INL is guaranteed at AVDD = 5.25V, for +25°C < TA < +85°C. See the Input Range and Protection section and Typical Operating Characteristics. Note 3: TA = -40°C. Note 4: DNL at code > 8192 or < 57343 (offset binary encoded), or code > -24576 or < +24575 (two’s complement), is guaranteed at AVDD = 5.25V, for +25°C < TA < +85°C. See the Input Range and Protection section and Typical Operating Characteristics. Note 5: DNL at code ≤ 8192 or ≥ 57343 (offset binary encoded), or code ≤ -24576 or ≥ +24575 (2’s complements), is guaranteed at AVDD = 5.25V, for +25°C < TA < +85°C. See the Input Range and Protection section and Typical Operating Characteristics. Note 6: AC dynamics are guaranteed at AVDD = 5.25V, for +25°C < TA < +85°C. See the Input Range and Protection section and Typical Operating Characteristics. Note 7: Tested with alternating channels modulated at full scale and ground. Note 8: See the Input Range and Protection section for more details. Note 9: CLOAD = 30pF on DB0–DB15 and EOC. Inputs (CH0–CH7) alternate between full scale and zero scale. fCONV = 250ksps. All data is read out. Note 10: Defined as the change in positive full scale caused by a ±2% variation in the nominal supply voltage. Note 11: It is recommended that RD, WR, and CS are kept high for the quiet time (tQ) and conversion time (tCON). Note 12: Guaranteed by design. 4 _______________________________________________________________________________________ 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs 0.2 VAVDD = 5.25V VDVDD = 3.3V fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V -0.6 32768 24576 16384 8192 65536 0 -0.8 -1.0 MAX DNL 0 MIN DNL -0.5 4.75 4.85 5.15 5.25 MAX DNL MAX11046 STATIC 40 IAVDD (mA) 0.5 VAVDD = 5.25V VDVDD = 3.3V fSAMPLE = 250ksps VRDC = 4.096V TA = +25°C fSAMPLE = 250ksps MAX11046 CONVERTING MAX11044 toc05 45 MAX11044 toc04 1.0 -0.5 5.05 VAVDD (V) ANALOG SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX INL MIN DNL 4.95 OUTPUT CODE (DECIMAL) 1.5 0 VDVDD = 3.3V fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V MIN INL -1.5 INL AND DNL vs. TEMPERATURE INL AND DNL (LSB) 0.5 -1.0 65536 -0.4 57344 32768 24576 16384 8192 -0.2 OUTPUT CODE (DECIMAL) MAX11045 CONVERTING 35 MAX11045 STATIC MAX11044 CONVERTING 30 -1.0 MIN INL MAX11044 STATIC 25 -1.5 10 35 60 85 4.95 5.05 5.15 ANALOG SUPPLY CURRENT vs. TEMPERATURE DIGITAL SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX11046 STATIC 5.25 12 10 TA = +25°C fSAMPLE = 250ksps MAX11046 CONVERTING 8 IDVDD (mA) MAX11045 CONVERTING 35 4.85 VAVDD (V) MAX11046 CONVERTING VAVDD = 5.0V fSAMPLE = 250ksps 40 4.75 TEMPERATURE (°C) MAX11044 toc07 45 -15 MAX11044 toc06 -40 IAVDD (mA) 0 -0.8 -1.0 49152 -0.6 40960 VAVDD = 5.25V VDVDD = 3.3V fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V -0.4 0 57344 0 MAX INL 1.0 INL AND DNL (LSB) 0.4 0.2 DNL (LSB) 0.4 1.5 MAX11044 toc02 0.6 49152 0.6 0.8 40960 0.8 INL (LSB) 1.0 MAX11044 toc01 1.0 -0.2 INL AND DNL vs. ANALOG SUPPLY VOLTAGE DIFFERENTIAL NONLINEARITY vs. CODE MAX11044 toc03 INTEGRAL NONLINEARITY vs. CODE MAX11045 STATIC 6 MAX11045 CONVERTING 4 MAX11044 CONVERTING MAX11044/MAX11045/ MAX11046 STATIC 30 2 MAX11044 CONVERTING MAX11044 STATIC 25 0 -40 -15 10 35 TEMPERATURE (°C) 60 85 2.75 3.25 3.75 4.25 4.75 5.25 VDVDD (V) _______________________________________________________________________________________ 5 MAX11044/MAX11045/MAX11046 Typical Operating Characteristics (AVDD = 5V, DVDD = 3.3V, TA = +25°C, fSAMPLE = 250ksps, internal reference, unless otherwise noted.) Typical Operating Characteristics (continued) (AVDD = 5V, DVDD = 3.3V, TA = +25°C, fSAMPLE = 250ksps, internal reference, unless otherwise noted.) MAX11044 CONVERTING 2.4 VDVDD = 3.3V fSAMPLE = 250ksps CDBxx = 15pF MAX11044/MAX11045/ MAX11046 STATIC 2 -15 10 35 60 IDVDD 1 0 -40 IAVDD 3 -15 10 35 60 3.25 3.75 4.25 4.75 AVDD AND DVDD (V) TEMPERATURE (°C) INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE 4.112 MAX11044 toc10 4.09520 TA = +25°C 4.09515 VAVDD = 5.0V 4.108 4.104 VRDC VREFIO (V) VREF (V) IDVDD 2.75 85 INTERNAL REFERENCE VOLTAGES vs. SUPPLY VOLTAGE 4.09505 UPPER TYPICAL LIMIT 4.100 4.096 4.092 4.09500 LOWER TYPICAL LIMIT 4.088 VREFIO 4.09495 4.084 4.080 4.09490 4.75 4.85 4.95 5.05 5.15 -40 5.25 -15 10 35 60 VAVDD (V) TEMPERATURE (°C) OFFSET ERROR AND OFFSET ERROR MATCHING vs. SUPPLY VOLTAGE OFFSET ERROR AND OFFSET ERROR MATCHING vs. TEMPERATURE TA = +25°C 0.006 85 0.010 MAX11044 toc12 0.010 VAVDD = 5.0V VREFIO = 4.096V 0.006 OFFSET ERROR MATCHING OFFSET ERROR MATCHING ERRORS (%FS) ERRORS (%FS) MAX11044 toc09A 2 0 -40 TEMPERATURE (°C) 4.09510 IAVDD 3 1 0 85 4 MAX11044 toc13 1.2 4 TA = +25°C MAX11044 toc11 MAX11045 CONVERTING VAVDD = 5.0V VDVDD = 3.3V SHUTDOWN CURRENT (µA) 4.8 5 MAX11044 toc09 6.0 5 SHUTDOWN CURRENT (µA) MAX11046 CONVERTING MAX11044 toc08 7.2 3.6 ANALOG AND DIGITAL SHUTDOWN CURRENT vs. SUPPLY VOLTAGE ANALOG AND DIGITAL SHUTDOWN CURRENT vs. TEMPERATURE DIGITAL SUPPLY CURRENT vs. TEMPERATURE IDVDD (mA) MAX11044/MAX11045/MAX11046 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs 0.002 -0.002 0.002 -0.002 OFFSET ERROR OFFSET ERROR -0.006 -0.006 -0.010 -0.010 4.75 4.85 4.95 5.05 VAVDD (V) 6 5.15 5.25 -40 -15 10 35 TEMPERATURE (°C) _______________________________________________________________________________________ 60 85 5.25 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs GAIN ERROR AND GAIN ERROR MATCHING vs. TEMPERATURE VAVDD = 5.0V GAIN ERROR MATCHING -0.003 0.002 -0.002 OFFSET ERROR MATCHING 4.95 5.05 5.15 -140 -40 5.25 -15 10 35 60 85 0 100 MAX11044 toc17 95 -80 fIN = 10kHz fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V VIN = -0.025dB FROM FS 94 SNR AND SINAD (dB) MAGNITUDE (dB) -60 75 125 SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-NOISE AND DISTORTION RATIO vs. TEMPERATURE fIN1 = 9838Hz fIN2 = 10235Hz fSAMPLE = 250ksps TA = +25°C VAVDD = 5.0V VRDC = 4.096V VIN = -0.01dBFS -40 50 FREQUENCY (kHz) TWO-TONE IMD PLOT -20 25 TEMPERATURE (°C) VAVDD (V) 0 -80 MAX11044 toc18 4.85 -60 -120 -0.010 4.75 -40 -100 -0.006 -0.005 fIN = 10kHz fSAMPLE = 250ksps TA = +25°C VAVDD = 5.0V -20 MAGNITUDE (dB) ERRORS (%FS) SNR 93 92 -100 91 SINAD -120 90 -140 7.2 8.0 8.8 9.6 10.4 11.2 12.0 10 35 60 TEMPERATURE (°C) TOTAL HARMONIC DISTORTION vs. TEMPERATURE SNR AND SINAD vs. ANALOG SUPPLY VOLTAGE -103.5 -104.0 -104.5 SNR 92.5 92.0 91.5 fIN = 10kHz fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V VIN = -0.025dB FROM FS SINAD 91.0 -105.0 85 93.0 MAX11044 toc19 fIN = 10kHz fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V VIN = -0.025dB FROM FS SNR AND SINAD (dB) THD (dB) -15 FREQUENCY (kHz) -102.5 -103.0 -40 12.8 MAX11044 toc20 ERRORS (%FS) 0 OFFSET ERROR 0.006 0.003 0 MAX11044 toc15 TA = +25°C GAIN ERROR FFT PLOT 0.010 MAX11044 toc14 0.005 MAX11044 toc16 GAIN ERROR AND GAIN ERROR MATCHING vs. SUPPLY VOLTAGE 90.5 -40 -15 10 35 TEMPERATURE (°C) 60 85 4.75 4.85 4.95 5.05 5.15 5.25 VAVDD (V) _______________________________________________________________________________________ 7 MAX11044/MAX11045/MAX11046 Typical Operating Characteristics (continued) (AVDD = 5V, DVDD = 3.3V, TA = +25°C, fSAMPLE = 250ksps, internal reference, unless otherwise noted.) Typical Operating Characteristics (continued) (AVDD = 5V, DVDD = 3.3V, TA = +25°C, fSAMPLE = 250ksps, internal reference, unless otherwise noted.) SIGNAL-TO-NOISE AND DISTORTION RATIO vs. FREQUENCY 94 -90 fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V VIN = -0.025dB FROM FS 86 84 -105 -105 -110 -115 82 5.05 5.15 5.25 0.1 VAVDD (V) 1 0.1 100 10 fIN = 60kHz fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V VIN = -0.025dB FROM FS INACTIVE CHANNEL AT GND -110 -120 -130 200,000 NUMBER OF OCCURRENCES VCHX = 0V VAVDD = 5.0V fSAMPLE = 250ksps TA = +25°C 150,000 100,000 50,000 -140 0 0.1 1 10 32765 CROSSTALK (dB) MAX11044 toc24 -90 100 FREQUENCY (kHz) OUTPUT CODE (DECIMAL) CONVERSION TIME vs. ANALOG SUPPLY VOLTAGE 2.99 CONVERSION TIME (µs) 2.98 2.97 2.96 2.95 MAX11044 toc27 2.99 CONVERSION TIME (µs) CONVERSION TIME vs. TEMPERATURE 3.00 MAX11044 toc26 3.00 2.98 2.97 2.96 2.95 2.94 2.94 2.93 2.93 2.92 2.92 4.75 4.85 4.95 5.05 VAVDD (V) 8 100 10 OUTPUT NOISE HISTOGRAM WITH INPUT CONNECTED TO GND CROSSTALK vs. FREQUENCY -100 1 FREQUENCY (kHz) FREQUENCY (kHz) MAX11044 toc25 4.95 32768 4.85 32767 4.75 -100 32766 -104 88 -95 32771 fIN = 10kHz fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V VIN = -0.025dB FROM FS -103 90 32770 SINAD (dB) -102 THD (dB) 92 -101 fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V VIN = -0.025dB FROM FS -85 32769 -100 THD vs. INPUT FREQUENCY -80 MAX11044 toc22 96 MAX11044 toc21 -99 MAX11044 toc23 TOTAL HARMONIC DISTORTION vs. ANALOG SUPPLY VOLTAGE THD (dB) MAX11044/MAX11045/MAX11046 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs 5.15 5.25 -40 -15 10 35 TEMPERATURE (°C) _______________________________________________________________________________________ 60 85 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs PIN NAME 1 DB13 16-Bit Parallel Data Bus Digital Output Bit 13 FUNCTION 2 DB12 16-Bit Parallel Data Bus Digital Output Bit 12 3 DB11 16-Bit Parallel Data Bus Digital Output Bit 11 4 DB10 16-Bit Parallel Data Bus Digital Output Bit 10 5 DB9 16-Bit Parallel Data Bus Digital Output Bit 9 6 DB8 16-Bit Parallel Data Bus Digital Output Bit 8 7, 21, 50 DGND Digital Ground 8, 20, 51 DVDD Digital Supply. Bypass to DGND with a 0.1µF capacitor at each DVDD input. 9 DB7 16-Bit Parallel Data Bus Digital Output Bit 7 10 DB6 16-Bit Parallel Data Bus Digital Output Bit 6 11 DB5 16-Bit Parallel Data Bus Digital Output Bit 5 12 DB4 16-Bit Parallel Data Bus Digital Output Bit 4 13 DB3 16-Bit Parallel Data Bus Digital I/O Bit 3 14 DB2 16-Bit Parallel Data Bus Digital I/O Bit 2 15 DB1 16-Bit Parallel Data Bus Digital I/O Bit 1 16 DB0 16-Bit Parallel Data Bus Digital I/O Bit 0 17 EOC Active-Low, End-of-Conversion Output. EOC goes low when a conversion is completed. EOC goes high when a conversion is initiated. 18 CONVST 19 SHDN 22, 28, 35, 43, 49 RDC 23, 27, 33, 38, 44, 48 AGNDS 24, 30, 41, 47 AVDD Analog Supply Input. Bypass AVDD to AGND with a 0.1µF capacitor at each AVDD input. 25, 31, 40, 46 AGND Analog Ground. Connect all AGND inputs together. 26 CH0 Channel 0 Analog Input 29 CH1 Channel 1 Analog Input 32 CH2 Channel 2 Analog Input 34 CH3 36 REFIO 37 CH4 Channel 4 Analog Input 39 CH5 Channel 5 Analog Input Convert Start Input. The rising edge of CONVST ends sample and starts a conversion on the captured sample. The ADC is in acquisition mode when CONVST is low and CONVST mode = 0. Shutdown Input. If SHDN is held high, the entire device will enter and stay in a low-current state. Contents of the configuration register are not lost when in the shutdown state. Reference Buffer Decoupling. Connect all RDC outputs together. Bypass to AGND with at least a 80µF total capacitance. See the Layout, Grounding, and Bypassing section. Signal Ground. Connect all AGND and AGNDS inputs together. Channel 3 Analog Input External Reference Input/Internal Reference Output. Place a 0.1µF capacitor from REFIO to AGND. _______________________________________________________________________________________ 9 MAX11044/MAX11045/MAX11046 Pin Description MAX11044/MAX11045/MAX11046 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs Pin Description (continued) PIN NAME 42 CH6 FUNCTION 45 CH7 Channel 7 Analog Input 52 WR Active-Low Write Input. Drive WR low to write to the ADC. Configuration registers are loaded on the rising edge of WR. 53 CS Active-Low Chip-Select Input. Drive CS low when reading from or writing to the ADC. 54 RD Active-Low Read Input. Drive RD low to read from the ADC. Each rising edge of RD advances the channel output on the data bus. 55 DB15 16-Bit Parallel Data Bus Digital Out Bit 15 56 DB14 16-Bit Parallel Data Bus Digital Out Bit 14 — EP Channel 6 Analog Input Exposed Pad. Internally connected to AGND. Connect to a large ground plane to maximize thermal performance. Not intended as an electrical connection point. Detailed Description The MAX11044/MAX11045/MAX11046 are fast, lowpower ADCs that combine 4, 6, or 8 independent ADC channels in a single IC. Each channel includes simultaneously sampling independent T/H circuitry that preserves relative phase information between inputs making the MAX11044/MAX11045/MAX11046 ideal for motor control and power monitoring. The MAX11044/ MAX11045/MAX11046 are available with ±5V input ranges that feature ±20mA overrange, fault-tolerant inputs. The MAX11044/MAX11045/MAX11046 operate with a single 4.75V to 5.25V supply. A separate 2.7V to 5.25V supply for digital circuitry makes the devices compatible with low-voltage processors. The MAX11044/MAX11045/MAX11046 perform conversions for all channels in parallel by activating independent ADCs. Results are available through a high-speed, 20MHz, parallel data bus after a conversion time of 3µs following the end of a sample. The data bus is bidirectional and allows for easy programming of the configuration register. The MAX11044/MAX11045/MAX11046 feature a reference buffer, which is driven by an internal bandgap reference circuit (VREFIO = 4.096V). Drive REFIO with an external reference or bypass with 0.1µF capacitor to ground when using the internal reference. Analog Inputs Track and Hold (T/H) To preserve phase information across all channels, each input includes a dedicated T/H circuitry. The input tracking circuitry provides a 4MHz small-signal bandwidth, enabling the device to digitize high-speed transient events and measure periodic signals with 10 bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. Use anti-alias filtering to avoid high-frequency signals being aliased into the frequency band of interest. Input Range and Protection The full-scale analog input voltage is a product of the reference voltage. For the MAX11044/MAX11045/ MAX11046, the full-scale input is bipolar in the range of: ±(VREFIO x 5 ) 4.096 When in external reference mode, drive VREFIO with a 3.0V to 4.25V source, resulting in an input range of ±3.662V to ±5.188V, respectively. All analog inputs are fault-protected to up to ±20mA. The MAX11044/MAX11045/MAX11046 include an input clamping circuit that activates when the input voltage at the analog input is above (VAVDD + 300mV) or below –(VAVDD + 300mV). The clamp circuit remains high impedance while the input signal is within the range of ±VAVDD and draws little or almost no current. However, when the input signal exceeds ±VAVDD, the clamps begin to turn on and shunt current to/from the AVDD supply. Consequently, to obtain the highest accuracy, ensure that the input voltage does not exceed ±VAVDD. Note that the input clamp circuit also has a small amount of hysteresis and once triggered remains engaged, shunting current to/from AVDD until the input returns to within the convertible range by several hundredths of a volt. This effect can cause some errors at the extremes of the transfer function if VIN is driven beyond ±VAVDD. ______________________________________________________________________________________ 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs RS = where VFAULT_MAX is the maximum voltage that the source produces during a fault condition. Figures 2 and 3 illustrate the clamp circuit voltage-current characteristics for a source impedance R S = 1280Ω. While the input voltage is within the ±(VAVDD + 300mV) range, no current flows in the input clamps. Once the input voltage goes beyond this voltage range, the clamps turn on and limit the voltage at the input pin. VFAULT _ MAX - 7V 20mA INPUT SIGNAL PIN VOLTAGE AVDD DVDD DB15 CLAMP S/H 16-BIT ADC 8 x 16-BIT REGISTERS CH0 SOURCE CH7 CLAMP S/H BIDIRECTIONAL DRIVERS RS DB4 DB3 DB0 16-BIT ADC CONFIGURATION REGISTERS AGNDS MAX11044 MAX11045 MAX11046 WR RD CS INTERFACE AND CONTROL AGND CONVST SHDN EOC INT REF BANDGAP REFERENCE RDC REF BUF DGND EXT REF REFIO Figure 1. Required Setup for Clamp Circuit RS = 1280Ω VAVDD = 5V MAX11044 fig03 20 30 MAX11044 fig02 30 RS = 1280Ω VAVDD = 5V 20 AT CH_ INPUT ICLAMP (mA) ICLAMP (mA) AT CH_ INPUT 10 AT SOURCE 0 10 AT SOURCE 0 -10 -10 -20 -20 -30 -30 -50 -30 -10 10 30 SIGNAL VOLTAGE AT SOURCE AND PIN (V) Figure 2. Input Clamp Characteristics 50 -8 -6 -4 -2 0 2 4 6 8 SIGNAL VOLTAGE AT SOURCE AND PIN (V) Figure 3. Input Clamp Characteristics (Zoom In) ______________________________________________________________________________________ 11 MAX11044/MAX11045/MAX11046 To make use of the input clamps (see Figure 1), connect a resistor (RS) between the analog input and the voltage source to limit the voltage at the analog input so that the fault current into the MAX11044/MAX11045/ MAX11046 does not exceed ±20mA. Note that the voltage at the analog input pin limits to approximately 7V during a fault condition so the following equation can be used to calculate the value of RS: MAX11044/MAX11045/MAX11046 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs Applications Information Digital Interface The bidirectional, parallel, digital interface, DB0–DB3, sets the 4-bit configuration register. This interface configures the following control signals: chip select (CS), read (RD), write (WR), end of conversion (EOC), and convert start (CONVST). Figures 6 and 7 and the Timing Characteristics in the Electrical Characteristics table show the operation of the interface. DB0–DB3, together with the output-only DB4–DB15, also output the 16-bit conversion result. All bits are high impedance when RD = 1 or CS = 1. DB3 (Int/Ext Reference) DB3 selects the internal or external reference. The POR default = 0. 0 = internal reference, REFIO internally driven through a 10kΩ resistor, bypass with 0.1µF capacitor to AGND. 1 = external reference, drive REFIO with a high-quality reference. DB2 (Output Data Format) DB2 selects the output data format. The POR default = 0. 0 = offset binary. 1 = two’s complement. DB1 (Reserved) Set to 0 for normal operation. 0 = normal operation. 1 = reserved; do not use. DB0 (CONVST Mode) DB0 selects the acquisition mode. The POR default = 0. 0 = CONVST controls the acquisition and conversion. Drive CONVST low to start acquisition. The rising edge of CONVST begins the conversion. 1 = acquisition mode starts as soon as the previous conversion is complete. The rising edge of CONVST begins the conversion. Programming the Configuration Register To program the configuration register, bring the CS and WR low and apply the required configuration data on DB3–DB0 of the bus and then raise WR once to save changes. 12 Table 1. Configuration Register DB3 DB2 DB1 DB0 Int/Ext Reference Output Data Format Reserved CONVST Mode Starting a Conversion CONVST initiates conversions. The MAX11044/ MAX11045/MAX11046 provide two acquisition modes set through the configuration register. Allow a quiet time (tQ) of 500ns prior to the start of conversion to avoid any noise interference during readout or write operations from corrupting a sample. In default mode (DB0 = 0), drive CONVST low to place the MAX11044/MAX11045/MAX11046 into acquisition mode. All the input switches are closed and the internal T/H circuits track the respective input voltage. Keep the CONVST signal low for at least 1µs (tACQ) to enable proper settling of the sampled voltages. On the rising edge of CONVST, the switches are opened and the MAX11044/MAX11045/MAX11046 begin the conversion on all the samples in parallel. EOC remains high until the conversion is completed. In the second mode (DB0 = 1), the MAX11044/ MAX11045/MAX11046 enter acquisition mode as soon as the previous conversion is completed. CONVST rising edge initiates the next sample and conversion sequence. CONVST needs to be low for at least 20ns to be valid. Provide adequate time for acquisition and the requisite quiet time in both modes to achieve accurate sampling and maximum performance of the MAX11044/ MAX11045/MAX11046. Reading Conversion Results The CS and RD are active-low, digital inputs that control the readout through the 16-bit, parallel, 20MHz data bus (D0–D15). After EOC transitions low, read the conversion data by driving CS and RD low. Each low period of RD presents the next channel’s result. When CS and RD are high, the data bus is high impedance. CS may be driven high between individual channel readouts or left low during the entire 8-channel readout. Reference Internal Reference The MAX11044/MAX11045/MAX11046 feature a precision, low-drift, internal bandgap reference. Bypass REFIO with a 0.1µF capacitor to AGND to reduce noise. The REFIO output voltage may be used as a reference for other circuits. The output impedance of REFIO is 10kΩ. Drive only high impedance circuits or buffer externally when using REFIO to drive external circuitry. ______________________________________________________________________________________ 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs Reference Buffer The MAX11044/MAX11045/MAX11046 have a built-in reference buffer to provide a low-impedance reference source to the SAR converters. This buffer is used in both internal and external reference mode. The reference buffer output feeds five RDC pins. The RDC pins should be all connected together on the PCB. The reference buffer is externally compensated and requires at least 10µF on the RDC node. For best performance, provide a total of at least 80µF on the RDC outputs. Transfer Functions Figures 8 and 9 show the transfer functions for all the formats and devices. Code transitions occur halfway between successive-integer LSB values. Layout, Grounding, and Bypassing For best performance use PCBs with ground planes. Ensure that digital and analog signal lines are separated from each other. Do not run analog and digital lines parallel to one another (especially clock lines), and avoid running digital lines underneath the ADC package. A single solid GND plane configuration with digital signals routed from one direction and analog signals from the other pro- CS (USER SUPPLIED) t5 t3 vides the best performance. Connect DGND, AGND, and AGNDS pins on the MAX11044/MAX11045/MAX11046 to this ground plane. Keep the ground return to the power supply for this ground low impedance and as short as possible for noise-free operation. To achieve the highest performance, connect all the RDC pins (22, 28, 36, 43, and 49) to a local RDC plane on the PCB. A total of at least 80µF of capacitance should be placed on this RDC plane. If two capacitors are used, place each as close as possible to pins 22 and 49. If four capacitors are used, place each as close as possible to pins 22, 28, 43, and 49. For example, two 47µF, 10V X5R capacitors in 1210 case size can be placed as close as possible to pins 22 and 49 will provide excellent performance. Alternatively, four 22µF, 10V X5R capacitors in 1210 case size placed as close as possible to pins 22, 28, 43, and 49 will also provide good performance. Ensure that each capacitor is connected directly into the GND plane with an independent via. If Y5U or Z5U ceramics are used, be aware of the highvoltage coefficient these capacitors exhibit and select higher voltage rating capacitors to ensure that at least 80µF of capacitance is on the RDC plane when the plane is driven to 4.096V by the built-in reference buffer. For example, a 22µF X5R with a 10V rating is approximately 20µF at 4.096V, whereas, the same capacitor in Y5U ceramic is just 13µF. However, a Y5U 22µF capacitor with a 25V rating cap is approximately 20µF at 4.096V. CS (USER SUPPLIED) t11 RD (USER SUPPLIED) WR (USER SUPPLIED) t6 t13 t12 t7 D0–D15 (USER SUPPLIED) t10 t9 t8 t4 D0–D15 Sn Sn + 1 CONFIGURATION REGISTER Figure 4. Programming Configuration-Register Timing Requirements Figure 5. Readout Timing Requirements ______________________________________________________________________________________ 13 MAX11044/MAX11045/MAX11046 External Reference Set the configuration register to disable the internal reference and drive REFIO with a high-quality external reference. To avoid signal degradation, ensure that the integrated reference noise applied to REFIO is less than 10µV in the bandwidth of up to 50kHz. MAX11044/MAX11045/MAX11046 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs SAMPLE tCON tACQ CONVST t1 EOC tO tQ CS RD D0–D15 S0 S1 S6 S7 Figure 6. Conversion Timing Diagram (DB0 = 0) SAMPLE tCON tACQ CONVST t2 EOC tO tQ CS RD D0–D15 S0 S1 S6 S7 Figure 7. Conversion Timing Diagram (DB0 = 1) 14 ______________________________________________________________________________________ 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs Typical Application Circuits Power-Grid Protection Figure 10 shows a typical power-grid protection application. DSP Motor Control Figure 11 shows a typical DSP motor control application. Definitions Integral Nonlinearity (INL) INL is the deviation of the values on an actual transfer function from a straight line. For these devices, this straight line is a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. OUTPUT CODE (hex) 7FFE 0001 5 x VREF 4.096 ZS = 0 -5 x VREF -FS = 4.096 +FS - (-FS) LSB = 65,536 +FS = Offset Error For the MAX11044/MAX11045/MAX11046, the offset error is defined at code transition 0x8000 to 0x8001 in offset binary encoding and 0x0000 to 0x0001 for two’s complement encoding. The offset code transitions should occur with an analog input voltage of exactly 0.5 x (10/4.096) x VREF/65,536 above GND. The offset error is defined as the deviation between the actual analog input voltage required to produce the offset code transition and the ideal analog input of 0.5 x (10/4.096) x VREF/65,536 above GND, expressed in LSBs. Gain Error Gain error is defined as the difference between the change in analog input voltage required to produce a top code transition minus a bottom code transition, subtracted from the ideal change in analog input voltage on (10/4.096) x V REF x (65,534/65,536). For the MAX11044/MAX11045/MAX11046, top code transition is 0x7FFE to 0x7FFF in two’s complement mode and 0xFFFE to 0xFFFF in offset binary mode. The bottom code transition is 0x8000 and 0x8001 in two’s complement FULL-SCALE TRANSITION FFFF FFFE 0000 FFFF V x 32,768 CODE = IN VREFIO 5 4.096 FFFE 8001 OUTPUT CODE (hex) 7FFF Differential Nonlinearity (DNL) DNL is the difference between an actual step width and the ideal value of 1 LSB. For these devices, the DNL of each digital output code is measured and the worst-case value is reported in the Electrical Characteristics table. A DNL error specification of greater than -1 LSB guarantees no missing codes and a monotonic transfer function. For example, -0.9 LSB guarantees no missing code while -1.1 LSB results in missing code. 8001 +FS = ZS = LSB = FULL-SCALE TRANSITION -5 x VREF 4.096 +FS - (-FS) 65,536 8000 7FFF 7FFE V x 32,768 CODE = IN + 32,768 VREFIO 5 4.096 0001 8000 5 x VREF 4.096 0000 -FS 0 -FS + 0.5 x LSB +FS - 1.5 x LSB INPUT VOLTAGE (LSB) Figure 8. Two’s Complement Transfer Function +FS -FS 0 -FS + 0.5 x LSB +FS - 1.5 x LSB INPUT VOLTAGE (LSB) +FS Figure 9. Offset-Binary Transfer Function ______________________________________________________________________________________ 15 MAX11044/MAX11045/MAX11046 Bypass AVDD and DVDD to the ground plane with 0.1µF ceramic chip capacitors on each pin as close as possible to the device to minimize parasitic inductance. Add at least one bulk 10µF decoupling capacitor to AVDD and DVDD per PCB. Interconnect all of the AVDD inputs and DVDD inputs using two solid power planes. For best performance, bring the AVDD power plane in on the analog interface side of the MAX11044/ MAX11045/MAX11046 and the DVDD power plane from the digital interface side of the device. For acquisition periods near minimum (1µs) use a 1nF C0G ceramic chip capacitor between each of the channel inputs to the ground plane as close as possible to the MAX11044/MAX11045/MAX11046. This capacitor reduces the inductance seen by the sampling circuitry and reduces the voltage transient seen by the input source circuit. MAX11044/MAX11045/MAX11046 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs VOLTAGE TRANSFORMER PHASE 1 OPT ADC OPT ADC CURRENT TRANSFORMER VN NEUTRAL ADC IN ADC LOAD 1 MAX11046 LOAD 2 LOAD 3 I3 V3 I2 ADC ADC PHASE 2 V2 ADC ADC PHASE 3 Figure 10. Power-Grid Protection 16 ______________________________________________________________________________________ 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs MAX11044/MAX11045/MAX11046 DSP-BASED DIGITAL PROCESSING ENGINE MAX11046 16-BIT ADC IGBT CURRENT DRIVERS 16-BIT ADC 16-BIT ADC 16-BIT ADC 16-BIT ADC IPHASE1 IPHASE3 IPHASE2 3-PHASE ELECTRIC MOTOR POSITION ENCODER Figure 11. DSP Motor Control ______________________________________________________________________________________ 17 MAX11044/MAX11045/MAX11046 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs mode and 0x0000 and 0x0001 in offset binary mode. For the MAX11044/MAX11045/MAX11046, the analog input voltage to produce these code transitions is measured and the gain error is computed by subtracting (10/4.096) x VREF x (65,534/65,536) from this measurement. Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization noise error only and results directly from the ADC’s resolution (N bits): SNR = (6.02 x N + 1.76)dB where N = 16 bits. In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components not including the fundamental, the first five harmonics, and the DC offset. Signal-to-Noise Plus Distortion (SINAD) SINAD is the ratio of the fundamental input frequency’s RMS amplitude to the RMS equivalent of all the other ADC output signals: ⎡ ⎤ SignalRMS SINAD(dB) = 10 × log ⎢ ⎥ ( + ) Noise Distortion RMS ⎦ ⎣ Effective Number of Bits (ENOB) The ENOB indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the full-scale range of the ADC, calculate the ENOB as follows: ENOB = SINAD − 1.76 6.02 Total Harmonic Distortion (THD) THD is the ratio of the RMS of the first five harmonics of the input signal to the fundamental itself. This is: expressed as: ⎡ ⎤ V 22 + V 32 + V 4 2 + V 52 ⎥ THD = 20 × log ⎢ ⎢ ⎥ V1 ⎣⎢ ⎦⎥ where V1 is the fundamental amplitude and V2 through V5 are the 2nd- through 5th-order harmonics. 18 Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest frequency component. Aperture Delay Aperture delay (tAD) is the time delay from the sampling clock edge to the instant when an actual sample is taken. Aperture Jitter Aperture jitter (tAJ) is the sample-to-sample variation in aperture delay. Channel-to-Channel Isolation Channel-to-channel isolation indicates how well each analog input is isolated from the other channels. Channel-to-channel isolation is measured by applying DC to channels 1 to 7, while a -0.4dBFS sine wave at 60Hz is applied to channel 0. A 10ksps FFT is taken for channel 0 and channel 1. Channel-to-channel isolation is expressed in dB as the power ratio of the two 60Hz magnitudes. Small-Signal Bandwidth A small -20dBFS analog input signal is applied to an ADC in a manner that ensures that the signal’s slew rate does not limit the ADC’s performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased 3dB. Full-Power Bandwidth A large -0.5dBFS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3dB. This point is defined as fullpower input bandwidth frequency. Positive Full-Scale Error The error in the input voltage that causes the last code transition of FFFE to FFFF (hex) (in default offset binary mode) or 7FFE to 7FFF (hex) (in two’s complement mode) from the ideal input voltage of 32,766.5 x (5/4.096) x (VREFIO/65,536) after correction for offset error. Negative Full-Scale Error The error in the input voltage that causes the first code transition of 0000 to 0001 (hex) (in default offset binary mode) or 8000 to 8001 (hex) (in two’s complement mode) from the ideal input voltage of -32,767.5 x (5/4.096) x (VREFIO/65,536) after correction for offset error. ______________________________________________________________________________________ 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs PROCESS: BiCMOS For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 56 TQFN-EP T5688+2 21-0135 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX11044/MAX11045/MAX11046 Package Information Chip Information