19-3052; Rev 3; 8/04 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges The MAX1304–MAX1306/MAX1308–MAX1310/MAX1312– MAX1314 12-bit, analog-to-digital converters (ADCs) offer eight, four, or two independent input channels. Independent track-and-hold (T/H) circuitry provides simultaneous sampling for each channel. The MAX1304/ MAX1305/MAX1306 provide a 0 to +5V input range with ±6V fault-tolerant inputs. The MAX1308/MAX1309/ MAX1310 provide a ±5V input range with ±16.5V fault-tolerant inputs. The MAX1312/MAX1313/MAX1314 have a ±10V input range with ±16.5V fault-tolerant inputs. These ADCs convert two channels in 0.9µs, and up to eight channels in 1.98µs, with an 8-channel throughput of 456ksps per channel. Other features include a 20MHz T/H input bandwidth, internal clock, internal (+2.5V) or external (+2.0V to +3.0V) reference, and power-saving modes. A 20MHz, 12-bit, bidirectional parallel data bus provides the conversion results and accepts digital inputs that activate each channel individually. All devices operate from a +4.75V to +5.25V analog supply and a +2.7V to +5.25V digital supply and consume 57mA total supply current when fully operational. Each device is available in a 48-pin 7mm x 7mm TQFP package and operates over the extended -40°C to +85°C temperature range. Applications SIN/COS Position Encoder Features ♦ Up to Eight Channels of Simultaneous Sampling 8ns Aperture Delay 100ps Channel-to-Channel T/H Match ♦ Extended Input Ranges 0 to +5V (MAX1304/MAX1305/MAX1306) -5V to +5V (MAX1308/MAX1309/MAX1310) -10V to +10V (MAX1312/MAX1313/MAX1314) ♦ Fast Conversion Time One Channel in 0.72µs Two Channels in 0.9µs Four Channels in 1.26µs Eight Channels in 1.98µs ♦ High Throughput 1075ksps/Channel for One Channel 901ksps/Channel for Two Channels 680ksps/Channel for Four Channels 456ksps/Channel for Eight Channels ♦ ±1 LSB INL, ±0.9 LSB DNL (max) ♦ 84dBc SFDR, -86dBc THD, 71dB SINAD, fIN = 500kHz at 0.4dBFS ♦ 12-Bit, 20MHz, Parallel Interface ♦ Internal or External Clock ♦ +2.5V Internal Reference or +2.0V to +3.0V External Reference Power-Grid Synchronization ♦ +5V Analog Supply, +3V to +5V Digital Supply 55mA Analog Supply Current 1.3mA Digital Supply Current Shutdown and Power-Saving Modes Power-Factor Monitoring ♦ 48-Pin TQFP Package (7mm x 7mm Footprint) Multiphase Motor Control Multiphase Power Monitoring Vibration and Waveform Analysis Selector Guide PART Ordering Information INPUT RANGE (V) CHANNEL COUNT TEMP RANGE PIN-PACKAGE MAX1304ECM 0 to +5 8 MAX1304ECM -40°C to +85°C 48 TQFP MAX1305ECM 0 to +5 4 MAX1305ECM -40°C to +85°C 48 TQFP MAX1306ECM 0 to +5 2 MAX1306ECM -40°C to +85°C 48 TQFP MAX1308ECM ±5 8 MAX1308ECM -40°C to +85°C 48 TQFP MAX1309ECM ±5 4 MAX1309ECM -40°C to +85°C 48 TQFP MAX1310ECM ±5 2 MAX1310ECM -40°C to +85°C 48 TQFP MAX1312ECM ±10 8 MAX1312ECM -40°C to +85°C 48 TQFP MAX1313ECM ±10 4 MAX1313ECM -40°C to +85°C 48 TQFP MAX1314ECM ±10 2 MAX1314ECM -40°C to +85°C 48 TQFP PART Pin Configurations appear at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing delivery, and ordering information please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 General Description MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges ABSOLUTE MAXIMUM RATINGS AVDD to AGND .........................................................-0.3V to +6V DVDD to DGND.........................................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V CH0–CH7, I.C. to AGND (MAX1304/MAX1305/MAX1306)....±6V CH0–CH7, I.C. to AGND (MAX1308/MAX1309/MAX1310)..±16.5V CH0–CH7, I.C. to AGND (MAX1312/MAX1313/MAX1314)..±16.5V D0–D11 to DGND ....................................-0.3V to (DVDD + 0.3V) EOC, EOLC, RD, WR, CS to DGND .........-0.3V to (DVDD + 0.3V) CONVST, CLK, SHDN, CHSHDN to DGND ..-0.3V to (DVDD + 0.3V) INTCLK/EXTCLK to AGND .......................-0.3V to (AVDD + 0.3V) REFMS, REF, MSV to AGND.....................-0.3V to (AVDD + 0.3V) REF+, COM, REF- to AGND.....................-0.3V to (AVDD + 0.3V) Maximum Current into Any Pin Except AVDD, DVDD, AGND, DGND ...........................................................................±50mA Continuous Power Dissipation (TA = +70°C) TQFP (derate 22.7mW/°C above +70°C) ................1818.2mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVDD = +5V, DVDD = +3V, AGND = DGND = 0, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ = CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. See Figures 3 and 4.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE (Note 1) Resolution N 12 Bits Integral Nonlinearity INL (Note 2) ±0.5 ±1.0 LSB Differential Nonlinearity DNL No missing codes (Note 2) ±0.3 ±0.9 LSB Unipolar, 0x000 to 0x001 ±3 ±16 Bipolar, 0xFFF to 0x000 ±3 ±16 Unipolar, between all channels ±9 ±20 Bipolar, between all channels ±9 ±20 Offset Error Offset-Error Matching Offset-Error Temperature Drift Unipolar, 0x000 to 0x001 7 Bipolar, 0xFFF to 0x000 7 Gain Error Gain-Error Matching Between all channels Gain-Error Temperature Drift LSB LSB ppm/°C ±2 ±16 ±3 ±14 4 LSB LSB ppm/°C DYNAMIC PERFORMANCE at fIN = 500kHz, AIN = -0.4dBFS (Note 2) Signal-to-Noise Ratio Signal-to-Noise Plus Distortion SNR 68 71 dB SINAD 68 71 dB Total Harmonic Distortion THD Spurious-Free Dynamic Range SFDR -86 Channel-to-Channel Isolation 80 -80 dBc 84 dBc 86 dB ANALOG INPUTS (CH0 through CH7) Input Voltage 2 VCH MAX1304/MAX1305/MAX1306 0 +5 MAX1308/MAX1309/MAX1310 -5 +5 MAX1312/MAX1313/MAX1314 -10 +10 _______________________________________________________________________________________ V 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges (AVDD = +5V, DVDD = +3V, AGND = DGND = 0, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ = CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. See Figures 3 and 4.) PARAMETER SYMBOL CONDITIONS MIN MAX1304/MAX1305/MAX1306 Input Resistance (Note 3) RCH ICH 8.66 MAX1312/MAX1313/MAX1314 14.26 MAX1308/MAX1309/MAX1310 MAX1312/MAX1313/MAX1314 Input Capacitance MAX UNITS 7.58 MAX1308/MAX1309MAX1310 MAX1304/MAX1305/MAX1306 Input Current (Note 3) TYP VCH = +5V VCH = 0V 0.54 -0.157 -0.12 -1.16 -0.87 -1.13 -0.85 VCH = +5V VCH = -5V 0.29 VCH = +10V VCH = -10V 0.56 CCH kΩ 0.72 0.39 mA 0.74 15 pF TRACK/HOLD External-Clock Throughput Rate (Note 4) Internal-Clock Throughput Rate (Note 4, Table 1) fTH fTH One channel selected for conversion 1075 Two channels selected for conversion 901 Four channels selected for conversion 680 Eight channels selected for conversion 456 One channel selected for conversion 983 Two channels selected for conversion 821 Four channels selected for conversion 618 Eight channels selected for conversion 413 ksps ksps Small-Signal Bandwidth 20 MHz Full-Power Bandwidth 20 MHz 8 ns Aperture Delay tAD Aperture-Delay Matching Aperture Jitter tAJ 100 ps 50 psRMS INTERNAL REFERENCE REF Output Voltage VREF 2.475 Reference Output-Voltage Temperature Drift 2.500 2.525 ppm/°C 30 REFMS Output Voltage VREFMS REF+ Output Voltage VREF+ 3.850 V COM Output Voltage VCOM 2.600 V REF- Output Voltage VREF- 1.350 V VREF+ VREF- 2.500 V Differential Reference Voltage 2.475 2.500 V 2.525 V _______________________________________________________________________________________ 3 MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 ELECTRICAL CHARACTERISTICS (continued) MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges ELECTRICAL CHARACTERISTICS (continued) (AVDD = +5V, DVDD = +3V, AGND = DGND = 0, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ = CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. See Figures 3 and 4.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX 2.0 2.5 3.0 UNITS EXTERNAL REFERENCE (REF and REFMS are externally driven) REF Input Voltage Range VREF REF Input Resistance RREF (Note 5) REF Input Capacitance REFMS Input Voltage Range VREFMS REFMS Input Resistance RREFMS 2.0 kΩ 15 pF 2.5 (Note 6) REFMS Input Capacitance V 5 3.0 V 5 kΩ 15 pF REF+ Output Voltage VREF+ VREF = +2.5V 3.850 V COM Output Voltage VCOM VREF = +2.5V 2.600 V VREF- VREF = +2.5V 1.350 V VREF+ VREF- VREF = +2.5V 2.500 V REF- Output Voltage Differential Reference Voltage DIGITAL INPUTS (D0–D7, RD, WR, CS, CLK, SHDN, CHSHDN, CONVST) Input-Voltage High VIH Input-Voltage Low VIL 0.7 x DVDD V 0.3 x DVDD Input Hysteresis 20 Input Capacitance CIN Input Current IIN mV 15 VIN = 0 or DVDD V pF 0.02 ±1 µA CLOCK-SELECT INPUT (INTCLK/EXTCLK) Input-Voltage High VIH Input-Voltage Low VIL 0.7 x AVDD V 0.3 x AVDD V DIGITAL OUTPUTS (D0–D11, EOC, EOLC) Output-Voltage High VOH ISOURCE = 0.8mA, Figure 1 Output-Voltage Low VOL ISINK = 1.6mA, Figure 1 DVDD - 0.6 V D0–D11 Tri-State Leakage Current RD = high or CS = high 0.06 D0–D11 Tri-State Output Capacitance RD = high or CS = high 15 0.4 V 1 µA pF POWER SUPPLIES Analog Supply Voltage AVDD 4.75 5.25 V Digital Supply Voltage DVDD 2.70 5.25 V Analog Supply Current 4 IAVDD MAX1304/MAX1305/MAX1306, all channels selected 55 60 MAX1308/MAX1309/MAX1310, all channels selected 54 60 MAX1312/MAX1313/MAX1314, all channels selected 54 60 _______________________________________________________________________________________ mA 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges (AVDD = +5V, DVDD = +3V, AGND = DGND = 0, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ = CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. See Figures 3 and 4.) PARAMETER SYMBOL Digital Supply Current (CLOAD = 100pF) (Note 7) IDVDD CONDITIONS MIN TYP MAX MAX1304/MAX1305/MAX1306, all channels selected 1.3 2.6 MAX1308/MAX1309/MAX1310, all channels selected 1.3 2.6 MAX1312/MAX1313/MAX1314, all channels selected 1.3 2.6 Shutdown Current (Note 8) IAVDD SHDN = DVDD, VCH = float 0.6 10 IDVDD SHDN = DVDD, RD = WR = high 0.02 1 Power-Supply Rejection Ratio PSRR AVDD = +4.75V to +5.25V 50 Internal clock, Figure 7 800 External clock, Figure 8 12 Internal clock, Figure 7 200 External clock, Figure 8 3 UNITS mA µA dB TIMING CHARACTERISTICS (Figure 1) Time to First Conversion Result tCONV Time to Subsequent Conversions tNEXT CONVST Pulse-Width Low (Acquisition Time) tACQ (Note 9) Figures 6–10 0.1 900 ns CLK Cycles 225 ns CLK Cycles 1000.0 µs CS Pulse Width tCS Figure 6 30 ns RD Pulse-Width Low tRDL Figures 7, 8, 9 30 ns RD Pulse-Width High tRDH Figures 7, 8, 9 30 ns WR Pulse-Width Low tWRL Figure 6 30 CS to WR tCTW Figure 6 WR to CS tWTC CS to RD tCTR RD to CS ns (Note 10) ns Figure 6 (Note 10) ns Figures 7, 8, 9 (Note 10) ns tRTC Figures 7, 8, 9 (Note 10) ns Data Access Time (RD Low to Valid Data) tACC Figures 7, 8, 9 Bus Relinquish Time (RD High) tREQ Figures 7, 8, 9 5 30 ns 30 ns CLK Rise to EOC Delay tEOCD Figure 8 20 CLK Rise to EOLC Fall Delay tEOLCD Figure 8 20 ns 20 ns 1 CLK Cycle CONVST Fall to EOLC Rise Delay tCVEOLCD Figures 7, 8, 9 Internal clock, Figure 7 EOC Pulse Width tEOC External clock, Figure 8 50 ns ns _______________________________________________________________________________________ 5 MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 ELECTRICAL CHARACTERISTICS (continued) MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges ELECTRICAL CHARACTERISTICS (continued) (AVDD = +5V, DVDD = +3V, AGND = DGND = 0, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ = CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. See Figures 3 and 4.) PARAMETER SYMBOL CONDITIONS MIN Input-Data Setup Time tDTW Figure 6 10 Input-Data Hold Time tWTD Figure 6 10 External CLK Period tCLK Figures 8, 9 TYP MAX UNITS ns ns 0.05 10.00 µs External CLK High Period tCLKH Logic sensitive to rising edges, Figures 8, 9 20 ns External CLK Low Period tCLKL Logic sensitive to rising edges, Figures 8, 9 20 ns External Clock Frequency fCLK (Note 11) 0.1 Internal Clock Frequency fINT CONVST High to CLK Edge tCNTC 20 15 Figures 8, 9 20 MHz MHz ns Note 1: For the MAX1304/MAX1305/MAX1306, VIN = 0 to +5V. For the MAX1308/MAX1309/MAX1310, VIN = -5V to +5V. For the MAX1312/MAX1313/MAX1314, VIN = -10V to +10V. Note 2: All channel performance is guaranteed by correlation to a single channel test. Note 3: The analog input resistance is terminated to an internal bias point (Figure 5). Calculate the analog input current using: VCH _ − VBIAS RCH _ ICH _ = for VCH within the input voltage range. Note 4: Throughput rate is given per channel. Throughput rate is a function of clock frequency (fCLK). The external clock throughput rate is specified with fCLK = 16.67MHz and the internal clock throughput rate is specified with fCLK = 15MHz. See the Data Throughput section for more information. Note 5: The REF input resistance is terminated to an internal +2.5V bias point (Figure 2). Calculate the REF input current using: IREF = VREF − 2.5V RREF for VREF within the input voltage range. Note 6: The REFMS input resistance is terminated to an internal +2.5V bias point (Figure 2). Calculate the REFMS input current using: IREFMS = VREFMS − 2.5V RREFMS for VREFMS within the input voltage range. Note 7: All analog inputs are driven with a -0.4dBFS 500kHz sine wave. Note 8: Shutdown current is measured with the analog input floating. The large amplitude of the maximum shutdown current specification is due to automated test equipment limitations. Note 9: CONVST must remain low for at least the acquisition period. The maximum acquisition time is limited by internal capacitor droop. Note 10: CS to WR and CS to RD are internally AND together. Setup and hold times do not apply. Note 11: Minimum CLK frequency is limited only by the internal T/H droop rate. Limit the time between the rising edge of CONVST and the falling edge of EOLC to a maximum of 1ms. 6 _______________________________________________________________________________________ 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges (AVDD = +5V, DVDD = +3V, AGND = DGND = 0, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ = CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), fIN = 500kHz, AIN = -0.4dBFS. TA = +25°C, unless otherwise noted.) (Figures 3 and 4) DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE 0.6 0.8 0.6 0.4 0.2 0.2 DNL (LSB) 0.4 0 0 -0.2 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 512 1024 1536 2048 2560 3072 3584 4096 DIGITAL OUTPUT CODE DIGITAL OUTPUT CODE OFFSET ERROR vs. ANALOG SUPPLY VOLTAGE OFFSET ERROR vs. TEMPERATURE 16 MAX1304 toc03 1.0 0.8 0.6 MAX1304 toc04 0 12 8 0.4 OFFSET ERROR (LSB) OFFSET ERROR (LSB) MAX1304 toc02 0.8 INL (LSB) 1.0 MAX1304 toc01 1.0 0.2 0 -0.2 -0.4 4 0 -4 -8 -0.6 -12 -0.8 -1.0 -16 4.7 4.8 4.9 5.0 5.1 5.2 5.3 -40 -15 AVDD (V) GAIN ERROR vs. ANALOG SUPPLY VOLTAGE 85 16 MAX1304 toc06 0 60 GAIN ERROR vs. TEMPERATURE MAX1304 toc05 1 10 35 TEMPERATURE (°C) 12 GAIN ERROR (LSB) GAIN ERROR (LSB) 8 -1 -2 -3 4 0 -4 -8 -4 -12 -5 -16 4.7 4.8 4.9 5.0 AVDD (V) 5.1 5.2 5.3 -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 7 MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 Typical Operating Characteristics Typical Operating Characteristics (continued) (AVDD = +5V, DVDD = +3V, AGND = DGND = 0, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ = CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), fIN = 500kHz, AIN = -0.4dBFS. TA = +25°C, unless otherwise noted.) (Figures 3 and 4) SMALL-SIGNAL BANDWIDTH vs. ANALOG INPUT FREQUENCY 0 2 MAX1304 toc07 AIN = -20dBFS AIN = -0.5dBFS 0 -2 GAIN (dB) -4 -6 -4 -6 -8 -8 -10 -10 -12 -12 0.1 1 100 10 0.1 1 ANALOG INPUT FREQUENCY (MHz) FFT PLOT (2048-POINT DATA RECORD) OUTPUT HISTOGRAM (DC INPUT) fTH = 1.04167Msps fIN = 500kHz AIN = -0.05dBFS SNR = 70.7dB SINAD = 70.6dB THD = -87.5dBc SFDR = 87.1dBc -20 -30 -40 -50 5497 5000 4000 COUNTS -10 6000 MAX1304 toc09 0 -60 -70 3000 2000 1611 -80 1084 1000 -90 -100 0 0 0 -110 0 100 200 300 FREQUENCY (kHz) 8 100 10 ANALOG INPUT FREQUENCY (MHz) MAX1304 toc10 GAIN (dB) -2 MAX1304 toc08 LARGE-SIGNAL BANDWIDTH vs. ANALOG INPUT FREQUENCY 2 AMPLITUDE (dBFS) MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges 400 500 2044 2045 2046 2047 2048 DIGITAL OUTPUT CODE _______________________________________________________________________________________ 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges (AVDD = +5V, DVDD = +3V, AGND = DGND = 0, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ = CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), fIN = 500kHz, AIN = -0.4dBFS. TA = +25°C, unless otherwise noted.) (Figures 3 and 4) SIGNAL-TO-NOISE PLUS DISTORTION vs. CLOCK FREQUENCY SIGNAL-TO-NOISE RATIO vs. CLOCK FREQUENCY 78 76 78 76 74 SINAD (dB) 72 70 68 72 70 68 66 66 64 64 62 62 60 60 0 5 10 15 20 0 25 5 10 15 20 fCLK (MHz) fCLK (MHz) TOTAL HARMONIC DISTORTION vs. CLOCK FREQUENCY SPURIOUS-FREE DYNAMIC RANGE vs. CLOCK FREQUENCY 100 MAX1304 toc13 -60 -65 95 90 -75 85 SFDR (dBc) -70 -80 25 MAX1304 toc14 SNR (dB) 74 THD (dBc) MAX1304 toc12 80 MAX1304 toc11 80 80 -85 75 -90 70 -95 65 60 -100 0 5 10 15 fCLK (MHz) 20 25 0 5 10 15 20 25 fCLK (MHz) _______________________________________________________________________________________ 9 MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 Typical Operating Characteristics (continued) Typical Operating Characteristics (continued) (AVDD = +5V, DVDD = +3V, AGND = DGND = 0, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ = CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), fIN = 500kHz, AIN = -0.4dBFS. TA = +25°C, unless otherwise noted.) (Figures 3 and 4) SIGNAL-TO-NOISE PLUS DISTORTION vs. REFERENCE VOLTAGE SIGNAL-TO-NOISE RATIO vs. REFERENCE VOLTAGE 74 73 74 73 72 SINAD (dB) 72 SNR (dB) MAX1304 toc16 75 MAX1304 toc15 75 71 70 69 71 70 69 68 68 67 67 66 66 65 65 2.0 2.2 2.4 2.6 2.8 2.0 3.0 2.2 2.4 2.6 2.8 3.0 VREF (V) VREF (V) TOTAL HARMONIC DISTORTION vs. REFERENCE VOLTAGE SPURIOUS-FREE DYNAMIC RANGE vs. REFERENCE VOLTAGE -72 -74 MAX1304 toc18 100 MAX1304 toc17 -70 95 -76 90 -78 SFDR (dBc) THD (dBc) MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges -80 -82 85 80 -84 -86 75 -88 -90 70 2.0 2.2 2.4 2.6 VREF (V) 10 2.8 3.0 2.0 2.2 2.4 2.6 2.8 VREF (V) ______________________________________________________________________________________ 3.0 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges TA = +85°C 56 2.0 MAX1304 toc19 57 CLOAD = 50pF 1.8 TA = +85°C 1.6 IDVDD (mA) IAVDD (mA) 55 TA = +25°C 54 TA = +25°C 1.4 TA = -40°C 1.2 TA = -40°C 53 1.0 52 0.8 0.6 51 4.7 4.8 4.9 5.0 5.1 2.5 5.3 5.2 3.0 3.5 4.0 4.5 5.5 5.0 DVDD (V) AVDD (V) DIGITAL SHUTDOWN CURRENT vs. DIGITAL SUPPLY VOLTAGE ANALOG SHUTDOWN CURRENT vs. ANALOG SUPPLY VOLTAGE 680 660 MAX1304 toc22 22 MAX1304 toc21 700 20 640 18 620 IDVDD (nA) IAVDD (nA) MAX1304 toc20 DIGITAL SUPPLY CURRENT vs. DIGITAL SUPPLY VOLTAGE ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE 600 580 16 14 560 540 12 520 10 500 4.7 4.8 4.9 5.0 5.1 2.5 5.3 5.2 3.0 3.5 4.5 5.5 5.0 DIGITAL SUPPLY CURRENT vs. NUMBER OF CHANNELS SELECTED ANALOG SUPPLY CURRENT vs. NUMBER OF CHANNELS SELECTED CHSHDN = 0 55 MAX1304 toc24 1.0 MAX1304 toc23 60 CHSHDN = 0 0.9 0.8 0.7 IDVDD (mA) 50 IAVDD (mA) 4.0 DVDD (V) AVDD (V) 45 0.6 0.5 0.4 40 0.3 35 0.2 0.1 30 0 1 2 3 4 5 6 7 NUMBER OF CHANNELS SELECTED 8 0 1 2 3 4 5 6 7 8 NUMBER OF CHANNELS SELECTED ______________________________________________________________________________________ 11 MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 Typical Operating Characteristics (continued) (AVDD = +5V, DVDD = +3V, AGND = DGND = 0, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ = CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), fIN = 500kHz, AIN = -0.4dBFS. TA = +25°C, unless otherwise noted.) (Figures 3 and 4) Typical Operating Characteristics (continued) (AVDD = +5V, DVDD = +3V, AGND = DGND = 0, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ = CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), fIN = 500kHz, AIN = -0.4dBFS. TA = +25°C, unless otherwise noted.) (Figures 3 and 4) INTERNAL REFERENCE VOLTAGE INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE vs. TEMPERATURE MAX1304 toc26 2.5003 2.503 2.5002 2.502 2.5001 2.501 VREF (V) VREF (V) 2.504 MAX1304 toc25 2.5004 2.5000 2.500 2.4999 2.499 2.4998 2.498 2.4997 2.497 2.4996 2.496 4.7 4.8 4.9 5.0 5.1 5.3 5.2 -40 -15 AVDD (V) 85 60 820 MAX1304 toc28 800 800 tCONV tCONV 600 780 TIME (ns) TIME (ns) 35 INTERNAL CLOCK CONVERSION TIME vs. TEMPERATURE MAX1304 toc27 900 700 10 TEMPERATURE (°C) INTERNAL CLOCK CONVERSION TIME vs. ANALOG SUPPLY VOLTAGE 500 400 tNEXT 300 tNEXT 200 200 180 100 0 4.8 4.9 5.0 5.1 160 5.3 5.2 -40 -15 AVDD (V) ANALOG INPUT CHANNEL CURRENT vs. ANALOG INPUT CHANNEL VOLTAGE ANALOG INPUT CHANNEL CURRENT vs. ANALOG INPUT CHANNEL VOLTAGE MAX1304/MAX1305/MAX1306 1.5 2.5 2.0 1.0 1.5 0.5 0 -0.5 -6 -4 -2 0 VCH_ (V) 2 4 6 0 -1.0 -1.5 -2.5 -3.0 -2.0 0.5 -0.5 -2.0 -1.5 MAX1312/MAX1313/MAX1314 1.0 -1.0 -1.5 -1.0 85 60 2.0 ICH_ (mA) ICH_ (mA) 0 -0.5 12 MAX1308/MAX1309/MAX1310 1.5 1.0 0.5 35 ANALOG INPUT CHANNEL CURRENT vs. ANALOG INPUT CHANNEL VOLTAGE MAX1304 toc30 3.0 MAX1304 toc29 2.0 10 TEMPERATURE (°C) MAX1304 toc31 4.7 ICH_ (mA) MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges -2.0 -20 -15 -10 -5 0 VCH_ (V) 5 10 15 20 -20 -15 -10 -5 0 VCH_ (V) ______________________________________________________________________________________ 5 10 15 20 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges PIN MAX1304 MAX1308 MAX1312 MAX1305 MAX1309 MAX1313 MAX1306 MAX1310 MAX1314 NAME FUNCTION 1, 15, 17 1, 15, 17 1, 15, 17 AVDD Analog Power Input. AVDD is the power input for the analog section of the converter. Apply +5V to AVDD. Connect all AVDD pins together. See the Layout, Grounding, and Bypassing section for additional information. 2, 3, 14, 16, 23 2, 3, 14, 16, 23 2, 3, 14, 16, 23 AGND Analog Ground. AGND is the power return for AVDD. Connect all AGND pins together. 4 4 4 CH0 Channel 0 Analog Input 5 5 5 CH1 Channel 1 Analog Input 6 6 6 MSV Midscale Voltage Bypass. For the unipolar MAX1304/MAX1305/MAX1306, connect a 2.2µF and a 0.1µF capacitor from MSV to AGND. For the bipolar MAX1308/MAX1309/MAX1310/MAX1312/MAX1313/MAX1314, connect MSV to AGND. 7 7 — CH2 Channel 2 Analog Input 8 8 — CH3 Channel 3 Analog Input 9 — — CH4 Channel 4 Analog Input 10 — — CH5 Channel 5 Analog Input 11 — — CH6 Channel 6 Analog Input 12 — — CH7 Channel 7 Analog Input 13 13 13 Clock-Mode Select Input. Connect INTCLK/EXTCLK to AVDD to select the INTCLK/ internal clock. Connect INTCLK/EXTCLK to AGND to use an external clock EXTCLK connected to CLK. 18 18 18 REFMS 19 19 19 REF Midscale Reference Bypass or Input. REFMS connects through a 5kΩ resistor to the internal +2.5V bandgap reference buffer. For the MAX1304/MAX1305/MAX1306 unipolar devices, VREFMS is the input to the unity-gain buffer that drives MSV. MSV sets the midpoint of the input voltage range. For internal reference operation, bypass REFMS with a ≥0.01µF capacitor to AGND. For external reference operation, drive REFMS with an external voltage from +2V to +3V. For the MAX1308/MAX1309/MAX1310/MAX1312/MAX1313/MAX1314 bipolar devices, connect REFMS to REF. For internal reference operation, bypass the REFMS/REF node with a ≥0.01µF capacitor to AGND. For external reference operation, drive the REFMS/REF node with an external voltage from +2V to +3V. ADC Reference Bypass or Input. REF connects through a 5kΩ resistor to the internal +2.5V bandgap reference buffer. For internal reference operation, bypass REF with a ≥0.01µF capacitor. For external reference operation with the MAX1304/MAX1305/MAX1306 unipolar devices, drive REF with an external voltage from +2V to +3V. For external reference operation with the MAX1308/MAX1309/MAX1310/ MAX1312/MAX1313/MAX1314 bipolar devices, connect REFMS to REF and drive the REFMS/REF node with an external voltage from +2V to +3V. ______________________________________________________________________________________ 13 MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 Pin Description MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges Pin Description (continued) PIN MAX1304 MAX1308 MAX1312 MAX1305 MAX1309 MAX1313 MAX1306 MAX1310 MAX1314 NAME FUNCTION 20 20 20 REF+ Positive Reference Bypass. Bypass REF+ with a 0.1µF capacitor to AGND. Also bypass REF+ to REF- with a 2.2µF and a 0.1µF capacitor. VREF+ = VCOM + VREF / 2. 21 21 21 COM Reference Common Bypass. Bypass COM to AGND with a 2.2µF and a 0.1µF capacitor. VCOM = 13 / 25 x AVDD. 22 22 22 REF- Negative Reference Bypass. Bypass REF- with a 0.1µF capacitor to AGND. Also bypass REF- to REF+ with a 2.2µF and a 0.1µF capacitor. VREF+ = VCOM - VREF / 2. 24, 39 24, 39 24, 39 DGND Digital Ground. DGND is the power return for DVDD. Connect all DGND pins together. 25, 38 25, 38 25, 38 DVDD Digital Power Input. DVDD powers the digital section of the converter, including the parallel interface. Apply +2.7V to +5.25V to DVDD. Bypass DVDD to DGND with a 0.1µF capacitor. Connect all DVDD pins together. 26 26 26 D0 Digital I/O 0 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1. 27 27 27 D1 Digital I/O 1 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1. 28 28 28 D2 Digital I/O 2 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1. 29 29 29 D3 Digital I/O 3 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1. 30 30 30 D4 Digital I/O 4 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1. 31 31 31 D5 Digital I/O 5 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1. 32 32 32 D6 Digital I/O 6 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1. 33 33 33 D7 Digital I/O 7 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1. 34 34 34 D8 Digital Output 8 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1. 35 35 35 D9 Digital Output 9 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1. 36 36 36 D10 Digital Output 10 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1. 37 37 37 D11 Digital Output 11 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1. 40 40 40 EOC End-of-Conversion Output. EOC goes low to indicate the end of a conversion. It returns high on the next rising CLK edge or the falling CONVST edge. 41 41 41 EOLC End-of-Last-Conversion Output. EOLC goes low to indicate the end of the last conversion. It returns high when CONVST goes low for the next conversion sequence. 42 42 42 RD Read Input. Pulling RD low initiates a read command of the parallel data bus. WR Write Input. Pulling WR low initiates a write command for configuring the device with D0–D7. 43 14 43 43 ______________________________________________________________________________________ 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges PIN MAX1304 MAX1308 MAX1312 MAX1305 MAX1309 MAX1313 MAX1306 MAX1310 MAX1314 NAME FUNCTION 44 44 44 CS Chip-Select Input. Pulling CS low activates the digital interface. Forcing CS high places D0–D11 in high-impedance mode. 45 45 45 CONVST 46 46 46 CLK 47 47 47 SHDN Conversion Start Input. Driving CONVST high initiates the conversion process. The analog inputs are sampled on the rising edge of CONVST. External Clock Input. For external clock operation, connect INTCLK/EXTCLK to DGND and drive CLK with an external clock signal from 100kHz to 20MHz. For internal clock operation, connect INTCLK/EXTCLK to DVDD and connect CLK to DGND. Shutdown Input. Driving SHDN high initiates device shutdown. Connect SHDN to DGND for normal operation. Active-Low Analog-Input Channel-Shutdown Input. Drive CHSHDN low to power down analog inputs that are not selected for conversion in the configuration register. Drive CHSHDN high to power up all analog input CHSHDN channels regardless of whether they are selected for conversion in the configuration register. See the Channel Shutdown (CHSHDN) section for more information. 48 48 48 — 9, 10, 11, 12 7, 8, 9, 10, 11, 12 I.C. Internally connected. Connect I.C. to AGND. Detailed Description VDD IOL = 1.6mA 1.6V DEVICE PIN 100pF IOH = 0.8mA The MAX1304–MAX1306/MAX1308–MAX1310/MAX1312– MAX1314 are 12-bit ADCs. The devices offer 8, 4, or 2 independently selectable input channels, each with dedicated T/H circuitry. Simultaneous sampling of all active channels preserves relative phase information making these devices ideal for motor control and power monitoring. Three input ranges are available, 0 to +5V, ±5V and ±10V. The 0 to +5V devices provide ±6V faulttolerant inputs. The ±5V and ±10V devices provide ±16.5V fault-tolerant inputs. Two-channel conversion results are available in 0.9µs. Conversion results from all eight channels are available in 1.98µs. The 8-channel throughput is 456ksps per channel. Internal or external reference and clock capability offer great flexibility, and ease of use. A write-only configuration register can mask out unused channels and a shutdown feature reduces power. A 20MHz, 12-bit, parallel data bus outputs the conversion results. Figure 2 shows the functional diagram of these ADCs. Figure 1. Digital Load Test Circuit ______________________________________________________________________________________ 15 MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 Pin Description (continued) MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges MAX1304–MAX1306 MAX1308–MAX1310 MAX1312–MAX1314 AVDD CH0 DVDD D11 T/H 12-BIT ADC 8x1 MUX CH7 D8 8 x 12 SRAM OUTPUT DRIVERS T/H D7 D0 MSV CONFIGURATION REGISTER * WR CS REF+ COM REF- INTERFACE AND CONTROL RD CONVST SHDN 5kΩ INTCLK/EXTCLK REF CLK 5kΩ CHSHDN REFMS EOC 2.500V EOLC DGND AGND *SWITCH CLOSED ON UNIPOLAR DEVICES, OPEN ON BIPOLAR DEVICES Figure 2. Functional Diagram 16 ______________________________________________________________________________________ 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges DVDD 0.1µF 1 0.1µF 15 0.1µF 17 BIPOLAR CONFIGURATION 18 0.01µF 19 AVDD DGND AVDD CLK REFMS MAX1308 MAX1312 CONVST CS WR 0.1µF 20 REF+ 0.1µF 2.2µF RD EOLC 22 REF0.1µF SHDN MSV REF EOC 24, 39 GND 48 47 46 45 44 43 DIGITAL INTERFACE AND CONTROL 42 41 40 2.2µF D11 21 0.1µF GND +2.7V TO +5.25V 0.1µF AVDD CHSHDN 6 25, 38 MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 +5V COM D9 2, 3, 14, 16, 23 12 11 10 BIPOLAR ANALOG INPUTS 9 D10 37 36 35 34 AGND D8 CH7 D7 CH6 D6 CH5 D5 CH4 D4 30 8 CH3 7 CH2 5 CH1 4 CH0 13 INTCLK/EXTCLK D3 D2 33 32 31 PARALLEL DIGITAL OUTPUT 29 28 D1 27 D0 26 Figure 3. Typical Bipolar Operating Circuit ______________________________________________________________________________________ 17 MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges +5V 0.1µF 1 0.1µF 15 0.1µF 17 DVDD AVDD 25, 38 +2.7V TO +5.25V 0.1µF AVDD DGND AVDD 24, 39 GND 2.2µF 6 0.1µF MSV SHDN CLK 0.01µF UNIPOLAR CONFIGURATION CHSHDN 18 0.01µF 19 REFMS CONVST MAX1304 REF CS WR 0.1µF 20 RD REF+ 0.1µF 2.2µF EOLC EOC 22 48 47 46 45 44 43 DIGITAL INTERFACE AND CONTROL 42 41 40 REF0.1µF 2.2µF D11 21 0.1µF COM D10 D9 GND 2, 3, 14, 16, 23 12 11 10 UNIPOLAR ANALOG INPUTS AGND D8 CH7 D7 CH6 D6 CH5 D5 9 CH4 8 CH3 7 CH2 5 CH1 4 CH0 13 INTCLK/EXTCLK 37 36 35 34 33 32 31 PARALLEL DIGITAL OUTPUT D4 30 D3 D2 29 28 D1 27 D0 26 Figure 4. Typical Unipolar Operating Circuit 18 ______________________________________________________________________________________ 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges AVDD *RSOURCE CH_ OVERVOLTAGE PROTECTION CLAMP 2.5pF R1 CHOLD Selecting an Input Buffer ANALOG SIGNAL SOURCE UNDERVOLTAGE PROTECTION CLAMP CSAMPLE R2 VBIAS *MINIMIZE RSOURCE TO AVOID GAIN ERROR AND DISTORTION. PART MAX1304 MAX1305 MAX1306 MAX1308 MAX1309 MAX1310 MAX1312 MAX1313 MAX1314 INPUT RANGE (V) R1 (kΩ) R2 (kΩ) VBIAS (V) 0 TO +5 3.33 5.00 0.90 ±5 6.67 2.86 2.50 ±10 13.33 2.35 2.06 R1 | | R2 = 2kΩ Figure 5. Single-Channel, Equivalent Analog Input T/H Circuit Analog Inputs Track and Hold (T/H) To preserve phase information across the multichannel MAX1304–MAX1306/MAX1308–MAX1310/MAX1312– MAX1314, all input channels have dedicated T/H amplifiers. Figure 5 shows the equivalent analog input T/H circuit for one channel. The input T/H circuit is controlled by the CONVST input. When CONVST is low, the T/H circuit tracks the analog input. When CONVST is high the T/H circuit holds the analog input. The rising edge of CONVST is the analog input sampling instant. There is an aperture delay (tAD) of 8ns and a 50psRMS aperture jitter (tAJ). The aperture delay of each dedicated T/H input is matched within 100ps of each other. To settle the charge on CSAMPLE to 12-bit accuracy, use a minimum acquisition time (t ACQ ) of 100ns. Therefore, CONVST must be low for at least 100ns. Although longer acquisition times allow the analog input to settle to its final value more accurately, the maximum To improve the input signal bandwidth under AC conditions, drive the input with a wideband buffer (>50MHz) that can drive the ADC’s input capacitance (15pF) and settle quickly. For example, the MAX4431 or the MAX4265 can be used for the 0 to +5V unipolar devices, or the MAX4350 can be used for ±5V bipolar inputs. Most applications require an input buffer to achieve 12-bit accuracy. Although slew rate and bandwidth are important, the most critical input buffer specification is settling time. The simultaneous sampling of multiple channels requires an acquisition time of 100ns. At the beginning of the acquisition, the ADC internal sampling capacitor array connects to the analog inputs, causing some disturbance. Ensure the amplifier is capable of settling to at least 12-bit accuracy during this interval. Use a low-noise, low-distortion, wideband amplifier that settles quickly and is stable with the ADC’s 15pF input capacitance. See the Maxim website at www.maxim-ic.com for application notes on how to choose the optimum buffer amplifier for your ADC application. Input Bandwidth The input-tracking circuitry has a 20MHz small-signal bandwidth, making it possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. Input Range and Protection The MAX1304/MAX1305/MAX1306 provide a 0 to +5V input voltage range with fault protection of ±6V. The MAX1308/MAX1309/MAX1310 provide a ±5V input voltage range with fault protection of ±16.5V. The MAX1312/MAX1313/MAX1314 provide a ±10V input voltage range with fault protection of ±16.5V. Figure 5 shows the single-channel equivalent input circuit. ______________________________________________________________________________________ 19 MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 MAX1304–MAX1306 MAX1308–MAX1310 MAX1312–MAX1314 acquisition time must be limited to 1ms. Accuracy with conversion times longer than 1ms cannot be guaranteed due to capacitor droop in the input circuitry. Due to the analog input resistive divider formed by R1 and R2 in Figure 5, any significant analog input source resistance (RSOURCE) results in gain error. Furthermore, R SOURCE causes distortion due to nonlinear analog input currents. Limit RSOURCE to a maximum of 100Ω. MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges Data Throughput Clock Modes The data throughput (fTH) of the MAX1304–MAX1306/ MAX1308–MAX1310/MAX1312–MAX1314 is a function of the clock speed (fCLK). In internal clock mode, fCLK = 15MHz (typ). In external clock mode, 100kHz ≤ fCLK ≤ 20MHz. When reading during conversion (Figures 7 and 8), calculate fTH as follows: The MAX1304–MAX1306/MAX1308–MAX1310/MAX1312– MAX1314 provide a 15MHz internal conversion clock. Alternatively, an external clock can be used. fTH = tACQ + tQUIET 1 12 + 3 x (N − 1) + 1 + fCLK where N is the number of active channels and tQUIET is the period of bus inactivity before the rising edge of CONVST. See the Starting a Conversion section for more information. Table 1 uses the above equation and shows the total throughput as a function of the number of channels selected for conversion. Internal Clock Internal clock mode frees the microprocessor from the burden of running the ADC conversion clock. For internal clock operation, connect INTCLK/EXTCLK to AVDD and connect CLK to DGND. Note that INTCLK/EXTCLK is referenced to AVDD, not DVDD. External Clock For external clock operation, connect INTCLK/EXTCLK to AGND and connect an external clock source to CLK. Note that INTCLK/EXTCLK is referenced to AVDD, not DV DD . The external clock frequency can be up to 20MHz. Linearity is not guaranteed with clock frequencies below 100kHz due to droop in the T/H circuits. Table 1. Throughput vs. Channels Sampled: fCLK = 15MHz, tACQ = 100ns, tQUIET = 50ns 20 CHANNELS SAMPLED (N) CLOCK CYCLES UNTIL LAST RESULT CLOCK CYCLE FOR READING LAST CONVERSION 1 12 1 2 15 1 3 18 1 4 21 1 5 24 6 7 8 TOTAL CONVERSION TIME (ns) TOTAL THROUGHPUT (ksps) THROUGHPUT PER CHANNEL (fTH) 800 983 983 1000 1643 821 1200 2117 705 1400 2474 618 1 1600 2752 550 27 1 1800 2975 495 30 1 2000 3157 451 33 1 2200 3310 413 ______________________________________________________________________________________ 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges Digital Interface The bidirectional parallel digital interface allows for setting the 8-bit configuration register (see the Configuration Register section) and reading the 12-bit conversion result. The interface includes the following control signals: chip select (CS), read (RD), write (WR), end of conversion (EOC), end of last conversion (EOLC), conversion start (CONVST), shutdown (SHDN), channel shutdown (CHSHDN), internal clock select (INTCLK/EXTCLK), and external clock input (CLK). Figures 6, 7, 8, 9, Table 2, and the Timing Characteristics show the operation of the interface. D0–D7 are bidirectional, and D8–D11 are output only. D0–D11 go high impedance when RD = 1 or CS = 1. However, the new configuration does not take effect until the next CONVST falling edge. At power-up all channels default active. Shutdown does not change the configuration register. The configuration register may be written to in shutdown. See the Channel Shutdown (CHSHDN) section for information about using the configuration register for power saving. CONVST CONFIGURATION REGISTER UPDATES RD tCS Configuration Register Enable channels as active by writing to the configuration register through I/O lines D0–D7 (Table 2). The bits in the configuration register map directly to the channels, with D0 controlling channel zero, and D7 controlling channel seven. Setting any bit high activates the corresponding input channel, while resetting any bit low deactivates the corresponding channel. On the devices with less than eight channels, some of the bits have no function (Table 2). To write to the configuration register, pull CS and WR low, load bits D0 through D7 onto the parallel bus, and force WR high. The data are latched on the rising edge of WR (Figure 6). Write to the configuration register at any point during the conversion sequence. At powerup, write to the configuration register to select the active channels before beginning a conversion. CS tWRL tCTW tWTC WR tDTW D0–D7 DATA-IN tWTD Figure 6. Write Timing Table 2. Configuration Register PART NUMBER MAX1304 MAX1308 MAX1312 MAX1305 MAX1309 MAX1313 MAX1306 MAX1310 MAX1314 STATE BIT/CHANNEL D0/CH0 D1/CH1 D2/CH2 D3/CH3 D4/CH4 D5/CH5 D6/CH6 D7/CH7 ON 1 1 1 1 1 1 1 1 OFF 0 0 0 0 0 0 0 0 ON 1 1 1 1 X X X X OFF 0 0 0 0 X X X X ON 1 1 X X X X X X OFF 0 0 X X X X X X X = Don’t care (must be 1 or 0). ______________________________________________________________________________________ 21 MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 Applications Information MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges SAMPLE INSTANT tACQ CONVST HOLD TRACK tCONV TRACK tNEXT EOC tEOC tCVEOLCD EOLC tQUIET ≥ 50ns CS* tCTR tRDH tRTC RD tACC tRDL CH0 D0–D11 CH1 tREQ *CS CAN BE LOW AT ALL TIMES, LOW DURING THE RD CYCLES, OR THE SAME AS RD. Figure 7. Read During Conversion—Channel 0 and Channel 1 Selected, Internal Clock Starting a Conversion To start a conversion using internal clock mode, pull CONVST low for the acquisition time (tACQ). The T/H acquires the signal while CONVST is low, and conversion begins on the rising edge of CONVST. The end-ofconversion signal (EOC) pulses low whenever a conversion result becomes available for read. The endof-last-conversion signal (EOLC) goes low when the last conversion result is available (Figure 7). To start a conversion using external clock mode, pull CONVST low for the acquisition time (tACQ). The T/H acquires the signal while CONVST is low. The rising edge of CONVST is the sampling instant. Apply an external clock to CLK to start the conversion. To avoid T/H droop degrading the sampled analog input signals, 22 the first CLK pulse must occur within 10µs from the rising edge of CONVST. Additionally, the external clock frequency must be greater than 100kHz to avoid T/H droop-degrading accuracy. The first conversion result is available for read when EOC goes low on the rising edge of the 13th clock cycle. Subsequent conversion results are available after every third clock cycle thereafter (Figures 8 and 9). In both internal and external clock modes, hold CONVST high until the last conversion result is read. If CONVST goes low in the middle of a conversion, the current conversion is aborted and a new conversion is initiated. Furthermore, there must be a period of bus inactivity (tQUIET) for 50ns or longer before the falling edge of CONVST for the specified ADC performance. ______________________________________________________________________________________ 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges tACQ CONVST HOLD TRACK tCNTC CLK TRACK tCLK 1 2 3 12 tCLKH 13 14 tCLKL 15 16 17 tNEXT tEOCD 18 19 1 tEOCD EOC tCONV tEOC tEOLCD tCVEOLCD EOLC tQUIET ≥ 50ns CS* tCTR tRTC tRDH RD tACC tRDL CH3 D0–D11 CH7 tREQ *CS CAN BE LOW AT ALL TIMES, LOW DURING THE RD CYCLES, OR THE SAME AS RD. Figure 8. Read During Conversion—Channel 3 and Channel 7 Selected, External Clock Reading a Conversion Result Reading During a Conversion Figures 7 and 8 show the interface signals to initiate a read operation during a conversion cycle. These figures show two channels selected for conversion. If more channels are selected, the results are available successively at every EOC falling edge. CS can be low at all times, low during the RD cycles, or the same as RD. After initiating a conversion by bringing CONVST high, wait for EOC to go low. In internal clock mode, EOC goes low within 900ns. In external clock mode, EOC goes low on the rising edge of the 13th CLK cycle. To read the conversion result, drive CS and RD low to latch data to the parallel digital output bus. Bring RD high to release the digital bus. In internal clock mode, the next EOC falling edge occurs within 225ns. In external clock mode, the next EOC falling edge occurs in three CLK cycles. When the last result is available EOLC goes low. Reading After Conversion Figure 9 shows the interface signals for a read operation after a conversion with all eight channels enabled. At the falling of EOLC, driving CS and RD low places the first conversion result onto the parallel bus. Successive low pulses of RD place the successive conversion results onto the bus. When the last conversion results in the sequence are read, additional read pulses wrap the pointer back to the first converted result. ______________________________________________________________________________________ 23 MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 SAMPLE INSTANT MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges CONVST EOC ONLY LAST PULSE SHOWN tCVEOLCD tEOC EOLC CS* tRTC tCTR tRDL tRDH tQUIET1 = 50ns RD D0–D11 CH0 tACC CH1 CH2 CH3 CH4 CH5 CH6 CH7 tREQ * CS CAN BE LOW AT ALL TIMES, LOW DURING THE RD CYCLES, OR THE SAME AS RD. Figure 9. Read After Conversion—Eight Channels Selected, External Clock Power-Up Reset At power-up, all channels are selected for conversion (see the Configuration Register section). After applying power, allow the 1ms wake-up time to elapse and then initiate a dummy conversion and discard the results. After the dummy conversion is complete, accurate conversions can be obtained. Power-Saving Modes Shutdown Mode During shutdown the internal reference and analog circuits in the device shutdown and the analog supply current drops to 0.6µA (typ). Select shutdown mode using the SHDN input. Set SHDN high to enter shutdown mode. SHDN takes precedence over CHSHDN. Entering and exiting shutdown mode does not change the configuration byte. However, a new configuration byte can be written while in shutdown mode by following the standard write procedure shown in Figure 6. EOC and EOLC are high when the MAX1304–MAX1306/ MAX1308–MAX1310/MAX1312–MAX1314 are shut down. The state of the digital outputs D0–D11 is independent of the state of SHDN. If CS and RD are low, the digital outputs D0–D11 are active regardless of SHDN. The digital outputs only go high impedance when CS or RD is high. When the digital outputs are powered down, the digital supply current drops to 20nA. 24 Exiting shutdown (falling edge of SHDN) starts a conversion in the same way as the rising edge of CONVST. After coming out of shutdown, initiate a dummy conversion and discard the results. After the dummy conversion, allow the 1ms wake-up time to expire before initiating the first accurate conversion. Channel Shutdown (C CHSHDN ) The channel-shutdown feature allows analog input channels to be powered down when they are not selected for conversion. Powering down channels that are not selected for conversion reduces the analog supply current by 2.9mA per channel. To power down channels that are not selected for conversion, pull CHSHDN low. See the Configuration Register section for information on selecting and deselecting channels for conversion. The drawback of powering down analog inputs that are not selected for conversion is that it takes time to power them up. Figure 10 shows how a dummy conversion is used to power up an analog input in external clock mode. After selecting a new channel in the configuration register, initiate a dummy conversion and discard the results. After the dummy conversion, allow the 1ms wake-up time (tWAKE) to expire before initiating the first accurate conversion. ______________________________________________________________________________________ 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 CS* tACQ tACQ CONVST CONFIGURATION REGISTER UPDATES DUMMY CONVERSION START FIRST ACCURATE CONVERSION START WR CONFIGURATION REGISTER POWERS UP ONE OR MORE CHANNELS D0–D7 DATA IN tWAKE ≥ 1ms 1 2 3 4 5 12 13 1 CLK EOC EOLC *CS CAN BE LOW AT ALL TIMES, LOW DURING THE RD CYCLES, OR THE SAME AS RD. Figure 10. Powering Up an Analog Input Channel with a Dummy Conversion and Wake-Up Time (CHSHDN = 0, External-Clock Mode, One Channel Selected) CS* tACQ tACQ CONVST CONFIGURATION REGISTER UPDATES FIRST ACCURATE CONVERSION START SECOND ACCURATE CONVERSION START WR CONFIGURATION REGISTER POWERS UP ONE OR MORE CHANNELS D0–D7 DATA IN 1 2 3 4 5 12 13 1 CLK EOC EOLC *CS CAN BE LOW AT ALL TIMES, LOW DURING THE RD CYCLES, OR THE SAME AS RD. Figure 11. Powering Up an Analog Input Channel Directly (CHSHDN = 1, External-Clock Mode, One Channel Selected) ______________________________________________________________________________________ 25 MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges erence voltage by driving REF with a +2.0V to +3.0V external reference. As shown in Figure 2, the REF input impedance is 5kΩ. For more information about using external references see the Transfer Functions section. To avoid the timing requirements associated with powering up an analog channel, force CHSHDN high. With CHSHDN high, each analog input is powered up regardless of whether it is selected for conversion in the configuration register. Note that shutdown mode takes precedence over the CHSHDN mode. Midscale Voltage (MSV) The voltage at MSV (VMSV) sets the midpoint of the ADC transfer functions. For the 0 to +5V input range (unipolar devices), the midpoint of the transfer function is +2.5V. For the ±5V and ±10V input range devices, the midpoint of the transfer function is zero. As shown in Figure 2, there is a unity-gain buffer between REFMS and MSV in the unipolar MAX1304/ MAX1305/MAX1306. This midscale buffer sets the midpoint of the unipolar transfer functions to either the internal +2.5V reference or an externally applied voltage at REFMS. VMSV follows VREFMS within ±3mV. The midscale buffer is not active for the bipolar devices. For these devices, MSV must be connected to AGND or externally driven. REFMS must be bypassed with a 0.01µF capacitor to AGND. See the Transfer Functions section for more information about MSV. Reference Internal Reference The internal reference circuits provide for analog input voltages of 0 to +5V for the unipolar MAX1304/ MAX1305/MAX1306, ±5V for the bipolar MAX1308/ MAX1309/MAX1310 or ±10V for the bipolar MAX1312/ MAX1313/MAX1314. Install external capacitors for reference stability, as indicated in Table 3 and shown in Figures 3 and 4. As illustrated in Figure 2, the internal reference voltage is 2.5V (VREF). This 2.5V is internally buffered to create the voltages at REF+ and REF-. Table 4 shows the voltages at COM, REF+, and REF-. External Reference External reference operation is achieved by overriding the internal reference voltage. Override the internal ref- Table 3. Reference Bypass Capacitors INPUT VOLTAGE RANGE LOCATION UNIPOLAR (µF) BIPOLAR (µF) 2.2 || 0.1 N/A REFMS Bypass Capacitor to AGND 0.01 0.01 REF Bypass Capacitor to AGND 0.01 0.01 REF+ Bypass Capacitor to AGND 0.1 0.1 2.2 || 0.1 2.2 || 0.1 MSV Bypass Capacitor to AGND REF+ to REF- Capacitor REF- Bypass Capacitor to AGND 0.1 0.1 COM Bypass Capacitor to AGND 2.2 || 0.1 2.2 || 0.1 N/A = Not applicable. Connect MSV directly to AGND. Table 4. Reference Voltages PARAMETER EQUATION CALCULATED VALUE (V) VREF = 2.000V, AVDD = 5.0V CALCULATED VALUE (V) VREF = 2.500V, AVDD = 5.0V CALCULATED VALUE (V) VREF = 3.000V, AVDD = 5.0V ( ) ( ) ( ) VCOM VCOM = 13 / 25 x AVDD 2.600 2.600 2.600 VREF+ VREF+ = VCOM + VREF / 2 3.600 3.850 4.100 VREF- VREF- = VCOM - VREF / 2 1.600 1.350 1.100 VREF+ - VREF- VREF- - VREF+ = VREF 2.000 2.500 3.000 26 ______________________________________________________________________________________ 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges Unipolar 0 to +5V Devices Table 5 and Figure 12 show the offset binary transfer function for the MAX1304/MAX1305/MAX1306 with a 0 to +5V input range. The full-scale input range (FSR) is two times the voltage at REF. The internal +2.5V reference gives a +5V FSR, while an external +2V to +3V reference allows an FSR of +4V to +6V, respectively. Calculate the LSB size using: 1 LSB = 2 x VREF 212 The input range is centered about VMSV, internally set to +2.5V. For a custom midscale voltage, drive REFMS with an external voltage source and MSV will follow REFMS. Noise present on MSV or REFMS directly couples into the ADC result. Use a precision, low-drift voltage reference with adequate bypassing to prevent MSV from degrading ADC performance. For maximum FSR, do not violate the absolute maximum voltage ratings of the analog inputs when choosing MSV. Determine the input voltage as a function of V REF , VMSV, and the output code in decimal using: VCH_ = LSB x CODE10 + VMSV - 2.500V which equals 1.22mV when using a 2.5V reference. Table 5. 0 to 5V Unipolar Code Table BINARY DIGITAL OUTPUT CODE DECIMAL EQUIVALENT DIGITAL OUTPUT CODE (CODE10) 1111 1111 1111 = 0xFFF 4095 +4.9994 ± 0.5 LSB 1111 1111 1110 = 0xFFE 4094 +4.9982 ± 0.5 LSB 1000 0000 0001 = 0x801 2049 +2.5018 ± 0.5 LSB 1000 0000 0000 = 0x800 2048 +2.5006 ± 0.5 LSB 0111 1111 1111 = 0x7FF 2047 +2.4994 ± 0.5 LSB 0000 0000 0001 = 0x001 1 +0.0018 ± 0.5 LSB 0000 0000 0000 = 0x000 0 +0.0006 ± 0.5 LSB INPUT VOLTAGE (V) VREF = +2.5V VREFMS = +2.5V ) BINARY OUTPUT CODE ( 2 x VREF 0xFFF 0xFFE 0xFFD 0xFFC 0x801 0x800 0x7FF 0x0003 0x0002 0x0001 0x0000 1 LSB = 0 1 2 3 2046 2048 2050 (MSV) 2 x VREF 4093 212 4095 INPUT VOLTAGE (LSBs) Figure 12. 0 to +5V Unipolar Transfer Function ______________________________________________________________________________________ 27 MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 Transfer Functions Bipolar ±5V Devices Table 6 and Figure 13 show the two’s complement transfer function for the ±5V input range MAX1308/MAX1309/ MAX1310. The FSR is four times the voltage at REF. The internal +2.5V reference gives a +10V FSR, while an external +2V to +3V reference allows an FSR of +8V to +12V respectively. Calculate the LSB size using: 1 LSB = 4 x VREF 212 which equals 2.44mV when using a 2.5V reference. The input range is centered about V MSV. Normally, MSV = AGND, and the input is symmetrical about zero. For a custom midscale voltage, drive MSV with an external voltage source. Noise present on MSV directly couples into the ADC result. Use a precision, low-drift voltage reference with adequate bypassing to prevent MSV from degrading ADC performance. For maximum FSR, do not violate the absolute maximum voltage ratings of the analog inputs when choosing MSV. Determine the input voltage as a function of VREF , VMSV, and the output code in decimal using: VCH_ = LSB x CODE10 + VMSV Table 6. ±5V Bipolar Code Table TWO’s COMPLEMENT DIGITAL OUTPUT CODE DECIMAL EQUIVALENT DIGITAL OUTPUT CODE (CODE10) 0111 1111 1111 = 0x7FF +2047 +4.9988 ± 0.5 LSB 0111 1111 1110 = 0x7FE +2046 +4.9963 ± 0.5 LSB 0000 0000 0001 = 0x001 +1 +0.0037 ± 0.5 LSB 0000 0000 0000 = 0x000 0 +0.0012 ± 0.5 LSB INPUT VOLTAGE (V) VREF = +2.5V VMSV = 0 ( ) 1111 1111 1111 = 0xFFF -1 -0.0012 ± 0.5 LSB 1000 0000 0001 = 0x801 -2047 -4.9963 ± 0.5 LSB 1000 0000 0000 = 0x800 -2048 -4.9988 ± 0.5 LSB 4 x VREF TWO'S COMPLEMENT BINARY OUTPUT CODE MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges 0x7FF 0x7FE 0x7FD 0x7FC 0x001 0x000 0xFFF 0x803 0x802 0x801 0x800 1 LSB = -2048 -2046 -1 0 +1 (MSV) 28 ______________________________________________________________________________________ 212 +2045 +2047 INPUT VOLTAGE (VCH_ - VMSV IN LSBs) Figure 13. ±5V Bipolar Transfer Function 4 x VREF 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges 1 LSB = 8 x VREF 212 which equals 4.88mV with a +2.5V internal reference. The input range is centered about V MSV. Normally, MSV = AGND, and the input is symmetrical about zero. For a custom midscale voltage, drive MSV with an external voltage source. Noise present on MSV directly couples into the ADC result. Use a precision, low-drift voltage reference with adequate bypassing to prevent MSV from degrading ADC performance. For maximum FSR, do not violate the absolute maximum voltage ratings of the analog inputs when choosing MSV. Determine the input voltage as a function of VREF , VMSV, and the output code in decimal using: VCH_ = LSB x CODE10 + VMSV Table 7. ±10V Bipolar Code Table DECIMAL EQUIVALENT DIGITAL OUTPUT CODE (CODE10) INPUT VOLTAGE (V) VREF = +2.5V VMSV = 0 0111 1111 1111 = 0x7FF +2047 +9.9976 ± 0.5 LSB 0111 1111 1110 = 0x7FE +2046 +9.9927 ± 0.5 LSB 0000 0000 0001 = 0x001 +1 +0.0073 ± 0.5 LSB 0000 0000 0000 = 0x000 0 0.0024 ± 0.5 LSB ( ) 1111 1111 1111 = 0xFFF -1 -0.0024 ± 0.5 LSB 1000 0000 0001 = 0x801 -2047 -9.9927 ± 0.5 LSB 1000 0000 0000 = 0x800 -2048 -9.9976 ± 0.5 LSB 8 x VREF TWO'S COMPLEMENT BINARY OUTPUT CODE TWO’s COMPLEMENT DIGITAL OUTPUT CODE 0x7FF 0x7FE 0x7FD 0x7FC 0x001 0x000 0xFFF 0x803 0x802 0x801 0x800 1 LSB = -2048 -2046 -1 0 +1 (MSV) 8 x VREF 212 +2045 +2047 INPUT VOLTAGE (VCH_ - VMSV IN LSBs) Figure 14. ±10V Bipolar Transfer Function ______________________________________________________________________________________ 29 MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 Bipolar ±10V Devices Table 7 and Figure 14 show the two’s complement transfer function for the ±10V input range MAX1312/ MAX1313/MAX1314. The FSR is eight times the voltage at REF. The internal +2.5V reference gives a +20V FSR, while an external +2V to +3V reference allows an FSR of +16V to +24V, respectively. Calculate the LSB size using: MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges 3-Phase Motor Controller The MAX1304–MAX1306/MAX1308–MAX1310/MAX1312– MAX1314 are ideally suited for motor-control systems (Figure 15). The devices’ simultaneously sampled inputs eliminate the need for complicated DSP algo- rithms that realign sequentially sampled data into a simultaneous sample set. Additionally, the variety of input voltage ranges allows for flexibility when choosing current sensors and position encoders. MAX1308 DSP 12-BIT ADC T/H IGBT CURRENT DRIVERS IPHASE3 CURRENT SENSOR IPHASE1 IPHASE2 3-PHASE ELECTRIC MOTOR PHASE 1 PHASE 3 PHASE 2 POSITION ENCODER Figure 15. 3-Phase Motor Control 30 ______________________________________________________________________________________ 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges ously sampled eight channels eliminate the need for complicated DSP algorithms that realign sequentially sampled data into a simultaneous sample set. MAX1312 T/H 12-BIT ADC MICROCONTROLLER BUFFERS AND INPUT PROTECTION VP3 VP1 VNEUTRAL VP2 IP3 IP2 IPn IP1 CURRENT TRANSFORMER PHASE 1 LOAD POWER GRID NEUTRAL CURRENT TRANSFORMER LOAD LOAD CURRENT TRANSFORMER PHASE 2 PHASE 3 CURRENT TRANSFORMER Figure 16. 3-Phase Power Monitoring ______________________________________________________________________________________ 31 MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 3-Phase Power-Monitoring System The 8-channel devices are well suited for use in 3-phase power monitoring (Figure 16). The simultane- MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges Layout, Grounding, and Bypassing For best performance use PC boards. Board layout must ensure that digital and analog signal lines are separated from each other. Do not run analog and digital lines parallel to one another (especially clock lines), and do not run digital lines underneath the ADC package. Figure 17 shows the recommended system ground connections. Establish an analog ground point at AGND and a digital ground point at DGND. Connect all analog grounds to the analog ground point. Connect all digital grounds to the digital ground point. For lowest noise operation, make the power-supply ground returns as low impedance and as short as possible. Connect the analog ground point to the digital ground point at one location. High-frequency noise in the power supplies degrades the ADC’s performance. Bypass the analog power plane to the analog ground plane with a 2.2µF capacitor within one inch of the device. Bypass each AVDD to AGND pair of pins with a 0.1µF capacitor as close to the device as possible. AVDD to AGND pairs are pin 1 to pin 2, pin 14 to pin 15, and pin 16 to pin 17. Likewise, bypass the digital power plane to the digital ground plane with a 2.2µF capacitor within one inch of the device. Bypass each DVDD to DGND pair of pins with a 0.1µF capacitor as close to the device as possible. DVDD to DGND pairs are pin 24 to pin 25, and pin 38 to pin 39. If a supply is very noisy use a ferrite bead as a lowpass filter as shown in Figure 17. Definitions Integral Nonlinearity (INL) INL is the deviation of the values on an actual transfer function from a straight line. For these devices, this straight line is drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. Differential Nonlinearity (DNL) DNL is the difference between an actual step width and the ideal value of 1 LSB. For these devices, the DNL of each digital output code is measured and the worstcase value is reported in the electrical characteristics table. A DNL error specification of less than ±1 LSB guarantees no missing codes and a monotonic transfer function. 32 ANALOG SUPPLY +5V RETURN DIGITAL GROUND POINT DIGITAL SUPPLY RETURN +3V TO +5V OPTIONAL ANALOG GROUND FERRITE POINT BEAD AVDD AGND DGND MAX1304–MAX1306 MAX1308–MAX1310 MAX1312–MAX1314 DGND DVDD DATA DVDD DIGITAL CIRCUITRY Figure 17. Power-Supply Grounding and Bypassing Offset Error Offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. Typically the point at which offset error is specified is either at or near the zeroscale point of the transfer function or at or near the midscale point of the transfer function. For the unipolar devices (MAX1304/MAX1305/ MAX1306), the ideal zero-scale transition from 0x000 to 0x001 occurs at 1 LSB above AGND (Figure 12, Table 5). Unipolar offset error is the amount of deviation between the measured zero-scale transition point and the ideal zero-scale transition point. For the bipolar devices (MAX1308/MAX1309/MAX1310/ MAX1312/MAX1313/MAX1314), the ideal midscale transition from 0xFFF to 0x000 occurs at MSV (Figures 14 and 13, Tables 7 and 6). The bipolar offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point. ______________________________________________________________________________________ 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed as: For the unipolar devices (MAX1304/MAX1305/ MAX1306), the full-scale transition point is from 0xFFE to 0xFFF and the zero-scale transition point is from 0x000 to 0x001. For the bipolar devices (MAX1308/MAX1309/MAX1310/ MAX1312/MAX1313/MAX1314), the full-scale transition point is from 0x7FE to 0x7FF and the zero-scale transition point is from 0x800 to 0x801. Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNRdB[max] = 6.02dB × N + 1.76dB In reality, there are other noise sources such as thermal noise, reference noise, and clock jitter. For these devices, SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first five harmonics, and the DC offset. Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset. ENOB = SINAD − 1.76 6.02 Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of the first five harmonics to the fundamental itself. This is expressed as: V22 + V32 + V 2 + V52 + V62 4 THD = 20 x log V 1 where V1 is the fundamental amplitude, and V2 through V 6 are the amplitudes of the 2nd- through 6thorder harmonics. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. SFDR is specified in decibels relative to the carrier (dBc). Channel-to-Channel Isolation Channel-to-channel isolation indicates how well each analog input is isolated from the others. The channel-tochannel isolation for these devices is measured by applying DC to channel 1 through channel 7 while an AC 500kHz, -0.4dBFS sine wave is applied to channel 0. An FFT is taken for channel 0 and channel 1 and the difference (in dB) of the 500kHz magnitudes is reported as the channel-to-channel isolation. Aperature Delay Aperture delay (tAD) is the time delay from the CONVST rising edge to the instant when an actual sample is taken. SIGNALRMS SINAD(dB) = 20 x log (NOISE + DISTORTION)RMS ______________________________________________________________________________________ 33 MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 Gain Error Gain error is a figure of merit that indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. For the MAX1304– MAX1306/MAX1308–MAX1310/MAX1312–MAX1314, the gain error is the difference of the measured full-scale and zero-scale transition points minus the difference of the ideal full-scale and zero-scale transition points. MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges Aperture Jitter Full-Power Bandwidth Aperture Jitter (tAJ) is the sample-to-sample variation in aperture delay. A large, -0.5dBFS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. This point is defined as fullpower input bandwidth frequency. Jitter is a concern when considering an ADC’s dynamic performance, e.g., SNR. To reconstruct an analog input from the ADC digital outputs, it is critical to know the time at which each sample was taken. Typical applications use an accurate sampling clock signal that has low jitter from sampling edge to sampling edge. For a system with a perfect sampling clock signal, with no clock jitter, the SNR performance of an ADC is limited by the ADC’s internal aperture jitter as follows: 1 SNR = 20 x log 2 x π x fIN x tAJ DC Power-Supply Rejection (PSRR) DC PSRR is defined as the change in the positive fullscale transfer function point caused by a ±5% variation in the analog power-supply voltage (AVDD). Chip Information TRANSISTOR COUNT: 50,000 PROCESS: 0.6µm BiCMOS where fIN represents the analog input frequency and tAJ is the time of the aperture jitter. Small-Signal Bandwidth A small -20dBFS analog input signal is applied to an ADC so that the signal’s slew rate does not limit the ADC’s performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. 34 ______________________________________________________________________________________ 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges 8 29 D11 37 38 39 41 42 43 44 40 29 27 11 26 12 25 D8 D7 D6 D5 D4 D3 D2 D1 D0 DVDD INTCLK/EXTCLK AGND AVDD AGND AVDD REFMS REF REF+ COM REFAGND DGND 13 28 10 D11 37 38 39 40 41 42 43 44 45 46 CHSHDN SHDN CLK CONVST CS WR RD EOLC EOC DGND DVDD 4-CHANNEL TQFP 1 36 2 35 AGND CH0 CH1 MSV 3 34 4 33 5 32 I.C. 7 I.C. I.C. I.C. I.C. 8 6 MAX1306 MAX1310 MAX1314 D10 D9 31 D8 D7 D6 D5 30 D4 29 24 23 22 REF REF+ COM REFAGND DGND AGND AVDD REFMS INTCLK/EXTCLK AGND AVDD 21 DVDD 20 25 19 26 12 18 27 11 17 10 D3 D2 D1 D0 16 28 15 9 14 30 9 AVDD AGND 13 45 46 CHSHDN SHDN CLK CONVST CS WR RD EOLC EOC DGND DVDD 8 48 47 MAX1305 MAX1309 MAX1313 7 8-CHANNEL TQFP I.C. 47 31 24 23 22 21 20 32 6 INTCLK/EXTCLK AGND AVDD AGND AVDD REFMS REF REF+ COM REFAGND DGND 19 25 18 12 17 26 16 11 15 27 14 10 13 28 5 D6 D5 D4 D3 D2 D1 D0 DVDD 30 9 33 D10 D9 24 MAX1304 MAX1308 MAX1312 7 34 4 23 31 3 CH0 CH1 MSV CH2 CH3 I.C. I.C. I.C. I.C. 22 32 6 35 21 5 D8 D7 36 2 20 33 1 19 34 4 AVDD AGND AGND 18 3 CH0 CH1 MSV CH2 CH3 CH4 CH5 CH6 CH7 D10 D9 17 35 16 36 2 15 1 14 AVDD AGND AGND 48 37 38 39 40 41 42 43 44 45 46 47 48 CHSHDN SHDN CLK CONVST CS WR RD EOLC EOC DGND DVDD D11 TOP VIEW 2-CHANNEL TQFP ______________________________________________________________________________________ 35 MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 Pin Configurations Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 32L/48L,TQFP.EPS MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.4mm 21-0054 E 1 2 PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.4mm 21-0054 E 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 36 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.