19-2905; Rev 1; 3/09 KIT ATION EVALU E L B A AVAIL 12.5Gbps CML 2 × 2 Crosspoint Switch The MAX3841 is a low-power, 12.5Gbps 2 × 2 crosspoint switch IC for high-speed serial data loopback, redundancy, and switching applications. The MAX3841 current-mode logic (CML) inputs and outputs have isolated VCC connections to enable DC-coupled interfaces to 1.8V, 2.5V, or 3.3V CML ICs. Fully differential signal paths and Maxim’s second-generation SiGe technology provide optimum signal integrity, minimizing jitter, crosstalk, and signal skew. The MAX3841 is ideal for serial OC-192 and 10GbE optical module, line card, switch fabric, and similar applications. The MAX3841 has 150mVP-P minimum differential input sensitivity, and 500mVP-P nominal differential output swing. Unused outputs can be powered down individually to conserve power. In addition to functioning as a 2 × 2 switch, the MAX3841 can be configured as a 2:1 multiplexer, 1:2 buffer, or dual 1:1 buffer. The MAX3841 is available in a 4mm × 4mm 24-pin thin QFN package, and consumes only 215mW with both outputs enabled. Features ♦ Up to 12.5Gbps Operation ♦ Less Than 10psP-P Deterministic Jitter ♦ Less Than 0.7psRMS Random Jitter ♦ 1.8V, 2.5V, and 3.3V DC-Coupled CML I/O ♦ Independent Output Power-Down ♦ 4mm × 4mm Thin QFN Package ♦ -40°C to +85°C Operation ♦ +3.3V Core Supply ♦ 215mW Power Consumption (Excluding Termination Currents) Ordering Information PART Applications TEMP RANGE PIN-PACKAGE MAX3841ETG -40°C to +85°C 24 Thin QFN-EP* MAX3841ETG+ -40°C to +85°C 24 Thin QFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. OC-192, 10GbE Switch/Line Cards OC-192, 10GbE Optical Modules System Redundancy/Self Test Pin Configuration appears at end of data sheet. Clock Fanout Typical Application Circuit 1.8V 3.3V 10Gbps SERIAL OPTICAL MODULE 2.5V 3.3V 1.8V VCC1OUT VCC VCC2IN 10Gbps CDR/SERDES ASIC 2.5V SDI+ OUT1+ IN2+ SDO+ SDI- OUT1- IN2- SDO- OUT2+ SDI+ IN1+ SDO+ MAX3841 IN1- SDO- SDI- OUT2- 2.5V 1.8V VCC2OUT VCC1IN SEL1 SEL2 ENO1 ENO2 GND LOOPBACK ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX3841 General Description MAX3841 12.5Gbps CML 2 × 2 Crosspoint Switch ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC..............................................-0.5V to +4.0V CML Supply Voltage (VCC_IN, VCC_OUT)...........-0.5V to +4.0V Continuous Output Current (OUT1±, OUT2±)...................±25mA CML Input Voltage (IN1±, IN2±)...........-0.5V to (VCC_IN + 0.5V) LVCMOS Input Voltage (SEL1, SEL2, ENO1, ENO2) .........................................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +85°C) 24-Pin Thin QFN (derate 20.8mW/°C above +85°C).............................................................1352mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-55°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, VCC_IN = +1.71V to VCC, VCC_OUT = +1.71V to VCC, TA = -40°C to +85°C. Typical values are at VCC = +3.3V, VCC_IN = VCC_OUT = 1.8V, TA = +25°C, unless otherwise noted.) PARAMETER Core Supply Current SYMBOL ICC Data Rate CML Input Differential CONDITIONS (Note 1) VIN AC-coupled or DC-coupled (Note 2) CML Input Common Mode DC-coupled CML Input Termination Single ended CML Input Return Loss CML Output Differential tR, tF TYP MAX 65 90 mA 12.5 Gbps 1200 mVP-P 0 150 VCC_IN - 0.3 UNITS VCC_IN V 57.5 42.5 50 (Note 2) 400 500 600 mVP-P Single ended 42.5 50 57.5 Up to 10GHz VOUT CML Output Termination CML Output Transition Time MIN Excluding CML termination currents 12 dB 20% to 80% (Notes 1, 3) 30 ps Deterministic Jitter (Notes 1, 4) 10 psP-P Random Jitter 0.3 0.7 psRMS Propagation Delay VIN = 150mVP-P (Notes 1, 5) Any input to output (Note 1) 100 140 ps Channel-to-Channel Skew (Note 1) 12 ps Output Duty-Cycle Skew LVCMOS Input Current 50% input duty cycle (Notes 1, 3) IIH, I IL -10 LVCMOS Input High Voltage VIH 1.7 LVCMOS Input Low Voltage VIL 8 ps +10 μA V 0.7 V Guaranteed by design and characterization. Differential swing is defined as VIN = (IN_+) - (IN_-) and VOUT = (OUT_+) - (OUT_-). See Figure 1. Measured using a 0000011111 pattern at 12.5Gbps, and VIN = 400mVP-P differential. Measured at 9.953Gbps using a pattern of 100 ones, 27 - 1 PRBS, 100 zeros, 27 - 1 PRBS, and at 12.5Gbps using a ±K28.5 pattern. VCC_IN = VCC_OUT = 1.8V, and VIN = 400mVP-P differential. Note 5: Refer to Application Note 1181: HFAN-04.5.1: Measuring Random Jitter on a Digital Sampling Oscilloscope. Note 1: Note 2: Note 3: Note 4: 2 _______________________________________________________________________________________ 12.5Gbps CML 2 × 2 Crosspoint Switch CORE SUPPLY CURRENT vs. TEMPERATURE (EXCLUDES CML I/O CURRENTS) 110 0 OUTPUTS ENABLE 100 1 OUTPUT ENABLE 90 2 OUTPUTS ENABLE 80 130 70 110 70 50 40 40 35 60 60mV/div 80 60 10 0 OUTPUTS ENABLE 90 50 -15 1 OUTPUT ENABLE 100 60 -40 2 OUTPUTS ENABLE 120 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 120 85 CML INPUTS AND OUTPUTS AC-COUPLED -40 -15 10 35 60 TEMPERATURE (°C) TEMPERATURE (°C) OUTPUT EYE DIAGRAM (10.7Gbps, 223 - 1 PRBS) OUTPUT EYE DIAGRAM (6.25Gbps, 223 - 1 PRBS) MAX3841 toc04 85 OUTPUT EYE DIAGRAM (622Mbps, 223 - 1 PRBS) MAX3841 toc06 60mV/div 60mV/div 28ps/div 270ps/div DETERMINISTIC JITTER vs. TEMPERATURE DIFFERENTIAL OUTPUT SWING vs. TEMPERATURE PROPAGATION DELAY 12 10 8 6 4 MAX3841 toc08 2 - 1 PRBS + 100CIDs AT 10.7Gbps 14 MAX3841 toc09 550 540 DIFFERENTIAL OUTPUT (mVP-P) 7 MAX3841 toc07 16ps/div 16 2 14ps/div MAX3841 toc05 60mV/div DETERMINISTIC JITTER (ps) MAX3841 toc02 130 OUTPUT EYE DIAGRAM (12.5Gbps, 223 - 1 PRBS) MAX3841 toc03 140 MAX3841 toc01 140 SUPPLY CURRENT vs. TEMPERATURE (CORE PLUS CML I/O CURRENTS) 530 IN1 520 510 500 490 480 OUT1 470 460 ±K28.5 AT 12.5Gbps 450 0 -40 -15 10 35 TEMPERATURE (°C) 60 85 -40 -15 10 35 60 85 100ps/div TEMPERATURE (°C) _______________________________________________________________________________________ 3 MAX3841 Typical Operating Characteristics (VCC = 3.3V, VCC_IN, VCC_OUT = 1.8V, VIN = 500mVP-P, TA = +25°C, unless otherwise noted.) 12.5Gbps CML 2 × 2 Crosspoint Switch MAX3841 Pin Description PIN NAME FUNCTION 1, 12 VCC 2, 5 VCC1IN +3.3V Core Supply Voltage 3 IN1+ Positive Serial Data Input 1, CML 4 IN1- Negative Serial Data Input 1, CML 6 SEL1 Output 1 Select, LVCMOS Input. See Table 1. 7 SEL2 Output 2 Select, LVCMOS Input. See Table 1. 8, 11 VCC2IN 9 IN2+ Positive Serial Data Input 2, CML 10 IN2- Negative Serial Data Input 2, CML 13, 24 GND Supply Ground 14, 17 VCC1OUT Supply Voltage for CML Input IN1. Connect to 1.8V, 2.5V, or 3.3V. Supply Voltage for CML Input IN2. Connect to 1.8V, 2.5V, or 3.3V. Supply Voltage for CML Output OUT1. Connect to 1.8V, 2.5V, or 3.3V. 15 OUT1- 16 OUT1+ Negative Serial Data Output 1, CML 18 ENO1 Output 1 Enable, LVCMOS Input. See Table 1. Output 2 Enable, LVCMOS Input. See Table 1. 19 ENO2 20, 23 VCC2OUT 21 OUT2- 22 OUT2+ — EP Positive Serial Data Output 1, CML Supply Voltage for CML Output OUT2. Connect to 1.8V, 2.5V, or 3.3V. Negative Serial Data Output 2, CML Positive Serial Data Output 2, CML Exposed Pad. The exposed pad must be soldered to the circuit board ground for proper thermal and electrical performance. Detailed Description The MAX3841 contains a pair of CML inputs that drive two 2:1 multiplexers, with separate select inputs SEL1 and SEL2, providing a 2 × 2 crosspoint data path. The outputs of the multiplexers each drive a high-performance CML output that can be disabled (powered down) using the ENO1/ENO2 inputs. All of the data paths are fully differential to minimize jitter, crosstalk, and signal skew. See Figure 1 for the functional diagram. The CML inputs accept serial NRZ data with differential amplitude from 150mVP-P to 1200mVP-P (see Figure 2). The CML outputs provide 500mVP-P nominal differential swing, resulting in low power consumption. 2 IN1 CML 1 2 OUT1 CML 0 ENO1 CML Input and Output Buffers The MAX3841 input and output buffers are terminated with 50Ω to independent supply lines, and are also compatible with 100Ω differential terminations. (See Figures 3 and 4.) Separate power-supply connections are provided for the core, input buffers, and output buffers to allow DCcoupling to 1.8V, 2.5V, or 3.3V CML ICs. If desired, the CML inputs and outputs can be AC-coupled. SEL1 2 IN2 CML 1 2 CML ENO2 MAX3841 Figure 1. Functional Diagram 4 OUT2 0 _______________________________________________________________________________________ SEL2 12.5Gbps CML 2 × 2 Crosspoint Switch 75mV MIN 600mV MAX V+ 150mV MIN (V+) - (V-) 1200mV MAX ENO1 ENO2 SEL1 SEL2 OUT1 OUT2 0 0 0 0 IN2 IN1 0 0 0 1 IN2 IN2 0 0 1 0 IN1 IN1 0 0 1 1 IN1 IN2 1 1 X X Disabled Disabled Applications Information Select and Enable Controls The MAX3841 provides two LVCMOS-compatible select inputs, SEL1 and SEL2. Either data input can be connected to either or both data outputs. The MAX3841 provides two LVCMOS-compatible enable inputs, ENO1 and ENO2, so each output can be disabled independently. The MAX3841 can also be used as a 1:2 driver, 2:1 multiplexer, or a dual 1:1 buffer by using the LVCMOS control inputs accordingly (see Table 1). Figure 2. Definition of Differential Voltage Swing VCC_IN 50Ω 50Ω Power-Supply Connections IN_+ Each of the input and output power-supply connections (VCC1IN, VCC2IN, VCC1OUT, VCC2OUT) is independent and need not be connected to the same voltage. The input and output supplies can be connected to 1.8V, 2.5V, or 3.3V, but the core supply (VCC) must be connected to 3.3V for proper operation. IN_- MAX3841 Input and Output Interfaces The MAX3841 inputs and outputs can be AC-coupled or DC-coupled according to the application. If an input or output is not used it should be terminated with 50Ω to the correct input or output supply voltage. For more information about interfacing with logic families, refer to Application Note 291: HFAN-01.0: Introduction to LVDS, PECL, and CML. Figure 3. Equivalent CML Input Circuit VCC_OUT 50Ω 50Ω OUT_+ OUT_- MAX3841 Package and Layout Considerations The MAX3841 is packaged in a 4mm × 4mm 24-pin thin QFN with exposed pad. The exposed pad provides thermal and electrical connectivity to the IC and must be soldered to a high-frequency ground plane. Use multiple vias to connect the exposed pad underneath the package to the PC board ground plane. Use good layout techniques for the 10Gbps PC board transmission lines, and configure the layout near the IC to minimize impedance discontinuities. Power-supply decoupling capacitors should be located as close as possible to the IC. Figure 4. Equivalent CML Output Circuit _______________________________________________________________________________________ 5 MAX3841 Table 1. Output Controls V- 12.5Gbps CML 2 × 2 Crosspoint Switch Chip Information TRANSISTOR COUNT: 950 PROCESS: SiGe BiCMOS ENO2 VCC2OUT OUT2- OUT2+ GND TOP VIEW VCC2OUT MAX3841 Pin Configuration Package Information 24 23 22 21 20 19 VCC 1 18 ENO1 VCC1IN 2 17 VCC1OUT IN1+ 3 16 OUT1+ IN1- 4 VCC1IN 5 SEL1 6 MAX3841 15 OUT1- DOCUMENT NO. 24 TQFN-EP T2444-3 21-0139 VCC 10 11 12 VCC2IN VCC2IN 9 IN2- SEL2 PACKAGE CODE 13 GND IN2+ 8 PACKAGE TYPE 14 VCC1OUT *EP 7 For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. THIN QFN *THE EXPOSED PAD OF THE QFN PACKAGE MUST BE SOLDERED TO GROUND FOR PROPER THERMAL AND ELECTRICAL OPERATION. 6 _______________________________________________________________________________________ 12.5Gbps CML 2 × 2 Crosspoint Switch REVISION NUMBER REVISION DATE 0 8/03 1 3/09 DESCRIPTION PAGES CHANGED Initial release. — Added a lead-free package to the Ordering Information table. 1 Changed the package code from T2444-1 to T2444-3 and replaced the package outline drawings with the Package Information table. 1, 6 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 7 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX3841 Revision History