19-2153; Rev 0; 9/01 KIT ATION EVALU E L B A AVAIL 3.125Gbps XAUI Quad Equalizer Features ♦ Four Differential Digital Data “Lanes” at 3.125Gbps ♦ Spans 40in (1.0m) of FR4 PC Board ♦ Receiver Equalization Reduces Intersymbol Interference (ISI) ♦ Low-Power, 175mW per Channel ♦ Standby Mode—Power-Down State ♦ Single +3.3V Supply ♦ Signal Detect Applications Ordering Information IEEE-802.3ae XAUI Interface (3.125Gbps) PART InfiniBand (2.5Gbps) TEMP. RANGE MAX3980UGH PIN-PACKAGE 0°C to +85°C 44 QFN-EP* *Exposed pad Pin Configuration appears at end of data sheet. Typical Application Circuit SWITCH CARD LINE CARD PC BOARD BACKPLANE PMD MAC SWITCH ≤ 40in (1.0m) Rx Tx 4 Rx 4 Tx IN 4 x 3.125Gbps +3.3V SUPPLY 4x 3.125Gbps 10GbE Tx Rx 4 Tx Rx 4 OUT MAX3980 MAX3980 OUT 4 Rx +3.3V SUPPLY 4 IN Tx ≤ 40in (1.0m) ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3980 General Description The MAX3980 quad equalizer provides compensation for transmission medium losses for four “lanes” of digital NRZ data at a 3.125Gbps data rate in one package. It is tailor-made for 10-Gigabit Ethernet (10GbE) backplane applications requiring attenuation of noise and jitter that occur in communicating from MAC to PMD or from MAC to Switch. In support of the IEEE-802.3ae for the XAUI interface, the MAX3980 adaptively allows XAUI lanes to reach up to 40in (1.0m) on FR4 board material. The equalizer has 100Ω differential CML data inputs and outputs. The MAX3980 is available in a 44-pin exposed-pad QFN package. The MAX3980 consumes only 700mW at +3.3V or 175mW per channel. MAX3980 3.125Gbps XAUI Quad Equalizer ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC.............................................-0.5V to +4.0 V Voltage at SDET, IN_± ..............................+0.5V to (VCC + 0.5V) Current Out of OUT_±.......................................-25mA to +25mA Continuous Power Dissipation (TA = +85°C) 44-Pin QFN-EP (derate 26.3mW/°C above +85°C)...2105mW Operating Ambient Temperature Range ................0°C to +85°C Storage Temperature Range .............................-55°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, input data rate = 3.125Gbps, TA = 0°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP EN = TTL low Supply Power Supply Noise Tolerance 0.25 EN = TTL high 0.7 10Hz < f < 100Hz 100 100Hz < f < 1MHz 40 1MHz < f < 2.5GHz 10 Signal Detect Assert Input signal level to assert SDET (Note 1) Signal Detect Deassert Input signal level to deassert SDET (Note 1) 0.9 From input to output UNITS W mVp-p 100 mVp-p Signal Detect Delay Latency MAX 30 mVp-p 10 µs 0.32 ns CML RECEIVER INPUT XAUI transmitter output measured differentially at point A, Figure 1, using K28.5 pattern Input Voltage Swing Return Loss 100MHz to 2.5GHz Input Resistance Differential 200 800 12 80 100 mVp-p dB 120 Ω EQUALIZATION Residual Jitter Random Jitter Total jitter (Note 2) 0.3 Deterministic jitter 0.2 (Note 2) 1.5 UIp-p psRMS CML TRANSMITTER OUTPUT (into 100Ω ±1Ω) Output Voltage Swing Differential swing 550 Common-Mode Voltage Transition Time tf, tr 20% to 80% (Note 3) Differential Skew Difference in 50% crossing between OUT_+ and OUT_- Output Resistance Single ended 2 850 mVp-p 130 ps 12 ps 60 Ω VCC - 0.3 60 40 50 _______________________________________________________________________________________ V 3.125Gbps XAUI Quad Equalizer (VCC = +3.0V to +3.6V, input data rate = 3.125Gbps, TA = 0°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TTL CONTROL PINS Input High Voltage 2.0 V Input Low Voltage 0.8 V Input High Current 250 µA Input Low Current 500 µA Output High Voltage Internal 10kΩ pullup Output Low Voltage Internal 10kΩ pullup 2.4 V 0.4 V Note 1: K28.7 pattern is applied differentially at point A as shown in Figure 1. Note 2: Total jitter does not include the signal source jitter. Total jitter (TJ) = [14.1 x RJ + DJ] where RJ is random RMS jitter and DJ is maximum deterministic jitter. Signal source is a K28.5± pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or equivalent for the random jitter test. Residual jitter is that which remains after equalizing media-induced losses of the environment of Figure 1 or its equivalent. The deterministic jitter at point B must be from mediainduced loss and not from clock-source modulation. Jitter is measured at 0 at point C of Figure 1. Note 3: Using K28.7 (0011111000) pattern. C B A FR4 STRIPLINE ≤ 40in (1m) MAX3980 SMA CONNECTOR SMA CONNECTOR IN OUT Figure 1. Test Conditions Referenced in the Electrical Characteristics Table _______________________________________________________________________________________ 3 MAX3980 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (VCC = +3.3V, 3.125Gbps, 500mVp-p board input with 27 - 1 PRBS, TA = +25°C, unless otherwise noted.) MAX3980 toc01 MAX3980 toc02 EQUALIZER OUTPUT EYE DIAGRAM (20in BACKPLANE WITH TWO TERADYNE HSD CONNECTORS AND 3in DAUGHTERBOARD) 100mV/ div 50mV/ div MAX3980 toc03 EQUALIZER OUTPUT EYE DIAGRAM AFTER EQUALIZATION (40in FR4 6mil STRIPLINE) EQUALIZER INPUT EYE DIAGRAM BEFORE EQUALIZATION (40in FR4 6mil STRIPLINE) 100mV/ div 50ps/div 50ps/div 50ps/div INPUT RETURN GAIN (S11, DIFFERENTIAL, INPUT SIGNAL = -60dBm, DEVICE POWERED OFF) EQUALIZER DETERMINISTIC JITTER vs. LENGTH (FR4 6mil STRIPLINE, K28.5 PATTERN) EQUALIZER LATENCY vs. TEMPERATURE 35 MAX3980 toc06 0 500 MAX3980 toc05 40 MAX3980 toc04 10 450 30 -20 400 25 DELAY (ps) JITTER (ps) -10 GAIN (dB) 20 15 -30 350 300 10 -40 250 5 0 -50 50 1050 2050 3050 4050 200 0 5050 10 20 30 40 50 LENGTH (in) FREQUENCY (MHz) 0 10 20 30 40 MAX3980 toc07 210 NORMAL OPERATION (EN = TTL HIGH) 190 170 150 130 110 90 STANDBY POWER (EN = TTL LOW) 70 50 0 10 20 30 40 50 60 70 80 TEMPERATURE (°C) 4 50 60 TEMPERATURE (°C) EQUALIZER OPERATING CURRENT vs. TEMPERATURE CURRENT (mA) MAX3980 3.125Gbps XAUI Quad Equalizer _______________________________________________________________________________________ 70 80 90 3.125Gbps XAUI Quad Equalizer PIN NAME FUNCTION 1, 5, 9, 13, 23, 27, 31, 35 VCC 2 IN1+ Positive Equalizer Input Channel 1, CML 3 IN1- Negative Equalizer Input Channel 1, CML 4, 8, 12, 16, 26, 30, 34, 38 GND Supply Ground 6 IN2+ Positive Equalizer Input Channel 2, CML 7 IN2- Negative Equalizer Input Channel 2, CML 10 IN3+ Positive Equalizer Input Channel 3, CML 11 IN3- Negative Equalizer Input Channel 3, CML 14 IN4+ Positive Equalizer Input Channel 4, CML Negative Equalizer Input Channel 4, CML +3.3V Supply Voltage 15 IN4- 17–22, 39–42 N.C. 24 OUT4- 25 OUT4+ Positive Equalizer Output Channel 4, CML 28 OUT3- Negative Equalizer Output Channel 3, CML 29 OUT3+ Positive Equalizer Output Channel 3, CML 32 OUT2- Negative Equalizer Output Channel 2, CML 33 OUT2+ Positive Equalizer Output Channel 2, CML 36 OUT1- Negative Equalizer Output Channel 1, CML 37 OUT1+ 43 EN 44 SDET EP Exposed Pad No Connection. Leave unconnected. Negative Equalizer Output Channel 4, CML Positive Equalizer Output Channel 1, CML Enable Equalizer Input. A TTL high selects normal operation. A TTL low selects low-power standby mode. Signal Detect Output for Channel 1. Produces a TTL high output when a signal is detected. Ground. The exposed pad must be soldered to the circuit board ground plane for proper thermal and electrical performance. _______________________________________________________________________________________ 5 MAX3980 Pin Description 3.125Gbps XAUI Quad Equalizer MAX3980 Functional Diagram IP1, IN1 ONLY IN1+ IN1- 2 2 SIGNAL DETECT OUT1+ 3 3 CML 4 4 3 3 EN SDET FUNCTION IS INDEPENDENT OF EN OUT1- 2 2 2 2 LIMITING AMP EQUALIZER 2 3 4 4 4 POWER MANAGEMENT Detailed Description Receiver and Transmitter The receiver accepts four lanes of 3.125Gbps currentmode logic (CML) digital data signals. The adaptive equalizer compensates each received signal for dielectric and skin losses. The limiting amp shapes the output of the equalizer. The regenerated XAUI lanes are transmitted as CML signals. The source impedance and termination impedances are 100Ω differential. General Theory of Operation Internally, the MAX3980 comprises signal-detect circuitry, four matched equalizers, and one equalizercontrol loop. The four equalizers are made up of a master equalizer and three slave equalizers. The adaptive control is generated from only channel 1. It is assumed that all channels have the same characterization in frequency content, coding, and transmission length. The master equalizer consists of the following functions: signal detect, adaptive equalizer, equalizer control, and limiting and output drivers. The signal detect indicates input signal power. When the input signal level is sufficiently high, the SDET output is asserted. This does not directly control the operation of the part. The equalizer core reduces intersymbol interference (ISI), compensating for frequency-dependent, mediainduced loss. The equalization control detects the spectral contents of the input signal and provides a control voltage to the equalizer core, adapting it to different media. The equalizer operation is optimized for 6 SDET TTL 3 2 3 3 4 4 4 MAX3980 short-run DC-balanced transmission codes such as 8b/10b codes. CML Input and Output Buffers The input and output buffers are implemented using CML. Equivalent circuits are shown in Figures 2 and 3. For details on interfacing with CML, see Maxim application note HFAN-1.0, Interfacing Between CML, PECL, and LVDS. The common-mode voltage of the input and output is above 2.5V. AC-coupling capacitors are required when interfacing this part. Values of 0.10µF or greater are recommended. Media Equalization Equalization at the input port compensates for the highfrequency loss encountered with up to 40in (1.0m) of FR4 transmission lines. This part is optimized for 40in and 3.125Gbps; however, the part reduces ISI for signals spanning longer distances and functions for data rates from 2Gbps to 4Gbps, provided that short-length balanced codes, such as 8b/10b, are used. Applications Information Standby Mode The power-saver standby state allows reduced-power operation. The TTL input, EN, must be set to TTL high for normal operation. A TTL low at EN forces the equalizer into the standby state. The signal EN does not affect the operation of the signal detect (SDET) function. For constant operation, connect the EN signal directly to VCC. _______________________________________________________________________________________ 3.125Gbps XAUI Quad Equalizer MAX3980 VCC VCC 50Ω 50Ω 1.2kΩ OUT+ 50Ω 50Ω OUT- IN+ Q1 Q2 INDATA ESD STRUCTURES 200µA ESD STRUCTURES Figure 2. CML Input Buffer Figure 3. CML Output Buffer Signal Detect with Standby Mode VCC GND 35 36 37 N.C. GND OUT1+ OUT139 38 N.C. N.C. 41 40 EN N.C. 43 42 SDET 44 34 OUT2+ OUT2VCC VCC IN1+ IN1GND VCC IN2+ 1 33 2 32 3 31 4 30 5 29 IN2GND 7 27 8 26 GND OUT3+ OUT3VCC GND VCC 9 25 OUT4+ IN3+ 10 24 IN3- 11 23 OUT4VCC 6 28 22 21 20 19 N.C. N.C. N.C. N.C. 18 17 16 14 IN4+ IN4GND N.C. N.C. 15 13 MAX3980 12 Circuit-board layout and design can significantly affect the MAX3980 performance. Use good high-frequency design techniques, including minimizing ground inductances and vias and using controlled-impedance transmission lines for the high-frequency data signals. Signals should be routed differentially to reduce EMI susceptibility and crosstalk. Power-supply decoupling capacitors should be placed as close as possible to the VCC pins. TOP VIEW VCC Layout Considerations Pin Configuration GND Signal activity is detected on channel 1 only. When the peak-to-peak differential voltage at IN1± is less than 30mVp-p, the TTL output SDET goes low. When the peak-to-peak differential voltage becomes greater than 100mVp-p, SDET is asserted high. SDET can be used to automatically force the equalizer into standby mode by connecting SDET directly to the EN input. When not used, SDET should not be connected. The signal-detect function continues to operate while the part is in standby mode. While connected to the EN pin, the signal detect can “wake up” the part and resume normal operation. QFN* *NOTE: THE EXPOSED PAD MUST BE SOLDERED TO SUPPLY GROUND. _______________________________________________________________________________________ 7 3.125Gbps XAUI Quad Equalizer QFN 28, 32,44, 48L.EPS MAX3980 Package Information 8 _______________________________________________________________________________________ 3.125Gbps XAUI Quad Equalizer Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9 © 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX3980 Package Information (continued)