MAXIM MAX11616EEE+

19-4561; Rev 3; 2/11
KIT
ATION
EVALU
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L
B
A
IL
AVA
Low-Power, 4-/8-/12-Channel, I2C,
12-Bit ADCs in Ultra-Small Packages
Applications
Handheld Portable
Applications
Solar-Powered Remote
Systems
Medical Instruments
Received-Signal-Strength
Indicators
Battery-Powered Test
Equipment
System Supervision
Features
o High-Speed I2C-Compatible Serial Interface
o
o
o
o
o
o
o
o
o
o
o
400kHz Fast Mode
1.7MHz High-Speed Mode
Single-Supply
2.7V to 3.6V (MAX11613/MAX11615/MAX11617)
4.5V to 5.5V (MAX11612/MAX11614/MAX11616)
Ultra-Small Packages
8-Pin µMAX (MAX11612/MAX11613)
1.9mm x 2.2mm, 12-Bump WLP (MAX11613)
16-Pin QSOP (MAX11614–MAX11617)
Internal Reference
2.048V (MAX11613/MAX11615/MAX11617)
4.096V (MAX11612/MAX11614/MAX11616)
External Reference: 1V to VDD
Internal Clock
4-Channel Single-Ended or 2-Channel Fully
Differential (MAX11612/MAX11613)
8-Channel Single-Ended or 4-Channel Fully
Differential (MAX11614/MAX11615)
12-Channel Single-Ended or 6-Channel Fully
Differential (MAX11616/MAX11617)
Internal FIFO with Channel-Scan Mode
Low Power
670µA at 94.4ksps
230µA at 40ksps
60µA at 10ksps
6µA at 1ksps
0.5µA in Power-Down Mode
Software-Configurable Unipolar/Bipolar
Ordering Information
I2C SLAVE
ADDRESS
TEMP RANGE
PINPACKAGE
MAX11612EUA+
-40°C to +85°C
8 µMAX
MAX11613EUA+
-40°C to +85°C
8 µMAX
0110100
MAX11613EWC+* -40°C to +85°C
12 WLP
0110100
PART
0110100
MAX11614EEE+
-40°C to +85°C
16 QSOP
0110011
MAX11615EEE+
-40°C to +85°C
16 QSOP
0110011
MAX11616EEE+
-40°C to +85°C
16 QSOP
0110101
MAX11617EEE+
-40°C to +85°C
16 QSOP
0110101
+Denotes a lead(Pb)-free/RoHs-compliant package.
*Future product—contact factory for availability.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
Pin Configurations, Typical Operating Circuit, and Selector
Guide appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX11612–MAX11617
General Description
The MAX11612–MAX11617 low-power, 12-bit, multichannel analog-to-digital converters (ADCs) feature
internal track/hold (T/H), voltage reference, clock, and an
I2C-compatible 2-wire serial interface. These devices
operate from a single supply of 2.7V to 3.6V
(MAX11613/MAX11615/MAX11617) or 4.5V to 5.5V
(MAX11612/MAX11614/MAX11616) and require only
670µA at the maximum sampling rate of 94.4ksps.
Supply current falls below 230µA for sampling rates
under 46ksps. AutoShutdown™ powers down the
devices between conversions, reducing supply current
to less than 1µA at low throughput rates. The
MAX11612/MAX11613 have 4 analog input channels
each, the MAX11614/MAX11615 have 8 analog input
channels each, while the MAX11616/MAX11617 have
12 analog input channels each. The fully differential
analog inputs are software configurable for unipolar or
bipolar, and single-ended or differential operation.
The full-scale analog input range is determined by the
internal reference or by an externally applied reference
voltage ranging from 1V to V DD . The MAX11613/
MAX11615/MAX11617 feature a 2.048V internal reference and the MAX11612/MAX11614/MAX11616 feature
a 4.096V internal reference.
The MAX11612/MAX11613 are available in an 8-pin
µMAX® package and the MAX11613 is available in an
ultra-small, 1.9mm x 2.2mm, 12-bump wafer-level package (WLP). The MAX11614–MAX11617 are available in a
16-pin QSOP package. The MAX11612–MAX11617 are
guaranteed over the extended temperature range (-40°C
to +85°C). For pin-compatible 10-bit parts, refer to the
MAX11606–MAX11611 data sheet. For pin-compatible 8bit parts, refer to the MAX11600–MAX11605 data sheet.
MAX11612–MAX11617
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V
AIN0–AIN11,
REF to GND ............-0.3V to the lower of (VDD + 0.3V) and 6V
SDA, SCL to GND.....................................................-0.3V to +6V
Maximum Current into Any Pin .........................................±50mA
Continuous Power Dissipation (TA = +70°C)
8-Pin µMAX (derate 5.9mW/°C above +70°C) ..........470.6mW
16-Pin QSOP (derate 8.3mW/°C above +70°C)........666.7mW
12-Pin WLP (derate 16.1mW/°C above +70°C) .........1288mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 2.7V to 3.6V (MAX11613/MAX11615/MAX11617), VDD = 4.5V to 5.5V (MAX11612/MAX11614/MAX11616), VREF = 2.048V
(MAX11613/MAX11615/MAX11617), VREF = 4.096V (MAX11612/MAX11614/MAX11616), fSCL = 1.7MHz, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C, see Tables 1–5 for programming notation.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 2)
Resolution
12
Bits
Relative Accuracy
INL
(Note 3)
±1
LSB
Differential Nonlinearity
DNL
No missing codes over temperature
±1
LSB
±4
LSB
Offset Error
Offset-Error Temperature
Coefficient
Relative to FSR
Gain Error
(Note 4)
Gain-Temperature Coefficient
Relative to FSR
0.3
ppm/°C
±4
LSB
0.3
ppm/°C
Channel-to-Channel Offset
Matching
±0.1
LSB
Channel-to-Channel Gain
Matching
±0.1
LSB
70
dB
-78
dB
DYNAMIC PERFORMANCE (fIN(SINE-WAVE) = 10kHz, VIN(P-P) = VREF, fSAMPLE = 94.4ksps)
Signal-to-Noise Plus Distortion
SINAD
Total Harmonic Distortion
THD
Spurious-Free Dynamic Range
SFDR
Up to the 5th harmonic
78
dB
Full-Power Bandwidth
SINAD > 68dB
3
MHz
Full-Linear Bandwidth
-3dB point
5
MHz
CONVERSION RATE
Conversion Time (Note 5)
2
tCONV
Internal clock
External clock
7.5
10.6
_______________________________________________________________________________________
µs
Low-Power, 4-/8-/12-Channel, I2C,
12-Bit ADCs in Ultra-Small Packages
(VDD = 2.7V to 3.6V (MAX11613/MAX11615/MAX11617), VDD = 4.5V to 5.5V (MAX11612/MAX11614/MAX11616), VREF = 2.048V
(MAX11613/MAX11615/MAX11617), VREF = 4.096V (MAX11612/MAX11614/MAX11616), fSCL = 1.7MHz, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C, see Tables 1–5 for programming notation.) (Note 1)
PARAMETER
Throughput Rate
SYMBOL
fSAMPLE
CONDITIONS
MIN
51
Internal clock, SCAN[1:0] = 00
CS[3:0] = 1011 (MAX11616/MAX11617)
51
External clock
Track/Hold Acquisition Time
MAX
ksps
800
ns
2.8
tAD
UNITS
94.4
Internal Clock Frequency
Aperture Delay (Note 6)
TYP
Internal clock, SCAN[1:0] = 01
External clock, fast mode
60
External clock, high-speed mode
30
MHz
ns
ANALOG INPUT (AIN0–AIN11)
Input-Voltage Range, SingleEnded and Differential (Note 7)
Unipolar
0
VREF
Bipolar
0
±VREF/2
Input Multiplexer Leakage Current
ON/OFF leakage current, VAIN_ = 0 or VDD
Input Capacitance
±0.01
CIN
±1
22
V
µA
pF
INTERNAL REFERENCE (Note 8)
Reference Voltage
VREF
Reference-Voltage Temperature
Coefficient
TA = +25°C
MAX11613/MAX11615/MAX11617
1.968
2.048
2.128
MAX11612/MAX11614/MAX11616
3.936
4.096
4.256
TCVREF
25
REF Short-Circuit Current
ppm/°C
2
REF Source Impedance
V
1.5
mA
kΩ
EXTERNAL REFERENCE
REF Input-Voltage Range
VREF
(Note 9)
REF Input Current
IREF
fSAMPLE = 94.4ksps
1
VDD
V
40
µA
DIGITAL INPUTS/OUTPUTS (SCL, SDA)
Input-High Voltage
Input-Low Voltage
Input Hysteresis
Input Current
VIH
0.7 x VDD
V
VIL
0.3 x VDD
VHYST
IIN
Input Capacitance
CIN
Output Low Voltage
VOL
0.1 x VDD
V
±10
VIN = 0 to VDD
15
ISINK = 3mA
V
µA
pF
0.4
V
_______________________________________________________________________________________
3
MAX11612–MAX11617
ELECTRICAL CHARACTERISTICS (continued)
MAX11612–MAX11617
Low-Power, 4-/8-/12-Channel, I2C,
12-Bit ADCs in Ultra-Small Packages
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V (MAX11613/MAX11615/MAX11617), VDD = 4.5V to 5.5V (MAX11612/MAX11614/MAX11616), VREF = 2.048V
(MAX11613/MAX11615/MAX11617), VREF = 4.096V (MAX11612/MAX11614/MAX11616), fSCL = 1.7MHz, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C, see Tables 1–5 for programming notation.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
Supply Voltage
VDD
MAX11613/MAX11615/MAX11617
2.7
3.6
MAX11612/MAX11614/MAX11616
4.5
5.5
fSAMPLE = 94.4ksps
external clock
Supply Current
IDD
PSRR
900
1150
External reference
670
900
fSAMPLE = 40ksps
internal clock
Internal reference
530
External reference
230
fSAMPLE = 10ksps
internal clock
Internal reference
380
External reference
60
Internal reference
330
fSAMPLE =1ksps
internal clock
Power-Supply Rejection Ratio
Internal reference
External reference
V
µA
6
Shutdown (internal REF off)
0.5
10
Full-scale input (Note 10)
±0.5
±2.0
LSB/V
TIMING CHARACTERISTICS (Figure 1)
(VDD = 2.7V to 3.6V (MAX11613/MAX11615/MAX11617), VDD = 4.5V to 5.5V (MAX11612/MAX11614/MAX11616), VREF = 2.048V
(MAX11613/MAX11615/MAX11617), VREF = 4.096V (MAX11612/MAX11614/MAX11616), fSCL = 1.7MHz, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C, see Tables 1–5 for programming notation.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
400
kHz
TIMING CHARACTERISTICS FOR FAST MODE
Serial-Clock Frequency
fSCL
Bus Free Time Between a STOP (P)
and a START (S) Condition
tBUF
1.3
µs
Hold Time for START (S) Condition
tHD, STA
0.6
µs
Low Period of the SCL Clock
tLOW
1.3
µs
High Period of the SCL Clock
tHIGH
0.6
µs
Setup Time for a Repeated START
Condition (Sr)
tSU, STA
0.6
µs
Data Hold Time (Note 11)
tHD, DAT
0
Data Setup Time
tSU, DAT
100
Rise Time of Both SDA and SCL
Signals, Receiving
Fall Time of SDA Transmitting
900
ns
ns
tR
Measured from 0.3VDD - 0.7VDD
20 + 0.1CB
300
tF
Measured from 0.3VDD - 0.7VDD (Note 12)
20 + 0.1CB
300
ns
Setup Time for STOP (P) Condition
tSU, STO
Capacitive Load for Each Bus Line
CB
400
pF
Pulse Width of Spike Suppressed
tSP
50
ns
4
0.6
ns
_______________________________________________________________________________________
µs
Low-Power, 4-/8-/12-Channel, I2C,
12-Bit ADCs in Ultra-Small Packages
(VDD = 2.7V to 3.6V (MAX11613/MAX11615/MAX11617), VDD = 4.5V to 5.5V (MAX11612/MAX11614/MAX11616), VREF = 2.048V
(MAX11613/MAX11615/MAX11617), VREF = 4.096V (MAX11612/MAX11614/MAX11616), fSCL = 1.7MHz, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C, see Tables 1–5 for programming notation.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
1.7
MHz
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (CB = 400pF, Note 13)
Serial-Clock Frequency
Hold Time, Repeated START
Condition (Sr)
fSCLH
(Note 14)
tHD, STA
160
ns
Low Period of the SCL Clock
tLOW
320
ns
High Period of the SCL Clock
tHIGH
120
ns
Setup Time for a Repeated START
Condition (Sr)
tSU, STA
160
ns
Data Hold Time
tHD, DAT
Data Setup Time
tSU, DAT
10
Rise Time of SCL Signal
(Current Source Enabled)
tRCL
20
80
ns
Rise Time of SCL Signal After
Acknowledge Bit
tRCL1
Measured from 0.3VDD - 0.7VDD
20
160
ns
Fall Time of SCL Signal
tFCL
Measured from 0.3VDD - 0.7VDD
20
80
ns
Rise Time of SDA Signal
tRDA
Measured from 0.3VDD - 0.7VDD
20
160
ns
tFDA
Measured from 0.3VDD - 0.7VDD (Note 12)
20
160
Fall Time of SDA Signal
Setup Time for STOP (P) Condition
tSU, STO
Capacitive Load for Each Bus Line
CB
Pulse Width of Spike Suppressed
tSP
(Note 11)
0
150
160
(Notes 11 and 14)
0
ns
ns
ns
ns
400
pF
10
ns
Note 1: All WLP devices are 100% production tested at TA = +25°C. Specifications over temperature limits are guaranteed by
design and characterization.
Note 2: For DC accuracy, the MAX11612/MAX11614/MAX11616 are tested at VDD = 5V and the
MAX11613/MAX11615/MAX11617are tested at VDD = 3V. All devices are configured for unipolar, single-ended inputs.
Note 3: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 4: Offset nulled.
Note 5: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion
time does not include acquisition time. SCL is the conversion clock in the external clock mode.
Note 6: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 7: The absolute input-voltage range for the analog inputs (AIN0–AIN11) is from GND to VDD.
Note 8: When the internal reference is configured to be available at AIN_/REF (SEL[2:1] = 11), decouple AIN_/REF to GND with a
0.1µF capacitor and a 2kΩ series resistor (see the Typical Operating Circuit).
Note 9: ADC performance is limited by the converter’s noise floor, typically 300µVP-P.
Note 10: Measured as for the MAX11613/MAX11615/MAX11617:
_______________________________________________________________________________________
5
MAX11612–MAX11617
TIMING CHARACTERISTICS (Figure 1) (continued)
TIMING CHARACTERISTICS (Figure 1) (continued)
(VDD = 2.7V to 3.6V (MAX11613/MAX11615/MAX11617), VDD = 4.5V to 5.5V (MAX11612/MAX11614/MAX11616), VREF = 2.048V
(MAX11613/MAX11615/MAX11617), VREF = 4.096V (MAX11612/MAX11614/MAX11616), fSCL = 1.7MHz, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C, see Tables 1–5 for programming notation.) (Note 1)
and for the MAX11612/MAX11614/MAX11616, where N is the number of bits:
⎡
2N − 1⎤
⎢[VFS (5.5V) − VFS (4.5V)] ×
⎥
VREF ⎥⎦
⎢⎣
(5.5V − 4.5V)
Note 11: A master device must provide a data hold time for SDA (referred to VIL of SCL) to bridge the undefined region of SCL’s
falling edge (see Figure 1).
Note 12: The minimum value is specified at TA = +25°C.
Note 13: CB = total capacitance of one bus line in pF.
Note 14: fSCL must meet the minimum clock low time plus the rise/fall times.
Typical Operating Characteristics
(VDD = 3.3V (MAX11613/MAX11615/MAX11617), VDD = 5V (MAX11612/MAX11614/MAX11616), fSCL = 1.7MHz, (50% duty cycle),
fSAMPLE = 94.4ksps, single-ended, unipolar, TA = +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. DIGITAL CODE
0.8
0.2
0.4
0.1
0.2
0
0.1
-0.2
-0.4
-0.3
-0.6
-0.4
-0.8
-0.5
500 1000 1500 2000 2500 3000 3500 4000
300
10k
20k
30k
40k
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
EXTERNAL REFERENCE MAX11616/MAX11614/
MAX11612
0.4
0.3
0.2
-40 -25 -10
5
20
35
50
TEMPERATURE (°C)
65
80
0.45
0.40
MAX11616/MAX11614/MAX11612
0.35
0.30
0.25
0.20
MAX11617/MAX11615/MAX11613
0.15
0.10
0.1
EXTERNAL REFERENCE MAX11617/MAX11615/
MAX11613
MAX11612 toc06
MAX11612 toc05
0.5
50k
0.50
SUPPLY CURRENT (µA)
INTERNAL REFERENCE MAX11617/MAX11615/
MAX11613
SDA = SCL = VDD
IDD (µA)
SETUP BYTE
EXT REF: 10111011
INT REF: 11011011
0.6
MAX11612 toc04
INTERNAL REFERENCE MAX11616/MAX11614/
MAX11612
400
350
0
500 1000 1500 2000 2500 3000 3500 4000
SUPPLY CURRENT
vs. TEMPERATURE
600
450
-180
0
FREQUENCY (Hz)
650
500
-140
DIGITAL OUTPUT CODE
700
550
-120
DIGITAL OUTPUT CODE
800
750
-100
-160
-1.0
0
6
0
-0.2
fSAMPLE = 94.4ksps
fIN = 10kHz
-80
AMPLITUDE (dBc)
0.6
INL (LSB)
DNL (LSB)
0.3
-60
MAX11612 toc02
0.4
FFT PLOT
1.0
MAX11612 toc01
0.5
MAX11612 toc03
DIFFERENTIAL NONLINEARITY
vs. DIGITAL CODE
SUPPLY CURRENT (µA)
MAX11612–MAX11617
Low-Power, 4-/8-/12-Channel, I2C,
12-Bit ADCs in Ultra-Small Packages
0.05
0
0
2.7
3.2
3.7
4.2
4.7
SUPPLY VOLTAGE (V)
5.2
-40 -25 -10
5
20
35
50
TEMPERATURE (°C)
_______________________________________________________________________________________
65
80
Low-Power, 4-/8-/12-Channel, I2C,
12-Bit ADCs in Ultra-Small Packages
700
B
A
600
500
B
400
MAX11617/MAX11615/MAX11613
0.9990
20
0
40
60
80
100
-40 -25 -10
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
65
1.6
1.2
80
0.8
0.4
0
-0.4
-0.8
-0.8
-1.2
-0.9
-1.6
-2.0
-1.0
-40 -25 -10
2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4
50
MAX11612 toc12
-0.1
MAX11617/MAX11615/MAX11613
NORMALIZED TO
REFERENCE VALUE AT
VDD = 3.3V
35
OFFSET ERROR vs. SUPPLY VOLTAGE
OFFSET ERROR (LSB)
0.99996
20
2.0
MAX11612 toc11
MAX11612 toc10
0.99998
5
TEMPERATURE (°C)
0
OFFSET ERROR (LSB)
1.00000
5
20
35
50
65
2.7
80
3.2
3.7
4.2
4.7
5.2 5.5
VDD (V)
TEMPERATURE (°C)
VDD (V)
GAIN ERROR vs. SUPPLY VOLTAGE
GAIN ERROR vs. TEMPERATURE
1.8
1.6
1.6
1.2
GAIN ERROR (LSB)
1.4
1.2
1.0
0.8
MAX11612 toc14
2.0
MAX11612 toc13
2.0
GAIN ERROR (LSB)
VREF (V)
1.00002
0.99990
0.9998
OFFSET ERROR vs. TEMPERATURE
MAX11616/MAX11614/MAX11612
NORMALIZED TO
REFERENCE VALUE AT
VDD = 5V
1.00004
1.0000
CONVERSION RATE (ksps)
1.00010
1.00006
1.0002
0.9992
MAX11617/MAX11615/MAX11613
NORMALIZED REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
1.00008
MAX11616/MAX11614/MAX11612
1.0004
0.9996
200
CONVERSION RATE (ksps)
0.99992
1.0006
0.9994
MAX11616/MAX11614/MAX11612
10 20 30 40 50 60 70 80 90 100
NORMALIZED TO VALUE AT TA = +25°C
1.0008
300
0
0.99994
1.0010
VREF NORMALIZED
A
A) INTERNAL REFERENCE ALWAYS ON
B) EXTERNAL REFERENCE
MAX11612 toc09
800
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX11612 toc08
A) INTERNAL REFERENCE ALWAYS ON
B) EXTERNAL REFERENCE
MAX11612 toc07
800
750
700
650
600
550
500
450
400
350
300
250
200
AVERAGE SUPPLY CURRENT vs.
CONVERSION RATE (EXTERNAL CLOCK)
AVERAGE IDD (µA)
AVERAGE IDD (µA)
AVERAGE SUPPLY CURRENT vs.
CONVERSION RATE (EXTERNAL CLOCK)
0.8
0.4
0
-0.4
0.6
-0.8
0.4
-1.2
0.2
-1.6
-2.0
0
-40 -25
-10
5
20
35
50
TEMPERATURE (°C)
65
80
2.7
3.2
3.7
4.2
4.7
5.2 5.5
VDD (V)
_______________________________________________________________________________________
7
MAX11612–MAX11617
Typical Operating Characteristics (continued)
(VDD = 3.3V (MAX11613/MAX11615/MAX11617), VDD = 5V (MAX11612/MAX11614/MAX11616), fSCL = 1.7MHz, (50% duty cycle),
fSAMPLE = 94.4ksps, single-ended, unipolar, TA = +25°C, unless otherwise noted.)
Low-Power, 4-/8-/12-Channel, I2C,
12-Bit ADCs in Ultra-Small Packages
MAX11612–MAX11617
Pin Description
PIN
MAX11612
MAX11613
MAX11614
MAX11615
MAX11616
MAX11617
NAME
FUNCTION
5, 6, 7
AIN0, AIN1, AIN2
µMAX
WLP
1, 2, 3
A1, A2, A3
5, 6, 7
—
—
8–12
8–12
AIN3–AIN7
—
—
—
4, 3, 2
AIN8–AIN10
4
A4
—
—
AIN3/REF
—
—
1
—
REF
—
—
—
1
AIN11/REF
5
C4
13
13
SCL
Clock Input
6
C3
14
14
SDA
Data Input/Output
7
B1, B2, B3,
B4, C2
15
15
GND
Ground
8
C1
16
16
VDD
Positive Supply. Bypass to GND with a 0.1µF capacitor.
—
—
2, 3, 4
—
N.C.
No connection. Not internally connected.
Analog Inputs
Analog Input 3/Reference Input or Output. Selected in
the setup register (see Tables 1 and 6).
Reference Input or Output. Selected in the setup
register (see Tables 1 and 6).
Analog Input 11/Reference Input or Output. Selected in
the setup register (see Tables 1 and 6).
A. F/S-MODE 2-WIRE SERIAL-INTERFACE TIMING
tR
tF
t
SDA
tSU.DAT
tHD.DAT
tLOW
tHD.STA
tBUF
tSU.STA
tSU.STO
SCL
tHD.STA
tHIGH
tR
tF
S
A
Sr
P
B. HS-MODE 2-WIRE SERIAL-INTERFACE TIMING
S
tRDA
tFDA
SDA
tSU.DAT
tHD.DAT
tLOW
tBUF
tHD.STA
tSU.STO
tSU.STA
SCL
tHD.STA
tHIGH
tRCL
tFCL
tRCL1
S
Sr
A
P
HS MODE
Figure 1. 2-Wire Serial-Interface Timing
8
_______________________________________________________________________________________
S
F/S MODE
Low-Power, 4-/8-/12-Channel, I2C,
12-Bit ADCs in Ultra-Small Packages
MAX11612–MAX11617
SDA
SCL
INPUT SHIFT REGISTER
VDD
SETUP REGISTER
GND
CONTROL
LOGIC
INTERNAL
OSCILLATOR
CONFIGURATION REGISTER
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11/REF
T/H
ANALOG
INPUT
MUX
12-BIT
ADC
OUTPUT SHIFT
REGISTER
AND RAM
REF
REFERENCE
4.096V (MAX11616)
2.048V (MAX11617)
MAX11616
MAX11617
Figure 2. MAX11616/MAX11617 Simplified Functional Diagram
2-wire serial interface supporting data rates up to
1.7MHz. Figure 2 shows the simplified internal structure
for the MAX11616/MAX11617.
VDD
IOL
Power Supply
VOUT
SDA
400pF
IOH
The MAX11612–MAX11617 operate from a single supply and consume 670µA (typ) at sampling rates up to
94.4ksps. The MAX11613/MAX11615/MAX11617 feature a 2.048V internal reference and the MAX11612/
MAX11614/MAX11616 feature a 4.096V internal reference. All devices can be configured for use with an
external reference from 1V to VDD.
Analog Input and Track/Hold
Figure 3. Load Circuit
Detailed Description
The MAX11612–MAX11617 analog-to-digital converters
(ADCs) use successive-approximation conversion techniques and fully differential input track/hold (T/H) circuitry to capture and convert an analog signal to a
serial 12-bit digital output. The MAX11612/MAX11613
are 4-channel ADCs, the MAX11614/MAX11615 are
8-channel ADCs, and the MAX11616/MAX11617 are
12-channel ADCs. These devices feature a high-speed,
The MAX11612–MAX11617 analog-input architecture
contains an analog-input multiplexer (mux), a fully differential track-and-hold (T/H) capacitor, T/H switches, a
comparator, and a fully differential switched capacitive
digital-to-analog converter (DAC) (Figure 4).
In single-ended mode, the analog input multiplexer connects C T/H between the analog input selected by
CS[3:0] (see the Configuration/Setup Bytes (Write Cycle)
section) and GND (Table 3). In differential mode, the
analog-input multiplexer connects CT/H to the + and analog inputs selected by CS[3:0] (Table 4).
_______________________________________________________________________________________
9
During the acquisition interval, the T/H switches are in
the track position and CT/H charges to the analog input
signal. At the end of the acquisition interval, the T/H
switches move to the hold position retaining the charge
on CT/H as a stable sample of the input signal.
During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator input voltage to
0V within the limits of a 12-bit resolution. This action
requires 12 conversion clock cycles and is equivalent
to transferring a charge of 11pF (VIN+ - VIN-) from
CT/H to the binary weighted capacitive DAC, forming a
digital representation of the analog input signal.
edge of the clock during the read (R/W = 1) bit. Hold
mode is then entered on the rising edge of the second
clock pulse during the shifting out of the first byte of the
result. The conversion is performed during the next 12
clock cycles.
The time required for the T/H circuitry to acquire an
input signal is a function of the input sample capacitance. If the analog-input source impedance is high,
the acquisition time constant lengthens and more time
must be allowed between conversions. The acquisition
time (tACQ) is the minimum time needed for the signal
to be acquired. It is calculated by:
Sufficiently low source impedance is required to ensure
an accurate sample. A source impedance of up to 1.5kΩ
does not significantly degrade sampling accuracy. To
minimize sampling errors with higher source impedances,
connect a 100pF capacitor from the analog input to GND.
This input capacitor forms an RC filter with the source
impedance limiting the analog-input bandwidth. For larger source impedances, use a buffer amplifier to maintain
analog-input signal integrity and bandwidth.
When operating in internal clock mode, the T/H circuitry
enters its tracking mode on the eighth rising clock edge
of the address byte, see the Slave Address section. The
T/H circuitry enters hold mode on the falling clock edge of
the acknowledge bit of the address byte (the ninth clock
pulse). A conversion or a series of conversions is then
internally clocked and the MAX11612–MAX11617 holds
SCL low. With external clock mode, the T/H circuitry
enters track mode after a valid address on the rising
tACQ ≥ 9 (RSOURCE + RIN) CIN
where RSOURCE is the analog-input source impedance,
RIN = 2.5kΩ, and CIN = 22pF. tACQ is 1.5/fSCL for internal
clock mode and tACQ = 2/fSCL for external clock mode.
Analog Input Bandwidth
The MAX11612–MAX11617 feature input-tracking circuitry with a 5MHz small-signal bandwidth. The 5MHz input
bandwidth makes it possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using
under sampling techniques. To avoid high-frequency
signals being aliased into the frequency band of interest,
anti-alias filtering is recommended.
Analog Input Range and Protection
Internal protection diodes clamp the analog input to
VDD and GND. These diodes allow the analog inputs to
HOLD
ANALOG INPUT MUX
REF
CT/H
AIN0
AIN1
HOLD
AIN3/REF
TRACK
VDD/2
HOLD
AIN2
CAPACITIVE
DAC
TRACK
HOLD
TRACK
TRACK
MAX11612–MAX11617
Low-Power, 4-/8-/12-Channel, I2C,
12-Bit ADCs in Ultra-Small Packages
CAPACITIVE
DAC
TRACK
GND
CT/H
HOLD
REF
MAX11612
MAX11613
Figure 4. Equivalent Input Circuit
10
______________________________________________________________________________________
Low-Power, 4-/8-/12-Channel, I2C,
12-Bit ADCs in Ultra-Small Packages
Single-Ended/Differential Input
The SGL/DIF of the configuration byte configures the
MAX11612–MAX11617 analog-input circuitry for singleended or differential inputs (Table 2). In single-ended
mode (SGL/DIF = 1), the digital conversion results are
the difference between the analog input selected by
CS[3:0] and GND (Table 3). In differential mode (SGL/
DIF = 0), the digital conversion results are the difference between the + and the - analog inputs selected
by CS[3:0] (Table 4).
SCL is stable are considered control signals (see the
START and STOP Conditions section). Both SDA and
SCL remain high when the bus is not busy.
START and STOP Conditions
The master initiates a transmission with a START condition (S), a high-to-low transition on SDA while SCL is
high. The master terminates a transmission with a
STOP condition (P), a low-to-high transition on SDA
while SCL is high (Figure 5). A repeated START condition (Sr) can be used in place of a STOP condition to
leave the bus active and the interface mode
unchanged (see the HS Mode section).
Sr
S
P
Unipolar/Bipolar
When operating in differential mode, the BIP/UNI bit of
the set-up byte (Table 1) selects unipolar or bipolar
operation. Unipolar mode sets the differential input
range from 0 to VREF. A negative differential analog
input in unipolar mode causes the digital output code
to be zero. Selecting bipolar mode sets the differential
input range to ±VREF/2. The digital output code is binary in unipolar mode and two’s complement in bipolar
mode. See the Transfer Functions section.
In single-ended mode, the MAX11612–MAX11617 always operates in unipolar mode irrespective of
BIP/UNI. The analog inputs are internally referenced to
GND with a full-scale input range from 0 to VREF.
2-Wire Digital Interface
The MAX11612–MAX11617 feature a 2-wire interface
consisting of a serial-data line (SDA) and serial-clock line
(SCL). SDA and SCL facilitate bidirectional communication between the MAX11612–MAX11617 and the master
at rates up to 1.7MHz. The MAX11612–MAX11617 are
slaves that transfer and receive data. The master (typically a microcontroller) initiates data transfer on the bus
and generates the SCL signal to permit that transfer.
SDA and SCL must be pulled high. This is typically done
with pullup resistors (750Ω or greater) (see the Typical
Operating Circuit). Series resistors (RS) are optional. They
protect the input architecture of the MAX11612–
MAX11617 from high voltage spikes on the bus lines and
minimize crosstalk and undershoot of the bus signals.
SDA
SCL
Figure 5. START and STOP Conditions
Acknowledge Bits
Data transfers are acknowledged with an acknowledge
bit (A) or a not-acknowledge bit (A). Both the master
and the MAX11612–MAX11617 (slave) generate
acknowledge bits. To generate an acknowledge, the
receiving device must pull SDA low before the rising
edge of the acknowledge-related clock pulse (ninth
pulse) and keep it low during the high period of the
clock pulse (Figure 6). To generate a not-acknowledge,
the receiver allows SDA to be pulled high before the
rising edge of the acknowledge-related clock pulse
and leaves SDA high during the high period of the
clock pulse. Monitoring the acknowledge bits allows for
detection of unsuccessful data transfers. An unsuccessful data transfer happens if a receiving device is
busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master should
reattempt communication at a later time.
S
NOT ACKNOWLEDGE
SDA
Bit Transfer
One data bit is transferred during each SCL clock
cycle. A minimum of 18 clock cycles are required to
transfer the data in or out of the MAX11612–MAX11617.
The data on SDA must remain stable during the high
period of the SCL clock pulse. Changes in SDA while
ACKNOWLEDGE
SCL
1
2
8
9
Figure 6. Acknowledge Bits
______________________________________________________________________________________
11
MAX11612–MAX11617
swing from (GND - 0.3V) to (VDD + 0.3V) without causing damage to the device. For accurate conversions,
the inputs must not go more than 50mV below GND or
above VDD.
MAX11612–MAX11617
Low-Power, 4-/8-/12-Channel, I2C,
12-Bit ADCs in Ultra-Small Packages
Slave Address
A bus master initiates communication with a slave device
by issuing a START condition followed by a slave
address. When idle, the MAX11612–MAX11617 continuously wait for a START condition followed by their slave
address. When the MAX11612–MAX11617 recognize
their slave address, they are ready to accept or send
data. See the Ordering Information for the factory programmed slave address of the selected device. The
least significant bit (LSB) of the address byte (R/W)
determines whether the master is writing to or reading
from the MAX11612–MAX11617 (R/W = 0 selects a write
condition, R/W = 1 selects a read condition). After
receiving the address, the MAX11612–MAX11617
(slave) issues an acknowledge by pulling SDA low for
one clock cycle.
0
1
HS Mode
At power-up, the MAX11612–MAX11617 bus timing is
set for F/S mode. The bus master selects HS mode by
addressing all devices on the bus with the HS-mode
master code 0000 1XXX (X = don’t care). After successfully receiving the HS-mode master code, the
MAX11612–MAX11617 issue a not-acknowledge, allowing SDA to be pulled high for one clock cycle (Figure 8).
After the not-acknowledge, the MAX11612–MAX11617
are in HS mode. The bus master must then send a
repeated START followed by a slave address to initiate
HS mode communication. If the master generates a
STOP condition, the MAX11612–MAX11617 return to
F/S mode.
SLAVE ADDRESS
MAX11612/MAX11613
S
Bus Timing
At power-up, the MAX11612–MAX11617 bus timing is
set for fast-mode (F/S mode), which allows conversion
rates up to 22.2ksps. The MAX11612–MAX11617 must
operate in high-speed mode (HS mode) to achieve conversion rates up to 94.4ksps. Figure 1 shows the bus timing for the MAX11612–MAX11617’s 2-wire interface.
1
0
1
0
0
R/W
A
SDA
1
SCL
2
3
4
5
6
7
8
X
A
9
SEE ORDERING INFORMATION FOR SLAVE ADDRESS OPTIONS AND DETAILS.
Figure 7. MAX11612/MAX11613 Slave Address Byte
HS-MODE MASTER CODE
S
0
0
0
0
1
X
X
Sr
SDA
SCL
F/S MODE
HS MODE
Figure 8. F/S-Mode to HS-Mode Transfer
12
______________________________________________________________________________________
Low-Power, 4-/8-/12-Channel, I2C,
12-Bit ADCs in Ultra-Small Packages
configuration byte (Table 2). The master can write either
one or two bytes to the slave in any order (setup byte,
then configuration byte; configuration byte, then setup
byte; setup byte or configuration byte only; Figure 9). If
the slave receives a byte successfully, it issues an
acknowledge. The master ends the write cycle by issuing a STOP condition or a repeated START condition.
When operating in HS mode, a STOP condition returns
the bus into F/S mode (see the HS Mode section).
MASTER TO SLAVE
SLAVE TO MASTER
A. ONE-BYTE WRITE CYCLE
1
S
7
1 1
SLAVE ADDRESS
8
1
1
NUMBER OF BITS
SETUP OR
W A
A P or Sr
CONFIGURATION BYTE
MSB DETERMINES WHETHER
SETUP OR CONFIGURATION BYTE
B. TWO-BYTE WRITE CYCLE
1
7
1 1
8
1
S
SLAVE ADDRESS
W A
SETUP OR
CONFIGURATION BYTE
A
8
1
1
NUMBER OF BITS
SETUP OR
A P or Sr
CONFIGURATION BYTE
MSB DETERMINES WHETHER
SETUP OR CONFIGURATION BYTE
Figure 9. Write Cycle
Table 1. Setup Byte Format
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
REG
SEL2
SEL1
SEL0
CLK
BIP/UNI
RST
X
BIT
NAME
7
REG
Register bit. 1 = setup byte, 0 = configuration byte (Table 2).
6
SEL2
5
SEL1
4
SEL0
Three bits select the reference voltage and the state of AIN_/REF
(MAX11612/MAX11613/MAX11616/MAX11617) or REF (MAX11614/MAX11615) (Table 6).
Default to 000 at power-up.
3
CLK
1 = external clock, 0 = internal clock. Defaults to 0 at power-up.
2
BIP/UNI
1
RST
0
X
DESCRIPTION
1 = bipolar, 0 = unipolar. Defaults to 0 at power-up (see the Unipolar/Bipolar section).
1 = no action, 0 = resets the configuration register to default. Setup register remains unchanged.
Don’t-care bit. This bit can be set to 1 or 0.
______________________________________________________________________________________
13
MAX11612–MAX11617
Configuration/Setup Bytes (Write Cycle)
A write cycle begins with the bus master issuing a
START condition followed by seven address bits (Figure
7) and a write bit (R/W = 0). If the address byte is successfully received, the MAX11612–MAX11617 (slave)
issues an acknowledge. The master then writes to the
slave. The slave recognizes the received byte as the
set-up byte (Table 1) if the most significant bit (MSB) is
1. If the MSB is 0, the slave recognizes that byte as the
MAX11612–MAX11617
Low-Power, 4-/8-/12-Channel, I2C,
12-Bit ADCs in Ultra-Small Packages
Table 2. Configuration Byte Format
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
REG
SCAN1
SCAN0
CS3
CS2
CS1
CS0
SGL/DIF
BIT
NAME
7
REG
6
SCAN1
5
SCAN0
4
CS3
3
CS2
2
CS1
1
CS0
0
SGL/DIF
DESCRIPTION
Register bit. 1 = setup byte (see Table 1), 0 = configuration byte.
Scan select bits. Two bits select the scanning configuration (Table 5). Default to 00 at power-up.
Channel select bits. Four bits select which analog input channels are to be used for conversion
(Tables 3 and 4). Default to 0000 at power-up. For the MAX11612/MAX11613, CS3 and CS2 are
internally set to 0. For the MAX11614/MAX11615, CS3 is internally set to 0.
1 = single-ended, 0 = differential (Tables 3 and 4). Defaults to 1 at power-up. See the SingleEnded/Differential Input section.
Table 3. Channel Selection in Single-Ended Mode (SGL/DIF = 1)
CS31
CS21
CS1
CS0
AIN0
0
0
0
0
+
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
RESERVED
1
1
0
1
RESERVED
1
1
1
0
RESERVED
1
1
1
1
RESERVED
AIN1
AIN2
AIN32
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9 AIN10 AIN112 GND
-
+
+
+
+
+
+
+
+
+
+
+
-
1For the MAX11612/MAX11613, CS3 and CS2 are internally set to 0. For the MAX11614/MAX11615, CS3 is internally set to 0.
2When SEL1 = 1, a single-ended read of AIN3/REF (MAX11612/MAX11613) or AIN11/REF (MAX11616/MAX11617) is ignored; scan
stops at AIN2 or AIN10. This does not apply to the MAX11614/MAX11615 as each provides separate pins for AIN7 and REF.
14
______________________________________________________________________________________
Low-Power, 4-/8-/12-Channel, I2C,
12-Bit ADCs in Ultra-Small Packages
CS31
CS21
CS1
CS0
AIN0
0
0
0
0
+
-
0
0
0
1
-
+
0
0
1
0
+
-
0
0
1
1
-
+
0
1
0
0
1
0
1
0
AIN1
AIN2
AIN32
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
0
+
-
0
1
-
+
1
0
+
-
1
1
1
-
+
1
0
0
0
+
-
1
0
0
1
-
+
1
0
1
0
1
0
1
1
1
1
0
0
RESERVED
1
1
0
1
RESERVED
1
1
1
0
RESERVED
1
1
1
1
RESERVED
AIN10 AIN112
+
-
-
+
1For the MAX11612/MAX11613, CS3 and CS2 are internally set to 0. For the MAX11614/MAX11615, CS3 is internally set to 0.
2 When SEL1 = 1, a differential read between AIN2 and AIN3/REF (MAX11612/MAX11613) or AIN10 and AIN11/REF
(MAX11616/MAX11617) returns the difference between GND and AIN2 or AIN10, respectively. For example, a differential read of 1011
returns the negative difference between AIN10 and GND. This does not apply to the MAX11614/MAX11615 as each provides separate
pins for AIN7 and REF. In differential scanning, the address increments by 2 until the limit set by CS3–CS1 has been reached.
Data Byte (Read Cycle)
A read cycle must be initiated to obtain conversion
results. Read cycles begin with the bus master issuing
a START condition followed by seven address bits and
a read bit (R/W = 1). If the address byte is successfully
received, the MAX11612–MAX11617 (slave) issues an
acknowledge. The master then reads from the slave.
The result is transmitted in two bytes; first four bits of
the first byte are high, then MSB through LSB are consecutively clocked out. After the master has received
the byte(s), it can issue an acknowledge if it wants to
continue reading or a not-acknowledge if it no longer
wishes to read. If the MAX11612–MAX11617 receive a
not-acknowledge, they release SDA, allowing the master
to generate a STOP or a repeated START condition. See
the Clock Modes and Scan Mode sections for detailed
information on how data is obtained and converted.
Clock Modes
The clock mode determines the conversion clock and
the data acquisition and conversion time. The clock
mode also affects the scan mode. The state of the setup byte’s CLK bit determines the clock mode (Table 1).
At power-up, the MAX11612–MAX11617 are defaulted
to internal clock mode (CLK = 0).
Internal Clock
When configured for internal clock mode (CLK = 0), the
MAX11612–MAX11617 use their internal oscillator as the
conversion clock. In internal clock mode, the MAX11612–
MAX11617 begin tracking the analog input after a valid
address on the eighth rising edge of the clock. On the
falling edge of the ninth clock, the analog signal is acquired
and the conversion begins. While converting the analog
input signal, the MAX11612–MAX11617 holds SCL low
(clock stretching). After the conversion completes, the
results are stored in internal memory. If the scan mode is set
for multiple conversions, they all happen in succession with
each additional result stored in memory. The MAX11612/
MAX11613 contain four 12-bit blocks of memory, the
MAX11614/MAX11615 contain eight 12-bit blocks of memory, and the MAX11616/MAX11617 contain twelve 12-bit
blocks of memory. Once all conversions are complete, the
MAX11612–MAX11617 release SCL, allowing it to be pulled
high. The master can now clock the results out of the memory in the same order the scan conversion has been done
at a clock rate of up to 1.7MHz. SCL is stretched for a maximum of 8.3µs per channel (see Figure 10).
The device memory contains all of the conversion
results when the MAX11612–MAX11617 release SCL.
______________________________________________________________________________________
15
MAX11612–MAX11617
Table 4. Channel Selection in Differential Mode (SGL/DIF = 0)
MAX11612–MAX11617
Low-Power, 4-/8-/12-Channel, I2C,
12-Bit ADCs in Ultra-Small Packages
MASTER TO SLAVE
SLAVE TO MASTER
A. SINGLE CONVERSION WITH INTERNAL CLOCK
1
7
1 1
S
SLAVE ADDRESS
R A
8
CLOCK STRETCH
8
A
RESULT 4 MSBs
RESULT 8 LSBs
1
1
NUMBER OF BITS
A P or Sr
tACQ
tCONV
B. SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
1
7
1 1
S
SLAVE ADDRESS
R A
8
CLOCK STRETCH
tACQ1
CLOCK STRETCH
tACQ2
tCONV2
tCONV1
1
8
1
8
RESULT 1 ( 4MSBs) A RESULT 1 (8 LSBs) A
1
8
1
1
NUMBER OF BITS
RESULT N (4MSBs) A RESULT N (8LSBs) A P or Sr
tACQN
tCONVN
Figure 10. Internal Clock Mode Read Cycles
The converted results are read back in a first-in-first-out
(FIFO) sequence. If AIN_/REF is set to be a reference
input or output (SEL1 = 1, Table 6), AIN_/REF is excluded from a multichannel scan. This does not apply to the
MAX11614/MAX11615 as each provides separate pins
for AIN7 and REF. The memory contents can be read
continuously. If reading continues past the result stored
in memory, the pointer wraps around and point to the
first result. Note that only the current conversion results
is read from memory. The device must be addressed
with a read command to obtain new conversion results.
The internal clock mode’s clock stretching quiets the
SCL bus signal reducing the system noise during
conversion. Using the internal clock also frees the bus
master (typically a microcontroller) from the burden of
running the conversion clock, allowing it to perform
other tasks that do not need to use the bus.
External Clock
When configured for external clock mode (CLK = 1),
the MAX11612–MAX11617 use the SCL as the conversion clock. In external clock mode, the MAX11612–
MAX11617 begin tracking the analog input on the ninth
rising clock edge of a valid slave address byte. Two
SCL clock cycles later, the analog signal is acquired
and the conversion begins. Unlike internal clock mode,
MASTER TO SLAVE
SLAVE TO MASTER
A. SINGLE CONVERSION WITH EXTERNAL CLOCK
1
7
1 1
8
1
8
1
1
S
SLAVE ADDRESS
R A
RESULT (4 MSBs)
A
RESULT (8 LSBs)
A
P OR Sr
NUMBER OF BITS
tACQ
tCONV
B. SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
1
S
7
1 1
SLAVE ADDRESS
R A
8
1
RESULT 1 (4 MSBs)
A
8
1
8
1
RESULT 2 (8 LSBs)
A
RESULT N (4 MSBs)
A
tACQ2
tACQN
tACQ1
tCONV1
8
RESULT N (8 LSBs)
1
1
A P OR Sr
tCONVN
Figure 11. External Clock Mode Read Cycle
16
______________________________________________________________________________________
NUMBER OF BITS
Low-Power, 4-/8-/12-Channel, I2C,
12-Bit ADCs in Ultra-Small Packages
SCAN1
SCAN0
SCANNING CONFIGURATION
0
0
Scans up from AIN0 to the input selected by CS3–CS0. When CS3–CS0 exceeds 1011, the scanning
stops at AIN11. When AIN_/REF is set to be a REF input/output, scanning stops at AIN2 or AIN10.
0
1
*Converts the input selected by CS3–CS0 eight times (see Tables 3 and 4).
MAX11612/MAX11613: Scans upper half of channels.
Scans up from AIN2 to the input selected by CS1 and CS0. When CS1 and CS0 are set for AIN0, AIN1,
and AIN2, the only scan that takes place is AIN2 (MAX11612/MAX11613). When AIN/REF is set to be a
REF input/output, scanning stops at AIN2.
1
0
MAX11614/MAX11615: Scans upper quartile of channels.
Scans up from AIN6 to the input selected by CS3–CS0. When CS3–CS0 is set for AIN0–AIN6, the only
scan that takes place is AIN6 (MAX11614/MAX11615).
MAX11616/MAX11617: Scans upper half of channels.
Scans up from AIN6 to the input selected by CS3–CS0. When CS3–CS0 is set for AIN0–AIN6, the only
scan that takes place is AIN6 (MAX11616/MAX11617). When AIN/REF is set to be a REF input/output,
scanning stops at selected channel or AIN10.
1
1
*Converts channel selected by CS3–CS0.
*When operating in external clock mode, there is no difference between SCAN[1:0] = 01 and SCAN[1:0] = 11, and converting occurs
perpetually until not-acknowledge occurs.
converted data is available immediately after the first
four empty high bits. The device continuously converts
input channels dictated by the scan mode until given a
not acknowledge. There is no need to readdress the
device with a read command to obtain new conversion
results (see Figure 11).
The conversion must complete in 1ms, or droop on the
track-and-hold capacitor degrades conversion results.
Use internal clock mode if the SCL clock period
exceeds 60µs.
The MAX11612–MAX11617 must operate in external
clock mode for conversion rates from 40ksps to
94.4ksps. Below 40ksps, internal clock mode is recommended due to much smaller power consumption.
Scan Mode
SCAN0 and SCAN1 of the configuration byte set the
scan mode configuration. Table 5 shows the scanning
configurations. If AIN_/REF is set to be a reference input
or output (SEL1 = 1, Table 6), AIN_/REF is excluded from
a multichannel scan. The scanned results are written to
memory in the same order as the conversion. Read the
results from memory in the order they were converted.
Each result needs a 2-byte transmission; the first byte
begins with four empty bits, during which SDA is left
high. Each byte has to be acknowledged by the master
or the memory transmission is terminated. It is not possible to read the memory independently of conversion.
Applications Information
Power-On Reset
The configuration and setup registers (Tables 1 and 2)
default to a single-ended, unipolar, single-channel conversion on AIN0 using the internal clock with VDD as the
reference and AIN_/REF configured as an analog input.
The memory contents are unknown after power-up.
Automatic Shutdown
Automatic shutdown occurs between conversions when
the MAX11612–MAX11617 are idle. All analog circuits
participate in automatic shutdown except the internal
reference due to its prohibitively long wake-up time.
When operating in external clock mode, a STOP, notacknowledge, or repeated START condition must be
issued to place the devices in idle mode and benefit
from automatic shutdown. A STOP condition is not necessary in internal clock mode to benefit from automatic
shutdown because power-down occurs once all conversion results are written to memory (Figure 10). When
using an external reference or VDD as a reference, all
analog circuitry is inactive in shutdown and supply current is less than 0.5µA. The digital conversion results
obtained in internal clock mode are maintained in memory during shutdown and are available for access through
the serial interface at any time prior to a STOP or a
repeated START condition.
______________________________________________________________________________________
17
MAX11612–MAX11617
Table 5. Scanning Configuration
MAX11612–MAX11617
Low-Power, 4-/8-/12-Channel, I2C,
12-Bit ADCs in Ultra-Small Packages
Table 6. Reference Voltage, AIN_/REF, and REF Format
0
0
X
VDD
AIN_/REF
(MAX11612/
MAX11613/
MAX11616/
MAX11617)
Analog input
Not connected
Always off
0
1
X
External reference
Reference input
Reference input
Always off
1
0
0
Internal reference
Analog input
Not connected
Always off
1
0
1
Internal reference
Analog input
Not connected
Always on
1
1
0
Internal reference
Reference output
Reference output
Always off
1
1
1
Internal reference
Reference output
Reference output
Always on
SEL2
SEL1
SEL0
REFERENCE
VOLTAGE
REF
(MAX11614/
MAX11615)
INTERNAL
REFERENCE
STATE
X = Don’t care.
When idle, the MAX11612–MAX11617 continuously wait
for a START condition followed by their slave address
(see the Slave Address section). Upon reading a valid
address byte, the MAX11612–MAX11617 power up.
The internal reference requires 10ms to wake up, so
when using the internal reference it should be powered
up 10ms prior to conversion or powered continuously.
Wake-up is invisible when using an external reference
or VDD as the reference.
Automatic shutdown results in dramatic power savings,
particularly at slow conversion rates and with internal
clock. For example, at a conversion rate of 10ksps, the
average supply current for the MAX11613 is 60µA (typ)
and drops to 6µA (typ) at 1ksps. At 0.1ksps the average
supply current is just 1µA, or a minuscule 3µW of power
consumption. See Average Supply Current vs. Conversion
Rate in the Typical Operating Characteristics section).
powered up, the reference always remains on until reconfigured. The internal reference requires 10ms to wake up
and is accessed using SEL0 (Table 6). When in shutdown,
the internal reference output is in a high-impedance state.
The reference should not be used to supply current for
external circuitry. The internal reference does not require an
external bypass capacitor and works best when left unconnected (SEL1 = 0).
External Reference
The external reference can range from 1V to VDD. For
maximum conversion accuracy, the reference must be
able to deliver up to 40µA and have an output impedance of 500kΩ or less. If the reference has a higher output impedance or is noisy, bypass it to GND as close to
AIN_/REF as possible with a 0.1µF capacitor.
OUTPUT CODE
Reference Voltage
SEL[2:0] of the setup byte (Table 1) control the reference
and the AIN_/REF configuration (Table 6). When AIN_/REF
is configured to be a reference input or reference output
(SEL1 = 1), differential conversions on AIN_/REF appear
as if AIN_/REF is connected to GND (see note 2 of Table
4). Single-ended conversion in scan mode AIN_/REF is
ignored by the internal limiter, which sets the highest available channel at AIN2 or AIN10.
Internal Reference
The internal reference is 4.096V for the MAX11612/
MAX11614/MAX11616 and 2.048V for the MAX11613/
MAX11615/MAX11617. SEL1 of the setup byte controls
whether AIN_/REF is used for an analog input or a reference (Table 6). When AIN_/REF is configured to be an
internal reference output (SEL[2:1] = 11), decouple
AIN_/REF to GND with a 0.1µF capacitor and a 2kΩ
series resistor (see the Typical Operating Circuit). Once
18
MAX11612–
MAX11617
FULL-SCALE
TRANSITION
11 . . . 111
11 . . . 110
11 . . . 101
FS = VREF
ZS = GND
V
1 LSB = REF
4096
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
0
1
2
3
INPUT VOLTAGE (LSB)
FS
FS - 3/2 LSB
Figure 12. Unipolar Transfer Function
______________________________________________________________________________________
Low-Power, 4-/8-/12-Channel, I2C,
MAX11612–MAX11617
OUTPUT CODE
011 . . . 111
FS = VREF
2
011 . . . 110
ZS = 0
000 . . . 010
000 . . . 001
MAX11612–
MAX11617
SUPPLIES
3V OR 5V
-VREF
2
V
1 LSB = REF
4096
VLOGIC = 3V/5V
GND
-FS =
000 . . . 000
4.7µF
R* = 5Ω
111 . . . 111
111 . . . 110
0.1µF
111 . . . 101
VDD
GND
100 . . . 001
100 . . . 000
MAX11612–
MAX11617
0
- FS
*VCOM ≤ VREF/2
3V/5V
DGND
DIGITAL
CIRCUITRY
+FS - 1 LSB
INPUT VOLTAGE (LSB)
*VIN = (AIN+) - (AIN-)
Figure 13. Bipolar Transfer Function
Transfer Functions
Output data coding for the MAX11612–MAX11617 is
binary in unipolar mode and two’s complement in bipolar mode with 1 LSB = (VREF/2N) where N is the number
of bits (12). Code transitions occur halfway between
successive-integer LSB values. Figures 12 and 13
show the input/output (I/O) transfer functions for unipolar and bipolar operations, respectively.
Layout, Grounding, and Bypassing
Only use PC boards. Wire-wrap configurations are not
recommended since the layout should ensure proper
separation of analog and digital traces. Do not run analog and digital lines parallel to each other, and do not
layout digital signal paths underneath the ADC package. Use separate analog and digital PCB ground sections with only one star point (Figure 14) connecting the
two ground systems (analog and digital). For lowest
noise operation, ensure the ground return to the star
ground’s power supply is low impedance and as short
as possible. Route digital signals far away from sensitive analog and reference inputs.
High-frequency noise in the power supply (VDD) could
influence the proper operation of the ADC’s fast comparator. Bypass VDD to the star ground with a network of
two parallel capacitors, 0.1µF and 4.7µF, located as
close as possible to the MAX11612–MAX11617 power-
*OPTIONAL
Figure 14. Power-Supply Grounding Connection
supply pin. Minimize capacitor lead length for best supply noise rejection, and add an attenuation resistor (5Ω)
in series with the power supply if it is extremely noisy.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on
an actual transfer function from a straight line. This straight
line can be either a best straight-line fit or a line drawn
between the endpoints of the transfer function, once offset
and gain errors have been nullified. The MAX11612–
MAX11617’s INL is measured using the endpoint.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples.
Aperture Delay
Aperture delay (tAD) is the time between the falling
edge of the sampling clock and the instant when an
actual sample is taken.
______________________________________________________________________________________
19
MAX11612–MAX11617
Low-Power, 4-/8-/12-Channel, I2C,
12-Bit ADCs in Ultra-Small Packages
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the fullscale analog input (RMS value) to the RMS quantization
error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only
and results directly from the ADC’s resolution (N Bits):
SNRMAX[dB] = 6.02dB N + 1.76dB
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five harmonics, and the DC offset.
⎞
⎛ ⎛ 2
V + V32 + V4 2 + V52 ⎞ ⎟
THD = 20 × log ⎜ ⎜ 2
⎟
⎜ ⎝
V1
⎠ ⎟⎠
⎝
where V1 is the fundamental amplitude, and V2 through
V5 are the amplitudes of the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest distortion component.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals.
Chip Information
PROCESS: BiCMOS
SignalRMS
⎡
⎤
SINAD(dB) = 20 × log ⎢
⎥
NoiseRMS
+
THDRMS
⎣
⎦
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the
ADC’s full-scale range, calculate the ENOB as follows:
ENOB = (SINAD - 1.76)/6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the input signal’s first five harmonics to the fundamental itself. This is expressed as:
20
Selector Guide
PART
INTERNAL
SUPPLY
INPUT
REFERENCE VOLTAGE
CHANNELS
(V)
(V)
INL
(LSB)
MAX11612
4
4.096
4.5 to 5.5
±1
MAX11613
4
2.048
2.7 to 3.6
±1
MAX11614
8
4.096
4.5 to 5.5
±1
MAX11615
8
2.048
2.7 to 3.6
±1
MAX11616
12
4.096
4.5 to 5.5
±1
MAX11617
12
2.048
2.7 to 3.6
±1
______________________________________________________________________________________
Low-Power, 4-/8-/12-Channel, I2C,
12-Bit ADCs in Ultra-Small Packages
3.3V or 5V
TOP VIEW
+
AIN0 1
AIN1 2
MAX11612
MAX11613
3
AIN2
AIN3/REF 4
8
VDD
7
GND
6
SDA
5
SCL
0.1µF
VDD
ANALOG
INPUTS
AIN0
AIN1
RS*
MAX11612–
MAX11617
SDA
SCL
RS *
RC NETWORK* 2kΩ
µMAX
AIN3**/REF
CREF
0.1µF
GND
5V
+
(REF) AIN11/REF 1
16 VDD
(N.C.) AIN10 2
15 GND
(N.C.) AIN9 3
14 SDA
(N.C.) AIN8 4
AIN0 5
MAX11614–
MAX11617
5V
RP
µC
13 SCL
11 AIN6
AIN2 7
10 AIN5
AIN3 8
9
SDA
SCL
12 AIN7
AIN1 6
RP
*OPTIONAL
**AIN11/REF (MAX11616/MAX11617)
AIN4
QSOP
( ) INDICATES PINS ON THE MAX11614/MAX11615.
TOP VIEW
(BUMPS ON BOTTOM)
1
Package Information
MAX11613
2
3
4
+
A
AIN0
AIN1
AIN2
AIN3/
REF
B
GND
GND
GND
GND
C
VDD
GND
SDA
SCL
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
8 µMAX
U8CN+1
21-0036
90-0092
12 WLP
W121C2+1
21-0009
Refer to Application
Note 1891
16 QSOP
E16+1
21-0055
90-0167
WLP
______________________________________________________________________________________
21
MAX11612–MAX11617
Typical Operating Circuit
Pin Configurations
MAX11612–MAX11617
Low-Power, 4-/8-/12-Channel, I2C,
12-Bit ADCs in Ultra-Small Packages
Revision History
PAGES
CHANGED
REVISION
NUMBER
REVISION
DATE
0
4/09
Introduction of the MAX11612/MAX11613
—
1
7/09
Introduction of the MAX11614–MAX11617
1
2
3/10
Changed Absolute Maximum Ratings and timing diagram
2/11
Added WLP to Ordering Information, Absolute Maximum Ratings, Electrical
Characteristics, Pin Description, and Package Information
3
DESCRIPTION
2, 12
1–5, 8, 21
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products
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