19-1640; Rev 0; 1/00 KIT ATION EVALU E L B AVAILA 400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface The MAX1090/MAX1092 low-power, 10-bit analog-todigital converters (ADCs) feature a successive-approximation ADC, automatic power-down, fast wake-up (2µs), on-chip clock, +2.5V internal reference, and high-speed, byte-wide parallel interface. The devices operate with a single +5V analog supply and feature a VLOGIC pin that allows them to interface directly with a +2.7V to +5.5V digital supply. Power consumption is only 10mW (VDD = VLOGIC) at a 400ksps max sampling rate. Two software-selectable power-down modes enable the MAX1090/MAX1092 to be shut down between conversions; accessing the parallel interface returns them to normal operation. Powering down between conversions can cut supply current to under 10µA at reduced sampling rates. Both devices offer software-configurable analog inputs for unipolar/bipolar and single-ended/pseudo-differential operation. In single-ended mode, the MAX1090 has eight input channels and the MAX1092 has four input channels (four and two input channels, respectively, when in pseudo-differential mode). Excellent dynamic performance and low power combined with ease of use and small package size make these converters ideal for battery-powered and dataacquisition applications or for other circuits with demanding power consumption and space requirements. The MAX1090 is available in a 28-pin QSOP package, while the MAX1092 comes in a 24-pin QSOP. For pincompatible +3V, 10-bit versions, refer to the MAX1091/ MAX1093 data sheet. Applications Features ♦ 10-Bit Resolution, ±0.5LSB Linearity ♦ +5V Single-Supply Operation ♦ User-Adjustable Logic Level (+2.7V to +5.5V) ♦ Internal +2.5V Reference ♦ Software-Configurable Analog Input Multiplexer 8-Channel Single-Ended/ 4-Channel Pseudo-Differential (MAX1090) 4-Channel Single-Ended/ 2-Channel Pseudo-Differential (MAX1092) ♦ Software-Configurable Unipolar/Bipolar Analog Inputs ♦ Low Current: 2.2mA (400ksps) 1.0mA (100ksps) 400µA (10ksps) 2µA (shutdown) ♦ Internal 6MHz Full-Power Bandwidth Track/Hold ♦ Byte-Wide Parallel (8+2) Interface ♦ Small Footprint: 28-Pin QSOP (MAX1090) 24-Pin QSOP (MAX1092) Pin Configurations TOP VIEW HBEN 1 D7 2 23 VDD D6 3 22 REF 21 REFADJ Industrial Control Systems Energy Management Data Logging Patient Monitoring D5 4 Data-Acquisition Systems Touchscreens D3 6 Ordering Information PART MAX1090ACEI TEMP. RANGE PIN-PACKAGE INL (LSB) 0°C to +70°C 28 QSOP ±0.5 MAX1090BCEI 0°C to +70°C 28 QSOP ±1 MAX1090AEEI -40°C to +85°C 28 QSOP ±0.5 MAX1090BEEI -40°C to +85°C 28 QSOP ±1 Ordering Information continued at end of data sheet. 24 VLOGIC D4 5 20 GND MAX1092 19 COM D2 7 18 CH0 D1/D9 8 17 CH1 D0/D8 9 16 CH2 INT 10 15 CH3 RD 11 14 CS WR 12 13 CLK QSOP Pin Configurations continued at end of data sheet. Typical Operating Circuits appear at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1 For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX1090/MAX1092 General Description MAX1090/MAX1092 400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V VLOGIC to GND.........................................................-0.3V to +6V CH0–CH7, COM to GND ............................-0.3V to (VDD + 0.3V) REF, REFADJ to GND.................................-0.3V to (VDD + 0.3V) Digital Inputs to GND ...............................................-0.3V to +6V Digital Outputs (D0–D9, INT) to GND ........................................... -0.3V to (VLOGIC + 0.3V) Continuous Power Dissipation (TA = +70°C) 24-Pin QSOP (derate 9.5mW/°C above +70°C).........762mW 28-Pin QSOP (derate 8.00mW/°C above +70°C).......667mW Operating Temperature Ranges MAX1090_C_ _/MAX1092_C_ _ ....................... 0°C to +70°C MAX1090_E_ _/MAX1092_E_ _ .....................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = VLOGIC = +5V ±10%, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 7.6MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY (Note 1) Resolution 10 RES Relative Accuracy (Note 2) INL Differential Nonlinearity DNL Bits MAX109_A ±0.5 MAX109_B ±1 No missing codes over temperature ±1 LSB ±2 LSB Offset Error ±2 Gain Error (Note 3) LSB LSB Gain Temperature Coefficient ±2.0 ppm/°C Channel-to-Channel Offset Matching ±0.1 LSB DYNAMIC SPECIFICATIONS (fIN(sine wave) = 50kHz, VIN = 2.5Vp-p, 400ksps, external fCLK = 7.6MHz, bipolar input mode) Signal-to-Noise Plus Distortion SINAD 60 dB Total Harmonic Distortion (including 5th-order harmonic) THD -72 dB Spurious-Free Dynamic Range SFDR 72 dB 76 dB Intermodulation Distortion IMD fIN1 = 49kHz, fIN2 = 52kHz Channel-to-Channel Crosstalk fIN = 175kHz, VIN = 2.5Vp-p (Note 4) -78 dB Full-Linear Bandwidth SINAD > 56dB 350 kHz Full-Power Bandwidth -3dB rolloff 6 MHz CONVERSION RATE Conversion Time (Note 5) tCONV T/H Acquisition Time tACQ Aperture Delay Aperture Jitter External Clock Frequency Duty Cycle 2 fCLK External clock mode 2.1 External acquisition/internal clock mode 2.5 3.0 Internal acquisition/internal clock mode 3.2 3.6 3.5 4 400 External acquisition or external clock mode 25 External acquisition or external clock mode <50 Internal acquisition/internal clock mode <200 µs ns ns ps 0.1 7.6 MHz 30 70 % _______________________________________________________________________________________ 400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface (VDD = VLOGIC = +5V ±10%, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 7.6MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ANALOG INPUTS Analog Input Voltage Range, Single Ended and Differential (Note 6) Unipolar, VCOM = 0 0 VREF -VREF/2 +VREF/2 VIN V Bipolar, VCOM = VREF / 2 Multiplexer Leakage Current ±0.01 On/off-leakage current, VIN = 0 or VDD Input Capacitance ±1 12 CIN µA pF INTERNAL REFERENCE 2.49 REF Output Voltage REF Short-Circuit Current REF Temperature Coefficient TCREF TA = 0°C to +70°C REFADJ Input Range For small adjustments REFADJ High Threshold To power down the internal reference Load Regulation (Note 7) 0 to 0.5mA output load 2.5 V mA ±20 ppm/°C ±100 mV VDD - 1.0 V 0.2 0.01 0.5 mV/mA 1 µF 4.7 10 µF 1.0 VDD + 50mV V Capacitive Bypass at REFADJ Capacitive Bypass at REF 2.51 15 EXTERNAL REFERENCE AT REF REF Input Voltage Range VREF Shutdown REF Input Current IREF 200 VREF = 2.5V, fSAMPLE = 400ksps 300 2 Shutdown mode µA DIGITAL INPUTS AND OUTPUTS Input Voltage High VIH Input Voltage Low VIL Input Hysteresis VLOGIC = 4.5V 4.0 VLOGIC = 2.7V 2.0 IIN 200 VIN = 0 or VDD CIN Output Voltage Low VOL ISINK = 1.6mA Output Voltage High VOH ISOURCE = 1mA Three-State Output Capacitance ±0.1 ±1 VLOGIC - 0.5 CS = VDD ±0.1 COUT CS = VDD 15 µA pF 0.4 ILEAKAGE V mV 15 Input Capacitance Three-State Leakage Current 0.8 VLOGIC = 4.5V or 2.7V VHYS Input Leakage Current V V V V ±1 µA pF _______________________________________________________________________________________ 3 MAX1090/MAX1092 ELECTRICAL CHARACTERISTICS (continued) MAX1090/MAX1092 400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface ELECTRICAL CHARACTERISTICS (continued) (VDD = VLOGIC = +5V ±10%, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 7.6MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER REQUIREMENTS Analog Supply Voltage VDD 4.5 5.5 V Digital Supply Voltage VLOGIC 2.7 VDD + 0.3 V Operating mode, fSAMPLE = 400ksps Positive Supply Current IDD Standby mode Operating mode, Internal reference 2.6 2.9 External reference 2.2 2.5 Internal reference 1.0 1.2 External reference 0.5 0.8 2 Shutdown mode VLOGIC Current Power-Supply Rejection ILOGIC PSR CL = 20pF 10 200 fSAMPLE = 400ksps Nonconverting VDD = 5V ±10%, full-scale input 2 10 ±0.3 ±0.7 mA µA µA mV TIMING CHARACTERISTICS (VDD = VLOGIC = +5V ±10%, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 7.6MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CLK Period tCP 132 ns CLK Pulse Width High tCH 40 ns CLK Pulse Width Low tCL 40 ns Data Valid to WR Rise Time tDS 40 ns WR Rise to Data Valid Hold Time tDH 0 ns WR to CLK Fall Setup Time tCWS 40 ns CLK Fall to WR Hold Time tCWH 40 ns CS to CLK or WR Setup Time tCSWS 60 ns CLK or WR to CS Hold Time tCSWH 0 ns CS Pulse Width tCS 100 ns WR Pulse Width (Note 8) tWR 60 ns 4 _______________________________________________________________________________________ 400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface (VDD = VLOGIC = +5V ±10%, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 7.6MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL MAX UNITS tTC CLOAD = 20pF, Figure 1 10 60 ns RD Rise to Output Disable tTR CLOAD = 20pF, Figure 1 10 40 ns RD Fall to Output Data Valid tDO CLOAD = 20pF, Figure 1 10 50 ns HBEN Rise to Output Data Valid tDO1 CLOAD = 20pF, Figure 1 10 50 ns HBEN Fall to Output Data Valid tDO1 CLOAD = 20pF, Figure 1 10 80 ns RD Fall to INT High Delay tINT1 CLOAD = 20pF, Figure 1 50 ns CS Fall to Output Data Valid tDO2 CLOAD = 20pF, Figure 1 100 ns CS Rise to Output Disable CONDITIONS MIN TYP Note 1: Tested at VDD = +5V, COM = GND, unipolar single-ended input mode. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have been removed. Note 3: Offset nulled. Note 4: On channel is grounded; sine wave applied to off channels. Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle. Note 6: Input voltage range referenced to negative input. The absolute range for the analog inputs is from GND to VDD. Note 7: External load should not change during conversion for specified accuracy. Note 8: When bit 5 is set low for internal acquisition, WR must not return low until after the first falling clock edge of the conversion. VLOGIC 3k DOUT 3k CLOAD 20pF a) HIGH-Z TO VOH AND VOL TO VOH DOUT CLOAD 20pF b) HIGH-Z TO VOL AND VOH TO VOL Figure 1. Load Circuits for Enable/Disable Times _______________________________________________________________________________________ 5 MAX1090/MAX1092 TIMING CHARACTERISTICS (continued) Typical Operating Characteristics (VDD = VLOGIC = +5V, VREF = +2.500V, fCLK = 7.6MHz, CL = 20pF, TA = +25°C, unless otherwise noted.) DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE 0.20 0.15 0.10 0.05 0.05 DNL (LSB) 0.10 0 -0.05 -0.10 0 -0.05 -0.15 -0.20 -0.20 -0.25 100 WITH EXTERNAL REFERENCE 10 -0.25 400 600 800 1000 1200 1 0 200 400 OUTPUT CODE 600 800 1000 1200 0.1 1 10 OUTPUT CODE SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. TEMPERATURE MAX1090/92 toc04 2.3 2.1 RL = ∞ CODE = 1010100000 2.2 IDD (mA) 10k 100k 1M STANDBY CURRENT vs. SUPPLY VOLTAGE 2.1 2.0 1k 990 980 STANDBY IDD (µA) RL = ∞ CODE = 1010100000 100 fSAMPLE (Hz) 2.0 1.9 MAX1090/92 toc06 200 MAX1090/92 toc05 0 IDD (mA) WITH INTERNAL REFERENCE -0.10 -0.15 2.2 1k IDD (µA) 0.15 10k MAX1090/92 toc02 0.20 INL (LSB) 0.25 MAX1090 TOC01 0.25 SUPPLY CURRENT vs. SAMPLE FREQUENCY MAX1090/92 toc03 INTEGRAL NONLINEARITY vs. OUTPUT CODE 970 960 950 1.9 1.8 940 1.7 4.75 5.00 5.25 5.50 930 -40 VDD (V) STANDBY CURRENT vs. TEMPERATURE 970 960 950 35 60 85 4.50 4.75 5.00 5.25 5.50 TEMPERATURE (°C) VDD (V) POWER-DOWN CURRENT vs. SUPPLY VOLTAGE POWER-DOWN CURRENT vs. TEMPERATURE MAX1090/92 toc08 980 10 3.0 POWER-DOWN IDD (µA) MAX1090/92 toc07 990 -15 2.5 2.0 1.5 2.2 MAX1090/92 toc09 4.50 POWER-DOWN IDD (µA) 1.8 STANDBY IDD (µA) MAX1090/MAX1092 400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface 2.1 2.0 1.9 940 1.0 930 -40 -15 10 35 TEMPERATURE (°C) 6 60 85 1.8 4.50 4.75 5.00 VDD (V) 5.25 5.50 -40 -15 10 35 TEMPERATURE (°C) _______________________________________________________________________________________ 60 85 400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface 2.51 2.50 2.49 2.49 5.00 5.25 5.50 -1.0 -40 -15 VDD (V) 60 4.50 85 0 -0.5 0 0.375 0.250 -0.50 10 35 60 85 0 4.50 4.75 5.00 5.25 TEMPERATURE (°C) VDD (V) LOGIC SUPPLY CURRENT vs. SUPPLY VOLTAGE LOGIC SUPPLY CURRENT vs. TEMPERATURE -15 10 35 60 85 FFT PLOT 20 150 100 VDD = 5V fIN = 50kHz fSAMPLE = 400ksps 0 -20 AMPLITUDE (dB) 150 -40 MAX1090/92 toc 17 200 ILOGIC (µA) 200 5.50 TEMPERATURE (°C) 250 MAX1090/92 toc16 250 5.50 0.125 -0.25 -1.0 5.25 GAIN ERROR vs. TEMPERATURE GAIN ERROR (LSB) GAIN ERROR (LSB) 0.25 -15 5.00 0.500 MAX1090/92 toc14 MAX1090 TOC13 0.50 0.5 -40 4.75 VDD (V) GAIN ERROR vs. SUPPLY VOLTAGE 1.0 OFFSET ERROR (LSB) 35 TEMPERATURE (°C) OFFSET ERROR vs. TEMPERATURE ILOGIC (µA) 10 MAX1090/92 toc15 4.75 0 -0.5 2.48 4.50 0.5 MAX1291/93 toc18 2.50 2.48 OFFSET ERROR (LSB) 2.52 VREF (V) 2.51 1.0 MAX1090/92 toc 11 2.52 VREF (V) 2.53 MAX1090/92 toc10 2.53 OFFSET ERROR vs. SUPPLY VOLTAGE INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE MAX1090 TOC12 INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE -40 -60 -80 -100 100 50 -120 50 -140 0 4.50 4.75 5.00 VDD (V) 5.25 5.50 -40 -15 10 35 TEMPERATURE (°C) 60 85 0 200 400 600 800 1000 1200 FREQUENCY (kHz) _______________________________________________________________________________________ 7 MAX1090/MAX1092 Typical Operating Characteristics (continued) (VDD = VLOGIC = +5V, VREF = +2.500V, fCLK = 7.6MHz, CL = 20pF, TA = +25°C, unless otherwise noted.) MAX1090/MAX1092 400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface Pin Description PIN NAME FUNCTION MAX1090 MAX1092 1 1 HBEN 2 2 D7 Three-State Digital I/O Line (D7) 3 3 D6 Three-State Digital I/O Line (D6) 4 4 D5 Three-State Digital I/O Line (D5) 5 5 D4 Three-State Digital I/O Line (D4) 6 6 D3 Three-State Digital I/O Line (D3) 7 7 D2 Three-State Digital I/O Line (D2) 8 8 D1/D9 Three-State Digital I/O Line (D1, HBEN = 0; D9, HBEN = 1) Three-State Digital I/O Line (D0, HBEN = 0; D8, HBEN = 1) 8 High Byte Enable. Used to multiplex the 10-bit conversion result. 1: 2 MSBs are multiplexed on the data bus. 0: 8 LSBs are available on the data bus. 9 9 D0/D8 10 10 INT INT goes low when the conversion is complete and the output data is ready. 11 11 RD Active-Low Read Select. If CS is low, a falling edge on RD will enable the read operation on the data bus. 12 12 WR Active-Low Write Select. When CS is low in internal acquisition mode, a rising edge on WR latches in configuration data and starts an acquisition plus a conversion cycle. When CS is low in external acquisition mode, the first rising edge on WR ends acquisition and starts a conversion. 13 13 CLK Clock Input. In external clock mode, drive CLK with a TTL/CMOS-compatible clock. In internal clock mode, connect this pin to either VDD or GND. 14 14 CS 15 — CH7 Analog Input Channel 7 16 — CH6 Analog Input Channel 6 17 — CH5 Analog Input Channel 5 18 — CH4 Analog Input Channel 4 19 15 CH3 Analog Input Channel 3 20 16 CH2 Analog Input Channel 2 21 17 CH1 Analog Input Channel 1 22 18 CH0 Analog Input Channel 0 23 19 COM Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode and must be stable to ±0.5LSB during conversion. 24 20 GND Analog and Digital Ground 25 21 REFADJ Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to GND with a 0.01µF capacitor. When using an external reference, connect REFADJ to VDD to disable the internal bandgap reference. 26 22 REF Bandgap Reference Buffer Output/External Reference Input. Add a 4.7µF capacitor to GND when using the internal reference. 27 23 VDD Analog +5V Power Supply. Bypass with a 0.1µF capacitor to GND. 28 24 VLOGIC Active-Low Chip Select. When CS is high, digital outputs (INT, D7–D0) are high impedance. Digital Power Supply. VLOGIC powers the digital outputs of the data converter and can range from +2.7V to VDD + 300mV. _______________________________________________________________________________________ 400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface REFADJ AV = 2.05 (CH7) 17k (CH6) (CH5) (CH4) CH3 CH2 ANALOG INPUT MULTIPLEXER CHARGE REDISTRIBUTION 10-BIT DAC RD INT COMP 10 COM CS WR 1.22V REFERENCE T/H CH1 CH0 CLK MAX1090/MAX1092 REF SUCCESSIVEAPPROXIMATION REGISTER CLOCK CONTROL LOGIC AND LATCHES 2 8 2 8 MUX 8 8 THREE-STATE, BIDIRECTIONAL I/O INTERFACE MAX1090 MAX1092 HBEN VDD VLOGIC GND D0–D7 8-BIT DATA BUS ( ) ARE FOR MAX1090 ONLY. Figure 2. Simplified Functional Diagram of 8-/4-Channel MAX1090/MAX1092 Detailed Description Converter Operation The MAX1090/MAX1092 ADCs use a successiveapproximation (SAR) conversion technique and an input track-and-hold (T/H) stage to convert an analog input signal to a 10-bit digital output. Their parallel 8+2 output format provides an easy interface to standard microprocessors (µPs). Figure 2 shows the simplified internal architecture of the MAX1090/MAX1092. Single-Ended and Pseudo-Differential Operation The sampling architecture of the ADC’s analog comparator is illustrated in the equivalent input circuits in Figures 3a and 3b. In single-ended mode, IN+ is internally switched to channels CH0–CH7 for the MAX1090 (Figure 3a) and to CH0–CH3 for the MAX1092 (Figure 3b), while IN- is switched to COM (Table 3). In differential mode, IN+ and IN- are selected from analog input pairs (Table 4). In differential mode, IN- and IN+ are internally switched to either of the analog inputs. This configuration is pseudodifferential in that only the signal at IN+ is sampled. The return side (IN-) must remain stable within ±0.5LSB (±0.1LSB for best performance) with respect to GND during a conversion. To accomplish this, connect a 0.1µF capacitor from IN- (the selected input) to GND. During the acquisition interval, the channel selected as the positive input (IN+) charges capacitor CHOLD. At the end of the acquisition interval, the T/H switch opens, retaining the charge on CHOLD as a sample of the signal at IN+. The conversion interval begins with the input multiplexer switching CHOLD from the positive input (IN+) to the negative input (IN-). This unbalances node ZERO at the comparator’s positive input. The capacitive digital-toanalog converter (DAC) adjusts during the remainder of the conversion cycle to restore node ZERO to 0V within the limits of 10-bit resolution. This action is equivalent to transferring a 12pF [(VIN+) - (VIN-)] charge from CHOLD to the binary-weighted capacitive DAC, which in turn forms a digital representation of the analog input signal. _______________________________________________________________________________________ 9 MAX1090/MAX1092 400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface 10-BIT CAPACITIVE DAC 10-BIT CAPACITIVE DAC REF CH0 CH1 REF COMPARATOR INPUT CHOLD MUX – + ZERO CH5 CH6 CH7 COM CSWITCH TRACK T/H SWITCH RIN 800Ω CH1 CSWITCH CH2 HOLD AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL. SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7 Figure 3a. MAX1090 Simplified Input Structure TRACK CH3 T/H SWITCH COM HOLD AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL. SINGLE-ENDED MODE: IN+ = CH0–CH3, IN- = COM PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF CH0/CH1 AND CH2/CH3 Figure 3b. MAX1092 Simplified Input Structure Analog Input Protection Internal protection diodes, which clamp the analog input to VDD and GND, allow each input channel to swing within (GND - 300mV) to (VDD + 300mV) without damage. However, for accurate conversions near full scale, neither input should exceed (VDD + 50mV) or be less than (GND - 50mV). If an off-channel analog input voltage exceeds the supplies by more than 50mV, limit the forward-bias input current to 4mA. Track/Hold The MAX1090/MAX1092 T/H stage enters its tracking mode on the rising edge of WR. In external acquisition mode, the part enters its hold mode on the next rising edge of WR. In internal acquisition mode, the part enters its hold mode on the fourth falling edge of the clock after writing the control byte. Note that in internal clock mode, this is approximately 1µs after writing the control byte. In single-ended operation, IN- is connected to COM and the converter samples the positive (+) input. In pseudo-differential operation, IN- connects to the negative input (-) and the difference of |(IN+) - (IN-)| is sampled. At the beginning of the next conversion, the positive input connects back to IN+ and C HOLD charges to the input signal. The time required for the T/H stage to acquire an input signal depends on how quickly its input capacitance is charged. If the input signal’s source impedance is high, the acquisition time lengthens and more time must be 10 ZERO 12pF RIN 800Ω CH2 CH3 CH4 CH0 12pF COMPARATOR INPUT CHOLD MUX – + allowed between conversions. The acquisition time, tACQ, is the maximum time the device takes to acquire the signal and is also the minimum time required for the signal to be acquired. Calculate this with the following equation: tACQ = 7 (RS + RIN) CIN where RS is the source impedance of the input signal, RIN (800Ω) is the input resistance, and CIN (12pF) is the input capacitance of the ADC. Source impedances below 3kΩ have no significant impact on the MAX1090/ MAX1092’s AC performance. Higher source impedances can be used if a 0.01µF capacitor is connected to the individual analog inputs. Along with the input impedance, this capacitor forms an RC filter, limiting the ADC’s signal bandwidth. Input Bandwidth The MAX1090/MAX1092 T/H stage offers a 350kHz fulllinear and a 6MHz full-power bandwidth. These features make it possible to digitize high-speed transients and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. To avoid aliasing high-frequency signals into the frequency band of interest, anti-alias filtering is recommended. Starting a Conversion Initiate a conversion by writing a control byte that selects the multiplexer channel and configures the MAX1090/MAX1092 for either unipolar or bipolar operation. A write pulse (WR + CS) can either start an acqui- ______________________________________________________________________________________ 400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface Internal Acquisition Select internal acquisition by writing the control byte with the ACQMOD bit cleared (ACQMOD = 0). This causes the write pulse to initiate an acquisition interval whose duration is internally timed. Conversion starts when this acquisition interval (three external clock cycles or approximately 1µs in internal clock mode) ends (Figure 4). When the internal acquisition is combined with the internal clock, the aperture jitter can be as high as 200ps. Internal clock users wishing to achieve the 50ps jitter specification should always use external acquisition mode. External Acquisition Use external acquisition mode for precise control of the sampling aperture and/or dependent control of acquisition and conversion times. The user controls acquisition and start-of-conversion with two separate write pulses. The first pulse, written with ACQMOD = 1, starts an acquisition interval of indeterminate length. The second write pulse, written with ACQMOD = 0 (all other bits in the control byte are unchanged), terminates acquisition and starts conversion on WR rising edge (Figure 5). The address bits for the input multiplexer must have the same values on the first and second write pulses. Power-down mode bits (PD0, PD1) can assume new values on the second write pulse (see the Power-Down Modes section). Changing other bits in the control byte will corrupt the conversion. Reading a Conversion A standard interrupt signal, INT, is provided to allow the MAX1090/MAX1092 to flag the µP when the conversion has ended and a valid result is available. INT goes low when the conversion is complete and the output data is ready (Figures 4 and 5). INT returns high on the first read cycle or if a new control byte is written. Selecting Clock Mode The MAX1090/MAX1092 operate with an internal or external clock. Control bits D6 and D7 select either internal or external clock mode. The part retains the last-requested clock mode if a power-down mode is selected in the current input word. For both internal and external clock modes, internal or external acquisition Table 1. Control Byte Functional Description BIT NAME FUNCTION PD1 and PD0 select the various clock and power-down modes. D7, D6 D5 D4 D3 D2, D1, D0 PD1, PD0 0 0 Full Power-Down Mode. Clock mode is unaffected. 0 1 Standby Power-Down Mode. Clock mode is unaffected. 1 0 Normal Operation Mode. Internal clock mode is selected. 1 1 Normal Operation Mode. External clock mode is selected. ACQMOD ACQMOD = 0: Internal Acquisition Mode ACQMOD = 1: External Acquisition Mode SGL/DIF SGL/DIF = 0: Pseudo-Differential Analog Input Mode SGL/DIF = 1: Single-Ended Analog Input Mode In single-ended mode, input signals are referred to COM. In pseudo-differential mode, the voltage difference between two channels is measured (Tables 2 and 3). UNI/BIP UNI/BIP = 0: Bipolar Mode UNI/BIP = 1: Unipolar Mode In unipolar mode, an analog input signal from 0 to VREF can be converted; in bipolar mode, the signal can range from -VREF/2 to +VREF/2. A2, A1, A0 Address bits A2–A0 select which of the 8/4 (MAX1090/MAX1092) channels is to be converted (Tables 3 and 4). ______________________________________________________________________________________ 11 MAX1090/MAX1092 sition interval or initiate a combined acquisition plus conversion. The sampling interval occurs at the end of the acquisition interval. The ACQMOD (acquisition mode) bit in the input control byte (Table 1) offers two options for acquiring the signal: an internal and an external acquisition. The conversion period lasts for 13 clock cycles in either the internal or external clock or acquisition mode. Writing a new control byte during a conversion cycle will abort the conversion and start a new acquisition interval. MAX1090/MAX1092 400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface tCS CS tACQ tCSWS tCSWH tWR tCONV WR tDH tDS CONTROL BYTE D7–D0 ACQMOD = "0" tINT1 INT RD HBEN tD0 tTR tD01 HIGH-Z HIGH/LOW BYTE VALID DOUT HIGH/LOW BYTE VALID HIGH-Z Figure 4. Conversion Timing Using Internal Acquisition Mode tCS CS tCSWS tWR tACQ tCSHW tCONV WR tDH tDS CONTROL BYTE ACQMOD = "1" D7–D0 CONTROL BYTE ACQMOD = "0" tINT1 INT RD HBEN tD0 HIGH-Z DOUT tD01 HIGH/LOW BYTE VALID tTR HIGH/LOW BYTE VALID Figure 5. Conversion Timing Using External Acquisition Mode 12 ______________________________________________________________________________________ HIGH-Z 400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface CLK pin either high or low to prevent the pin from floating. Internal Clock Mode Select internal clock mode to release the µP from the burden of running the SAR conversion clock. To select this mode, bit D7 of the control byte must be set to 1 and bit D6 must be set to 0; the internal clock frequency is then selected, resulting in a 3.6µs conversion time. When using the internal clock mode, connect the External Clock Mode To select the external clock mode, bits D6 and D7 of the control byte must be set to one. Figure 6 shows the clock and WR timing relationship for internal (Figure 6a) and external (Figure 6b) acquisition modes with an external clock. Proper operation requires a 100kHz to 7.6MHz clock frequency with 30% to 70% duty cycle. Operating the MAX1090/MAX1092 with clock frequen- ACQUISITION STARTS tCP CONVERSION STARTS ACQUISITION ENDS CLK tCWS tCH WR tCL WR GOES HIGH WHEN CLK IS HIGH. ACQMOD = "0" tCWH ACQUISITION STARTS ACQUISITION ENDS CONVERSION STARTS CLK WR ACQMOD = "0" WR GOES HIGH WHEN CLK IS LOW. Figure 6a. External Clock and WR Timing (Internal Acquisition Mode) ACQUISITION STARTS ACQUISITION ENDS CONVERSION STARTS CLK tCWS tDH WR ACQMOD = "0" WR GOES HIGH WHEN CLK IS HIGH. ACQMOD = "1" ACQUISITION STARTS ACQUISITION ENDS CONVERSION STARTS CLK tCWH tDH WR ACQMOD = "1" WR GOES HIGH WHEN CLK IS LOW. ACQMOD = "0" Figure 6b. External Clock and WR Timing (External Acquisition Mode) ______________________________________________________________________________________ 13 MAX1090/MAX1092 can be used. At power-up, the MAX1090/MAX1092 enter the default external clock mode. MAX1090/MAX1092 400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface Input Format The control byte is latched into the device on pins D7– D0 during a write command. Table 2 shows the control byte format. cies lower than 100kHz is not recommended because it will cause a voltage droop across the hold capacitor in the T/H stage that will result in degraded performance. Digital Interface Output Format The output format for the MAX1090/MAX1092 is binary in unipolar mode and two’s complement in bipolar mode. When reading the output data, CS and RD must be low. When HBEN = 0, the lower 8 bits are read. With HBEN = 1, the upper 2 bits are available and the output data bits D7–D2 are set either low in unipolar mode or to the value of the MSB in bipolar mode (Table 5). Input (control byte) and output data are multiplexed on a three-state parallel interface. This parallel interface (I/O) can easily be interfaced with standard µPs. The signals CS, WR, and RD control the write and read operations. CS represents the chip-select signal, which enables a µP to address the MAX1090/MAX1092 as an I/O port. When high, CS disables the CLK, WR, and RD inputs and forces the interface into a high-impedance (high-Z) state. Table 2. Control Byte Format D7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB) PD1 PD0 ACQMOD SGL/DIF UNI/BIP A2 A1 A0 Table 3. Channel Selection for Single-Ended Operation (SGL/DIF = 1) A2 A1 A0 CH0 0 0 0 + 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 CH1 CH2 CH3 CH4* CH5* CH6* CH7* COM - + + + + + + + - *Channels CH4–CH7 apply to MAX1090 only. Table 4. Channel Selection for Pseudo-Differential Operation (SGL/DIF = 0) A2 A1 A0 CH0 CH1 0 0 0 + - CH2 CH3 CH4* CH5* CH6* 0 0 1 - + 0 1 0 + - 0 1 1 - + 1 0 0 + - 1 0 1 - + 1 1 0 + - 1 1 1 - + *Channels CH4–CH7 apply to MAX1090 only. 14 ______________________________________________________________________________________ CH7* 400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface PIN HBEN = 0 D0 Bit 0 (LSB) D1 Bit 1 VDD = +5V 50k HBEN = 1 Bit 8 MAX1090 MAX1092 330k Bit 9 (MSB) 50k BIPOLAR (UNI/BIP = 0) UNIPOLAR (UNI/BIP = 1) D2 Bit 2 Bit 9 0 D3 Bit 3 Bit 9 0 D4 Bit 4 Bit 9 0 D5 Bit 5 Bit 9 0 D6 Bit 6 Bit 9 0 D7 Bit 7 Bit 9 0 ___________Applications Information Power-On Reset When power is first applied, internal power-on reset circuitry activates the MAX1090/MAX1092 in external clock mode and sets INT high. After the power supplies stabilize, the internal reset time is 10µs, and no conversions should be attempted during this phase. When using the internal reference, 500µs are required for VREF to stabilize. Internal and External Reference The MAX1090/MAX1092 can be used with an internal or external reference voltage. An external reference can be connected directly to REF or REFADJ. An internal buffer is designed to provide +2.5V at REF for both devices. The internally trimmed +1.22V reference is buffered with a +2.05V/V gain. Internal Reference The full-scale range with the internal reference is +2.5V with unipolar inputs and ±1.25V with bipolar inputs. The internal reference buffer allows for small adjustments (±100mV) in the reference voltage (Figure 7). Note: The reference buffer must be compensated with an external capacitor (4.7µF min) connected between REF and GND to reduce reference noise and switching spikes from the ADC. To further minimize reference noise, connect a 0.01µF capacitor between REFADJ and GND. External Reference With the MAX1090/MAX1092, an external reference can be placed at either the input (REFADJ) or the output (REF) of the internal reference-buffer amplifier. REFADJ GND 4.7µF REF 0.01µF Figure 7. Reference Voltage Adjustment with External Potentiometer Using the REFADJ input makes buffering the external reference unnecessary. The REFADJ input impedance is typically 17kΩ. When applying an external reference to REF, disable the internal reference buffer by connecting REFADJ to V DD . The DC input resistance at REF is 25kΩ. Therefore, an external reference at REF must deliver up to 200µA DC load current during a conversion and have an output impedance less than 10Ω. If the reference has higher output impedance or is noisy, bypass it close to the REF pin with a 4.7µF capacitor. Power-Down Modes To save power, place the converter in a low-current shutdown state between conversions. Select standby mode or shutdown mode through bits D6 and D7 of the control byte (Tables 1 and 2). In both software powerdown modes, the parallel interface remains active, but the ADC does not convert. Standby Mode While in standby mode, the supply current is 1mA (typ). The part will power up on the next rising edge on WR and is ready to perform conversions. This quick turn-on time allows the user to realize significantly reduced power consumption for conversion rates below 400ksps. Shutdown Mode Shutdown mode turns off all chip functions that draw quiescent current, reducing the typical supply current to 2µA immediately after the current conversion is completed. A rising edge on WR causes the MAX1090/ MAX1092 to exit shutdown mode and return to normal operation. To achieve full 10-bit accuracy with a 4.7µF reference bypass capacitor, 500µs is required after power-up. Waiting this 500µs in standby mode instead of in full-power mode can reduce power consumption by a factor of 3 or more. When using an external reference, ______________________________________________________________________________________ 15 MAX1090/MAX1092 Table 5. Data-Bus Output (8+2 Parallel Interface) MAX1090/MAX1092 400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface only 50µs are required after power-up. Enter standby mode by performing a dummy conversion with the control byte specifying standby mode. Note: Bypass capacitors larger than 4.7µF between REF and GND will result in longer power-up delays. Transfer Function Table 6 shows the full-scale voltage ranges for unipolar and bipolar modes. Figure 8 depicts the nominal, unipolar input/output (I/O) transfer function, and Figure 9 shows the bipolar I/O transfer function. Code transitions occur halfway between successive-integer LSB values. Output coding is binary, with 1LSB = VREF / 1024. OUTPUT CODE FULL-SCALE TRANSITION 111 . . . 111 FS = REF + COM 111 . . . 110 ZS = COM 100 . . . 010 100 . . . 001 1LSB = 100 . . . 000 REF 1024 011 . . . 111 011 . . . 110 011 . . . 101 000 . . . 001 Maximum Sampling Rate/ Achieving 475ksps When running at the maximum clock frequency of 7.6MHz, the specified 400ksps throughput is achieved by completing a conversion every 19 clock cycles: 1 write cycle, 3 acquisition cycles, 13 conversion cycles, and 2 read cycles. This assumes that the results of the last conversion are read before the next control byte is written. It’s possible to achieve higher throughputs (Figure 10), up to 475ksps, by first writing a control word to begin the acquisition cycle of the next conversion, then reading the results of the previous conversion from the bus. This technique allows a conversion to be completed every 16 clock cycles. Note that switching the data bus during acquisition or conversion can cause additional supply noise that may make it difficult to achieve true 10-bit performance. Layout, Grounding, and Bypassing For best performance, use printed circuit boards. Wirewrap configurations are not recommended since the layout should ensure proper separation of analog and digital traces. Do not run analog and digital lines parallel to each other, and do not lay out digital signal paths underneath the ADC package. Use separate analog and digital PC board ground sections with only one star point (Figure 11) connecting the two ground systems (analog and digital). For lowest noise operation, ensure the ground return to the star ground’s power supply is low impedance and as short as possible. Route digital signals far away from sensitive analog and reference inputs. 000 . . . 000 0 1 2 512 FS INPUT VOLTAGE (LSB) (COM) FS - 3/2LBS Figure 8. Unipolar Transfer Function OUTPUT CODE 011 . . . 111 FS = REF + COM 2 011 . . . 110 ZS = COM 000 . . . 010 000 . . . 001 000 . . . 000 -REF + COM 2 REF 1LSB = 1024 -FS = 111 . . . 111 111 . . . 110 111 . . . 101 100 . . . 001 100 . . . 000 COM* - FS +FS - 1LSB INPUT VOLTAGE (LSB) *COM ≤ VREF / 2 Figure 9. Bipolar Transfer Function Table 6. Full Scale and Zero Scale for Unipolar and Bipolar Operation UNIPOLAR MODE 16 BIPOLAR MODE Full Scale VREF + COM Positive Full Scale Zero Scale COM Zero Scale VREF/2 + COM COM — — Negative Full Scale -VREF/2 + COM ______________________________________________________________________________________ 400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface MAX1090/MAX1092’s INL is measured using the endpoint method. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function. Aperture Jitter __________________________Definitions Integral Nonlinearity Aperture jitter (tAJ) is the sample-to-sample variation in the time between the samples. Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. The Aperture delay (t AD ) is the time between the rising edge of the sampling clock and the instant when an actual sample is taken. 1 2 3 4 5 6 7 8 9 Aperture Delay 10 11 12 13 14 15 16 CLK WR RD HBEN D7–D0 D9–D8 CONTROL D7–D0 BYTE D7–D0 D9–D8 CONTROL BYTE LOW HIGH BYTE BYTE STATE LOW BYTE CONVERSION ACQUISITION HIGH BYTE ACQUISITION SAMPLING INSTANT Figure 10. Timing Diagram for Fastest Conversion ______________________________________________________________________________________ 17 MAX1090/MAX1092 High-frequency noise in the power supply (VDD) could influence the proper operation of the ADC’s fast comparator. Bypass VDD to the star ground with a network of two parallel capacitors, 0.1µF and 4.7µF, located as close as possible to the MAX1090/MAX1092 powersupply pin. Minimize capacitor lead length for best supply-noise rejection, and add an attenuation resistor (5Ω) if the power supply is extremely noisy. MAX1090/MAX1092 400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency’s RMS amplitude to RMS equivalent of all other ADC output signals. SINAD (dB) = 20 · log (SignalRMS / NoiseRMS) SUPPLIES +3V R* = 5Ω VLOGIC = +3V/+5V GND 4.7µF 0.1µF VDD GND MAX1090 MAX1092 COM +3V/+5V DGND DIGITAL CIRCUITRY *OPTIONAL Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of the input signal’s first five harmonics to the fundamental itself. This is expressed as: THD = 20 Figure 11. Power-Supply and Grounding Connections Signal-to-Noise Ratio For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of fullscale analog input (RMS value) to the RMS quantization error (residual error). The ideal theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNR = (6.02 · N + 1.76)dB In reality, there are other noise sources besides quantization noise, including thermal noise, reference noise, clock jitter, etc. Therefore, SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. 18 Effective Number of Bits Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the ADC’s full-scale range, calculate the ENOB as follows: ENOB = (SINAD - 1.76) / 6.02 2 V2 + V32 + V4 2 + V52 / V1 ⋅ log where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion component. Chip Information TRANSISTOR COUNT: 5781 ______________________________________________________________________________________ 400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface CLK +2.7V TO +5.5V VLOGIC +5V MAX1090 VDD µP CONTROL INPUTS CS REF WR REFADJ CLK 0.1µF 4.7µF +2.7V TO +5.5V +5V MAX1092 VDD +2.5V RD VLOGIC µP CONTROL INPUTS HBEN CS REF WR REFADJ +2.5V 4.7µF 0.1µF RD HBEN INT OUTPUT STATUS INT OUTPUT STATUS CH7 D7 CH6 D7 D6 CH5 D6 D5 CH4 D4 CH3 D3 CH2 D2 CH1 D1/D9 CH0 D0/D8 COM D5 ANALOG INPUTS GND D4 CH3 D3 CH2 D2 CH1 D1/D9 CH0 D0/D8 COM ANALOG INPUTS GND GND µP DATA BUS GND µP DATA BUS Pin Configurations (continued) TOP VIEW Ordering Information (continued) PART HBEN 1 28 VLOGIC TEMP. RANGE PIN-PACKAGE INL (LSB) MAX1092ACEG 0°C to +70°C 24 QSOP ±0.5 D7 2 27 VDD MAX1092BCEG 0°C to +70°C 24 QSOP ±1 D6 3 26 REF MAX1092AEEG -40°C to +85°C 24 QSOP ± 0.5 D5 4 25 REFADJ MAX1092BEEG -40°C to +85°C 24 QSOP ±1 D4 5 D3 6 24 GND MAX1090 23 COM D2 7 22 CH0 D1/D9 8 21 CH1 D0/D8 9 20 CH2 INT 10 19 CH3 RD 11 18 CH4 WR 12 17 CH5 CLK 13 16 CH6 CS 14 15 CH7 QSOP ______________________________________________________________________________________ 19 MAX1090/MAX1092 Typical Operating Circuits 400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface QSOP.EPS MAX1090/MAX1092 Package Information Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.