19-3861; Rev 0; 10/05 22-Bit, Low-Power, 5MHz to 10MHz Serializer and Deserializer Chipsets The MAX9223/MAX9224 serializer/deserializer chipsets reduce wiring by serializing 22 bits onto a single differential pair. 22 bits are serialized in each cycle of the parallel input clock resulting in a 110Mbps to 220Mbps net serial-data rate ideal for cell phone QVGA and QCIF displays. The MAX9223 serializes the 18-bit RGB, VSYNC, HSYNC, and two control signals from the baseband processor to reduce wiring through the hinge to the LCD controller. The 2-wire serial interface uses low-current differential signaling (LCDS) for low EMI, high commonmode noise immunity, and ground-shift tolerance. The MAX9223/MAX9224 automatically identify the word boundary in serial data in case of signal interruption. The MAX9224 power-down is controlled by the MAX9223. The MAX9223 and MAX9224 consume 3.5µA or less in power-down mode. The MAX9223 serializer operates from a single +2.375V to +3.465V supply and accepts +1.71V to +3.465V inputs. The MAX9224 deserializer operates from a +2.375V to +3.465V core supply and has a separate output buffer supply (V DDO ), allowing +1.71V to +3.465V output high levels. The MAX9223/MAX9224 are specified over the -40°C to +85°C extended temperature range and are available in 28-pin TQFN (4mm x 4mm x 0.8mm) packages with an exposed paddle. Applications Cell Phones Features ♦ Ideal for Serializing Cell Phone LCD or Imager Parallel Interface ♦ MAX9223 Serializes 18-Bit RGB, VSYNC, HSYNC, and Two Control Signals ♦ LCDS Rejects Common-Mode Noise ♦ Automatic Location of Word Boundary After Signal Interruption ♦ Power-Down Control Through the Serial Link ♦ Power-Down Supply Current 0.5µA (max)—MAX9223 3.0µA (max)—MAX9224 ♦ +2.375V to +3.465V Core Supply Voltage ♦ Parallel I/O Interfaces Directly to 1.8V to 3.3V Logic ♦ ±15kV Human Body Model ESD Protection ♦ -40°C to +85°C Operating Temperature Range Ordering Information PART TEMP RANGE PINPACKAGE PKG CODE MAX9223ETI -40°C to +85°C 28 TQFN-EP* T2844-1 MAX9223ETI+ -40°C to +85°C 28 TQFN-EP* T2844-1 MAX9224ETI -40°C to +85°C 28 TQFN-EP* T2844-1 MAX9224ETI+ -40°C to +85°C 28 TQFN-EP* T2844-1 LCDs +Denotes lead-free package. *EP = Exposed paddle. Digital Cameras Pin Configurations appear at end of data sheet. Typical Application Circuit LCDS LATCH INPUT PARALLEL DATA IN PARALLEL TO SERIAL TIMING AND CONTROL PIXEL CLOCK IN SERIAL TO PARALLEL OUTPUT LATCH POWER-DOWN CONTROL TIMING AND CONTROL DLL MAX9223 PARALLEL DATA OUT PIXEL CLOCK OUT MAX9224 ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9223/MAX9224 General Description MAX9223/MAX9224 22-Bit, Low-Power, 5MHz to 10MHz Serializer and Deserializer Chipset ABSOLUTE MAXIMUM RATINGS VDD to GND ...........................................................-0.5V to +4.0V VDDO to GND.........................................................-0.5V to +4.0V Serial Interface (SDO+, SDO-, SDI+, SDI-) to GND .....................................................-0.5V to +4.0V Single-Ended Inputs (DIN_, PCLKIN, PWRDN) to GND ....................................-0.5V to (VDD + 0.5V) Single-Ended Outputs (DOUT_, PCLKOUT) to GND ..............................-0.5V to (VDDO + 0.5V) Continuous Power Dissipation (TA = +70°C) 28-Pin TQFN (4mm x 4mm x 0.8mm) Multilayer PC Board (derate 28.6mW/°C above +70°C).............................................................2286mW Single-Layer PC Board (derate 20.8mW/°C above +70°C).............................................................1667mW Storage Temperature Range .............................-65°C to +150°C Junction Temperature ......................................................+150°C Lead Temperature (soldering, 10s) .................................+300°C ESD Protection (Human Body Model) SDO+, SDO-, SDI+, SDI- to GND ...............................> ±15kV All Other Pins ................................................................> ±2kV Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS—MAX9223 (VDD = +2.375V to +3.465V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = +2.5V, TA = +25°C.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SINGLE-ENDED INPUTS (PCLKIN, DIN_, PWRDN) High-Level Input Voltage VIH Low-Level Input Voltage VIL 1.19 VIN = 0V to VDD Input Current IIN -0.3V ≤ VIN < 0V VDD < VIN ≤ (VDD + 0.3V) VDD + 0.3 -0.3 +0.3 -20 +20 -100 +100 V V µA LCDS OUTPUT (SDO+, SDO-) Differential Output Current (Note 3) Output Short-Circuit Current IODH High level 600 643 880 IODL Low level 200 229 300 IOS Shorted to 0V or VDD IDD VDD = 2.5V, DIN_ = all low or all high 880 µA µA POWER SUPPLY Supply Current Worst-Case Pattern Supply Current Power-Down Supply Current 2 IDDW IDDZ VDD = 2.5V, Figure 1 PCLKIN = 5MHz (110Mbps) 4.4 8.2 PCLKIN = 10MHz (220Mbps) 5.6 8.2 PCLKIN = 5MHz (110Mbps) 4.1 10.6 PCLKIN = 10MHz (220Mbps) 5.4 10.6 mA mA All inputs = low _______________________________________________________________________________________ 0.5 µA 22-Bit, Low-Power, 5MHz to 10MHz Serializer and Deserializer Chipset (VDD = +2.375V to +3.465V, VDDO = +1.71V to +3.465V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = VDDO = +2.5V, TA = +25°C.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SINGLE-ENDED OUTPUTS (PCLKOUT, DOUT_) High-Level Output Voltage VOH VDDO = +2.375V to +3.465V, IOH = -1mA Low-Level Output Voltage VOL VDDO = +2.375V to +3.465V, IOL = 1mA Output Short-Circuit Current IOS Output shorted to ground VDDO = 2.375V 0.8 x VDDO V 0.2 V -2 VDDO = 3.135V -9 VDDO = 3.465V -20 mA LCDS INPUT (SDI+, SDI-) Differential Input-Current Threshold IID Common-Mode Input Current IIC Differential Input Impedance ZID 400 µA -300 ±500 +300 IIC = 0µA at VDD = 3.3V ±5% 69 90 109 IIC = 0µA at VDD = 2.8V ±5% 82 108 132 IIC = 0µA at VDD = 2.5V ±5% 95 125 153 IIC = ±300µA at VDD = 3.3V ±5% 67 91 112 IIC = ±300µA at VDD = 2.8V ±5% 86 108 136 Common-Mode Input Impedance ZIC IIC = ±300µA 90 167 375 Input Capacitance CIN SDI+ or SDI- to ground ITOT VDD = VDDO = 2.5V DOUT_ = all high or all low 2 µA Ω Ω pF POWER SUPPLY Supply Current (Note 4) Worst-Case Pattern Supply Current (Note 4) Power-Down Supply Current (Note 4) Supply Difference ITOTW CL = 5pF, VDD = VDDO = 2.5V, Figure 2 PCLKOUT = 5MHz (110Mbps) 9 12 PCLKOUT = 10MHz (220Mbps) 9 12 PCLKOUT = 5MHz (110Mbps) 10 12 PCLKOUT = 10MHz (220Mbps) 10 12 0.08 3 µA -5 +5 % -0.2 +0.2 V mA mA ITOTZ VSD MAX9223 VDD to MAX9224 VDD VGD MAX9223 to MAX9224 ground difference GROUND POTENTIAL Ground Difference _______________________________________________________________________________________ 3 MAX9223/MAX9224 DC ELECTRICAL CHARACTERISTICS—MAX9224 MAX9223/MAX9224 22-Bit, Low-Power, 5MHz to 10MHz Serializer and Deserializer Chipset AC ELECTRICAL CHARACTERISTICS—MAX9223 (VDD = +2.375V to +3.465V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = +2.5V, TA = +25°C.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PCLKIN INPUT REQUIREMENTS (Figure 3) Input Rise Time tR 2 ns Input Fall Time tF 2 ns PCLKIN Period tP 100 200 ns High-Level Pulse Width tPWH 0.3 x tP 0.7 x tP ns Low-Level Pulse Width tPWL 0.3 x tP 0.7 x tP ns Setup Time tS 3 ns Hold Time tH 1 ns AC ELECTRICAL CHARACTERISTICS—MAX9224 (VDD = VDDO = +2.375V to +3.465V, CL = 5pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = VDDO = +2.5V, TA = +25°C.) (Notes 3, 5) PARAMETER SYMBOL MAX UNITS tP Figure 4 100 200 ns High-Level Pulse Width tPWH Figure 4 0.4 x tP 0.6 x tP ns Low-Level Pulse Width tPWL Figure 4 0.4 x tP 0.6 x tP ns Data Valid Before PCLKOUT tVB Figure 4 5 ns Data Valid After PCLKOUT tVA Figure 4 5 ns tPU1 From VDD = VDDO = 2.375V when supplies are ramping up 6144 x tP tPU2 From PWRDN low to high 4096 x tP tPWRDN From PWRDN high to low PCLKOUT Period CONDITIONS MIN TYP SERIALIZER AND DESERIALIZER LINK Power-Up Time Power-Down Time 2.8 10 ns µs Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground. Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production tested at TA = +85°C. Note 3: Parameters are guaranteed by design and characterization, and are not production tested. Limits are set at ±6 sigma. Note 4: ITOT = IDD + IDDO. Note 5: CL includes probe and test jig capacitance. 4 _______________________________________________________________________________________ 22-Bit, Low-Power, 5MHz to 10MHz Serializer and Deserializer Chipset ODD DIN_ ODD DOUT_ EVEN DIN_ EVEN DOUT_ PCLKIN PCLKOUT Figure 1. Serializer Worst-Case Switching Pattern Figure 2. Deserializer Worst-Case Switching Pattern tP tPWL tPWH VIH PCLKIN VIL VIL tF tR tH tS DIN_ PWRDN VIH VIH VIH VIH VIL VIL VIH IS THE MINIMUM HIGH-LEVEL INPUT AND VIL IS THE MAXIMUM LOW-LEVEL INPUT (SEE THE DC ELECTRICAL CHARACTERISTICS TABLE) Figure 3. Serializer Input Timing tP tPWH tPWL VOH VOH PCLKOUT VOL VOL tVB DOUT_ VOH tVA VOH VOH VOL VOL VOH IS THE MINIMUM HIGH-LEVEL OUTPUT AND VOL IS THE MAXIMUM LOW-LEVEL OUTPUT (SEE THE DC ELECTRICAL CHARACTERISTICS TABLE) Figure 4. Deserializer Output Timing _______________________________________________________________________________________ 5 MAX9223/MAX9224 Test Circuits/Timing Diagrams Typical Operating Characteristics (VDD = VDDO = +2.8V, logic input levels = 0 to +2.8V, logic output load CL = 5pF, TA = +25°C, unless otherwise noted.) 4 PCLKIN = 5MHz 10 8 PCLKIN = 10MHz 6 4 DIN[21:0] = WORST-CASE SWITCHING PATTERN 8 PCLKIN = 10MHz 6 4 PCLKIN = 5MHz PCLKIN = 5MHz 2 2 2.7 2.9 3.1 3.3 2.9 3.1 3.3 3.5 2.3 2.7 2.9 3.1 3.3 MAX9223 SUPPLY CURRENT vs. FREQUENCY MAX9223 SUPPLY CURRENT vs. FREQUENCY VDD = 2.5V DIN[21:0] = ALL HIGH VDD = 3.3V SUPPLY CURRENT (mA) VDD = 2.8V 4 8 VDD = 2.8V 6 4 8 VDD = 2.5V VDD = 3.3V 2 6 7 8 9 10 3.5 DIN[21:0] = WORST-CASE SWITCHING PATTERN VDD = 2.8V SUPPLY CURRENT (mA) DIN[21:0] = ALL LOW 5 2.5 MAX9223 SUPPLY CURRENT vs. FREQUENCY 2 6 4 VDD = 2.5V 2 5 6 7 8 9 10 5 6 7 8 9 10 FREQUENCY (MHz) FREQUENCY (MHz) MAX9223 POWER-DOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX9224 SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX9224 SUPPLY CURRENT vs. SUPPLY VOLTAGE 0.08 PCLKOUT = 10MHz 10 9 PCLKOUT = 5MHz 8 0 2.5 2.7 2.9 3.1 SUPPLY VOLTAGE (V) 3.3 3.5 PCLKOUT = 10MHz 10 9 PCLKOUT = 5MHz 8 7 2.3 DOUT[21:0] = ALL HIGH 11 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 0.12 DOUT[21:0] = ALL LOW 11 12 MAX9233/4 toc08 12 MAX9233/4 toc07 PCLKIN = LOW PWRDN = LOW DIN[21:0] = ALL LOW MAX9233/4 toc09 FREQUENCY (MHz) 0.04 6 2.7 SUPPLY VOLTAGE (V) 6 0.16 2.5 SUPPLY VOLTAGE (V) 8 0.20 2 2.3 SUPPLY VOLTAGE (V) VDD = 3.3V SUPPLY CURRENT (mA) 3.5 MAX9233/4 toc05 10 2.5 MAX9233/4 toc04 2.3 MAX9233/4 toc03 DIN[21:0] = ALL HIGH MAX9233/4 toc06 6 MAX9223 SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT (mA) PCLKIN = 10MHz 8 10 MAX9233/4 toc01 DIN[21:0] = ALL LOW SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 10 MAX9223 SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX9233/4 toc02 MAX9223 SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT (µA) MAX9223/MAX9224 22-Bit, Low-Power, 5MHz to 10MHz Serializer and Deserializer Chipset 7 2.3 2.5 2.7 2.9 3.1 SUPPLY VOLTAGE (V) 3.3 3.5 2.3 2.5 2.7 2.9 3.1 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 3.3 3.5 22-Bit, Low-Power, 5MHz to 10MHz Serializer and Deserializer Chipset PCLKOUT = 5MHz VDD = 2.8V 10 9 VDD = 2.5V 8 2.7 2.9 3.1 3.3 9 VDD = 2.5V 6 7 8 9 10 5 6 7 8 9 10 FREQUENCY (MHz) FREQUENCY (MHz) MAX9224 SUPPLY CURRENT vs. FREQUENCY MAX9224 POWER-DOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX9224 DOUT OUTPUT-HIGH VOLTAGE vs. SOURCE CURRENT 0.6 10 9 VDD = 2.5V 8 2.75 VDDO = 2.375V VDDO = 2V 2.50 0.5 2.25 DOUT (V) SUPPLY CURRENT (µA) VDD = 2.8V SDI+/SDI- PULLED UP TO VDD DOUT[21:0] = ALL LOW MAX9233/4 toc15 SUPPLY VOLTAGE (V) DOUT[21:0] = WORST-CASE SWITCHING PATTERN VDD = 3.3V 11 10 7 5 3.5 MAX9233/4 toc14 12 2.5 MAX9233/4 toc13 2.3 VDD = 3.3V VDD = 2.8V 8 7 7 DOUT[21:0] = ALL HIGH 11 SUPPLY CURRENT (mA) 9 12 MAX9233/4 toc11 VDD = 3.3V 0.4 2.00 1.75 0.3 1.50 VDDO = 1.71V 7 1.25 0.2 7 8 9 10 2.3 2.5 FREQUENCY (MHz) 2.7 2.9 3.1 MAX9224 DOUT OUTPUT-LOW VOLTAGE vs. SINK CURRENT 0 3.5 0.2 VDDO = +1.71V TO +2.375V 120 0.4 0.6 0.8 1.0 SOURCE CURRENT (mA) MAX9224 DIFFERENTIAL INPUT IMPEDANCE vs. SUPPLY VOLTAGE 160 90 60 30 0 MAX9233/4 toc17 150 3.3 SUPPLY VOLTAGE (V) INPUT IMPEDANCE (Ω) 6 DOUT (mV) 5 MAX9233/4 toc16 SUPPLY CURRENT (mA) 10 8 SUPPLY CURRENT (mA) DOUT[21:0] = ALL LOW 11 SUPPLY CURRENT (mA) DOUT[21:0] = WORST-CASE SWITCHING PATTERN PCLKOUT = 10MHz 11 12 MAX9233/4 toc10 12 MAX9224 SUPPLY CURRENT vs. FREQUENCY MAX9233/4 toc12 MAX9224 SUPPLY CURRENT vs. FREQUENCY MAX9224 SUPPLY CURRENT vs. SUPPLY VOLTAGE 140 120 100 80 0 0.2 0.4 0.6 SINK CURRENT (mA) 0.8 1.0 2.3 2.5 2.7 2.9 3.1 3.3 3.5 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 7 MAX9223/MAX9224 Typical Operating Characteristics (continued) (VDD = VDDO = +2.8V, logic input levels = 0 to +2.8V, logic output load CL = 5pF, TA = +25°C, unless otherwise noted.) 22-Bit, Low-Power, 5MHz to 10MHz Serializer and Deserializer Chipset MAX9223/MAX9224 Pin Description (MAX9223) PIN NAME 1–12, 14, 15, 21–28 DIN13–DIN2, DIN1, DIN0, DIN21–DIN14 FUNCTION 13 PCLKIN Parallel Clock Input. The rising edge of PCLKIN (typically the pixel clock) latches the parallel data input. Internally pulled down to GND. 16 PWRDN Power-Down Input. Pull PWRDN low to place the MAX9223 and MAX9224 in power-down mode. Drive PWRDN high for normal operation. Internally pulled down to GND. 17 SDO- 18 SDO+ Noninverting LCDS Serial-Data Output 19 GND Ground 20 VDD Core Supply Voltage. Bypass to GND with 0.1µF and 0.01µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. — EP Single-Ended Parallel Data Inputs. The 22 data bits are loaded into the input latch on the rising edge of PCLKIN. DIN[9:0] are 1.71V to 3.465V tolerant. Internally pulled down to GND. Inverting LCDS Serial-Data Output Exposed Paddle. Connect EP to ground. Pin Description (MAX9224) PIN NAME 1, 7, 8, 10–28 DOUT21, DOUT0, DOUT1, DOUT2–DOUT20 2 VDDO Output Supply Voltage. Bypass to GND with 0.1µF and 0.01µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. 3 GND Ground 4 SDI+ Noninverting LCDS Serial-Data Input 5 SDI- Inverting LCDS Serial-Data Input 6 VDD Core Supply Voltage. Bypass to GND with 0.1µF and 0.01µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. 9 PCLKOUT Parallel Clock Output. Parallel output data are valid on the rising edge of PCLKOUT (typically the pixel clock). — EP 8 FUNCTION Single-Ended Parallel Data Outputs. DOUT[21:0] are valid on the rising edge of PCLKOUT. Exposed Paddle. Connect EP to ground. _______________________________________________________________________________________ 22-Bit, Low-Power, 5MHz to 10MHz Serializer and Deserializer Chipset PARALLEL TO SERIAL LATCH INPUT DIN[21:0] MAX9224 Functional Diagram SDO+ SDI+ SDO- SDI- SERIAL TO PARALLEL OUTPUT LATCH DOUT[21:0] TIMING AND CONTROL PCLKIN PWRDN TIMING AND CONTROL DLL MAX9223 PCLKOUT MAX9224 Detailed Description and PCLKOUT. Output data is valid on the rising edge of PCLKOUT. The first bit (G) is internally grounded and transmitted first. Bit 0 (DIN[0]) is the first valid data bit. Boundary bits OH are used by the MAX9224 deserializer to identify the word boundary and are the inverse polarity of data bit 21 (DIN[21]). Therefore, at least one level transition is guaranteed in one word. The clock is recovered from the serial input. The MAX9223 serializer operates at a 5MHz to 10MHz parallel clock frequency, serializing 22 bits of parallel input data DIN[21:0] in each cycle of the parallel clock. DIN[21:0] are latched on the rising edge of PCLKIN. The data and internally generated serial clock are combined and transmitted through SDO+/SDO- using multilevel LCDS. The MAX9224 deserializer receives the LCDS signal on SDI+/SDI-. The deserialized data and recovered parallel clock are available at DOUT[21:0] Serial word format: G 0 1 2 3 4 5 6 7 8 9 10 LCDS The MAX9223/MAX9224 use a proprietary multilevel LCDS interface. Figure 5 provides a representation of the data and clock in the multilevel LCDS interface. This interface offers advantages over other chipsets, such as requiring only one differential pair as the transmission medium, the inherently aligned data and clock, and much smaller current levels than the 4mA typically found in traditional LVDS interfaces. MAX9223/MAX9224 Handshaking The handshaking function of the MAX9223/MAX9224 provides bidirectional communication between the two devices in case a word boundary error is detected. Prior 11 12 13 14 15 16 17 18 19 20 21 OH OH to data transmission, the MAX9223 serializer adds boundary bits (OH) to the end of the latched word. These boundary bits are the inverse of the last bit of the latched word. During data transmission, the MAX9224 deserializer continuously monitors the state of the boundary bits of each word. If a word boundary error is detected, the serial link is pulled up to VCC and the MAX9224 powers down. The MAX9223 detects the pullup of the serial link and powers down for 1.0µs. After 1.0µs, the MAX9223 powers up, causing the power-up of the MAX9224. Then the word boundary is reestablished, and data transfer resumes. The handshaking function is disabled when PWRDN is pulled low. _______________________________________________________________________________________ 9 MAX9223/MAX9224 MAX9223 Functional Diagram MAX9223/MAX9224 22-Bit, Low-Power, 5MHz to 10MHz Serializer and Deserializer Chipset PARALLEL DATA INPUT PCLK IN DIN[21:0] DIN 0 1 2 3 9 10 11 12 13 14 20 21 EXAMPLE INPUT 1 1 0 1 1 0 0 1 0 1 1 1 LCDS SERIAL DATA OUTPUT FOR EXAMPLE INPUT (SD0±) G* 1 1 0 1 1 0 0 0 1 1 1 1 OH OH *INTERNALLY PREPENDED BIT—ALWAYS 0. NOTE: THERE IS NO TRANSITION BETWEEN OH BITS. Figure 5. Multilevel LCDS Output Representation Applications Information PCLKIN Latch Edge The parallel data input of the MAX9223 serializer is latched on the rising edge of PCLKIN. Figure 3 shows the serializer input timing. PCLKOUT Strobe The serial-data output of the MAX9224 deserializer is valid on the rising edge of PCLKOUT. Figure 4 shows the deserializer output timing. Power-Down and Power-Off Driving PWRDN low puts the MAX9223 in power-down mode and sends a pulse to power down the MAX9224. In power-down mode, the DLL is stopped, SDO+/SDO- are high impedance to ground and differential, and the LCDS link is weakly biased around VDD - 0.8V. With PWRDN and all inputs low, the combined MAX9223/MAX9224 supply current is reduced to 3.5µA or less. Driving PWRDN high starts DLL lock to PCLKIN and initiates a MAX9224 power-up sequence. The MAX9223 10 LCDS output is not driven until the DLL locks. 4096 clock cycles are required for the power-up and link synchronization, before valid DIN can be latched. See Figure 6 for an overall power-up and power-down timing diagram. For normal operation, PCLKIN must be running and settled before driving PWRDN high. If VDD = 0, the LCDS outputs are high impedance to ground and differential. Ground-Shift Tolerance The MAX9223/MAX9224 are designed to function normally in the event of a slight shift in ground potential. However, the MAX9224 deserializer ground must be within ±0.2V relative to the MAX9223 serializer ground to maintain proper operation. MAX9224 Output Buffer Supply (VDDO) The MAX9224 parallel outputs are powered from VDDO, which accepts a +1.71V to +3.465V supply, allowing direct interface to inputs with 1.8V to 3.3V logic levels. ______________________________________________________________________________________ 22-Bit, Low-Power, 5MHz to 10MHz Serializer and Deserializer Chipset POWERDOWN DATA TRANSFER MAX9223/MAX9224 POWER-UP AND LINK SYNCHRONIZATION IN POWERDOWN IN POWERDOWN tPWRDN PWRDN 1 2 4096 PCLKIN DIN_ DON'T CARE 1 LOW DON'T CARE N 1 LOW N DOUT_ PCLKOUT HIGH HIGH Figure 6. MAX9223/MAX9224 Power-Up/Power-Down Sequence Flex Cable, PC Board Interconnect, and Connectors Interconnect for LCDS typically has a differential impedance of 110Ω. Use interconnect and connectors that have matched differential impedance to minimize impedance discontinuities. Board Layout and Supply Bypassing Separate the logic and LCDS signals to prevent crosstalk. A PC board or flex with separate layers for power, ground, and signals is recommended. Bypass each VDD and VDDO pin with high-frequency, surface-mount ceramic 0.1µF and 0.01µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. ESD Protection 1MΩ CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 100pF RD 1.5kΩ DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST Figure 7. Human Body Model ESD Test Circuit Chip Information PROCESS: CMOS The MAX9223/MAX9224 LCDS inputs and outputs (SDO+/SDO-, SDI+/SDI-) are rated for ±15kV ESD protection using the Human Body Model. The Human Body Model discharge components are CS = 100pF and RD = 1.5kΩ (Figure 7). ______________________________________________________________________________________ 11 MAX9223/MAX9224 22-Bit, Low-Power, 5MHz to 10MHz Serializer and Deserializer Chipset SDO- PWRDN DIN0 DOUT13 DOUT12 18 17 16 15 21 20 14 DIN20 22 19 18 17 16 15 14 DOUT14 22 DOUT6 DIN19 23 13 PCLKIN DOUT15 23 13 DOUT5 DIN18 24 12 DIN2 DOUT16 24 12 DOUT4 11 DIN3 DOUT17 25 11 DOUT3 10 DIN4 DOUT18 26 10 DOUT2 DIN17 25 MAX9223 DIN16 26 MAX9224 1 2 3 4 5 6 7 DOUT0 7 VDD 6 SDI- 5 SDI+ 4 GND 3 VDDO 2 DOUT21 1 DIN7 DOUT1 DIN8 PCLKOUT 8 DIN9 9 DOUT20 28 DIN10 DOUT19 27 DIN11 DIN5 DIN6 DIN12 9 8 DIN13 DIN15 27 DIN14 28 TQFN-EP 12 DIN1 DOUT7 SDO+ 19 DOUT8 GND 20 DOUT9 VDD 21 DOUT11 DIN21 TOP VIEW DOUT10 Pin Configurations TQFN-EP ______________________________________________________________________________________ 22-Bit, Low-Power, 5MHz to 10MHz Serializer and Deserializer Chipset 24L QFN THIN.EPS PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm 21-0139 E 1 2 PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm 21-0139 E 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 © 2005 Maxim Integrated Products Springer Printed USA is a registered trademark of Maxim Integrated Products, Inc. MAX9223/MAX9224 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)