19-3680; Rev 1; 12/07 KIT ATION EVALU LE B A IL A AV 10-Bit, Low-Power, 10MHz-to-20MHz Serializer and Deserializer Chipset Features ♦ Ideal for Serializing Cell Phone Camera Parallel Interface The MAX9225/MAX9226 serializer/deserializer chipset reduces wiring by serializing 10 bits onto a single differential pair. Ten bits are serialized in each cycle of the parallel input clock resulting in a 100Mbps to 200Mbps net serial-data rate. The MAX9225 serializes the 8-bit YUV, HSYNC and VSYNC outputs from a camera mounted in the flip part of the phone, reducing wiring through the hinge to the baseband processor in the base of the phone. The 2-wire serial interface uses low-current differential signaling (LCDS) for low EMI, high common-mode noise immunity, and ground-shift tolerance. The MAX9225/MAX9226 automatically identify the word boundary in the serial data in case of signal interruption. The MAX9226 power-down is controlled by the MAX9225. The MAX9225/MAX9226 consume 3.5µA or less in power-down mode. The MAX9225 serializer operates from a single +2.375V to +3.465V supply and accepts +1.71V to +3.465V inputs. The MAX9226 deserializer operates from a +2.375V to +3.465V core supply and has a separate output buffer supply (V DDO ), allowing +1.71V to +3.465V output high levels. The MAX9225/MAX9226 are specified over the -40°C to +85°C extended temperature range and are available in 16-pin TQFN (3mm x 3mm x 0.8mm) packages with an exposed paddle. ♦ MAX9225 Serializes 8-Bit YUV, HSYNC, and VSYNC ♦ LCDS Rejects Common-Mode Noise ♦ Automatic Location of Word Boundary After Signal Interruption ♦ Power-Down Control Through the Serial Link ♦ Power-Down Supply Current 0.5µA (max) for MAX9225 3.0µA (max) for MAX9226 ♦ +2.375V to +3.465V Core Supply Voltage ♦ Parallel I/O Interfaces Directly to 1.8V to 3.3V Logic ♦ ±15kV Human Body Model ESD Protection ♦ -40°C to +85°C Operating Temperature Range Ordering Information PART MAX9225ETE TEMP RANGE PINPACKAGE PKG TOP CODE MARK -40°C to +85°C 16 TQFN-EP* T1633-4 ADO MAX9225ETE+ -40°C to +85°C 16 TQFN-EP* T1633-4 ADO MAX9226ETE Applications -40°C to +85°C 16 TQFN-EP* T1633-4 ADX MAX9226ETE+ -40°C to +85°C 16 TQFN-EP* T1633-4 ADX +Denotes lead-free package. *EP = Exposed paddle. Cell Phone Cameras Digital Cameras Pin Configurations appear at end of data sheet. Typical Application Circuit LCDS INPUT LATCH PARALLEL DATA IN PARALLEL TO SERIAL TIMING AND CONTROL PIXEL CLOCK IN SERIAL TO PARALLEL OUTPUT LATCH POWER-DOWN CONTROL TIMING AND CONTROL DLL MAX9225 PARALLEL DATA OUT PIXEL CLOCK OUT MAX9226 ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9225/MAX9226 General Description MAX9225/MAX9226 10-Bit, Low-Power, 10MHz-to-20MHz Serializer and Deserializer Chipset ABSOLUTE MAXIMUM RATINGS VDD to GND ...........................................................-0.5V to +4.0V VDDO to GND.........................................................-0.5V to +4.0V Serial Interface (SDO+, SDO-, SDI+, SDI-) to GND .....................................................-0.5V to +4.0V Single-Ended Inputs (DIN_, PCLKIN, PWRDN) to GND ....................................-0.5V to (VDD + 0.5V) Single-Ended Outputs (DOUT_, PCLKOUT) to GND ..............................-0.5V to (VDDO + 0.5V) Continuous Power Dissipation (TA = +70°C) 16-Pin TQFN (3mm x 3mm x 0.8mm) Multilayer PCB (derate 20.8mW/°C above +70°C).............................................................1667mW Single-Layer PCB (derate 15.6mW/°C above +70°C).............................................................1250mW Storage Temperature Range .............................-65°C to +150°C Junction Temperature ......................................................+150°C Lead Temperature (soldering, 10s) .................................+300°C ESD Protection (Human Body Model) SDO+, SDO-, SDI+, SDI- to GND ...............................> ±15kV All Other Pins to GND ...................................................> ±2kV Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (MAX9225) (VDD = +2.375V to +3.465V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = +2.5V, TA = +25°C.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SINGLE-ENDED INPUTS (PCLKIN, DIN_, PWRDN) High-Level Input Voltage VIH 1.19 Low-Level Input Voltage VIL -0.3 +0.3 -20 +20 -100 +100 VIN = 0V to VDD Input Current IIN -0.3V ≤ VIN < 0V VDD < VIN ≤ (VDD + 0.3V) VDD + 0.3 V V µA LCDS OUTPUT (SDO+, SDO-) Differential Output Current Output Short-Circuit Current IODH High level 575 643 880 IODL Low level 200 229 300 IOS Shorted to 0V or VDD 880 µA µA POWER SUPPLY Supply Current Worst-Case Pattern Supply Current Power-Down Supply Current 2 IDD IDDW IDDZ VDD = 2.5V VDD = 2.5V, Figure 1 PCLKIN = 10MHz, 100Mbps 4.7 8.2 PCLKIN = 20MHz, 200Mbps 6.2 8.2 PCLKIN = 10MHz, 100Mbps 4.7 10.6 PCLKIN = 20MHz, 200Mbps 6.2 10.6 mA mA All inputs = low _______________________________________________________________________________________ 0.5 µA 10-Bit, Low-Power, 10MHz-to-20MHz Serializer and Deserializer Chipset (VDD = +2.375V to +3.465V, VDDO = +1.71V to +3.465V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = VDDO = +2.5V, TA = +25°C.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SINGLE-ENDED OUTPUTS (PCLKOUT, DOUT_) High-Level Output Voltage VOH VDDO = +2.375V to +3.465V, IOH = -1mA Low-Level Output Voltage VOL VDDO = +2.375V to +3.465V, IOL = 1mA Output Short-Circuit Current IOS Output shorted to ground 0.8 x VDDO V 0.2 VDDO = 2.375V -2 VDDO = 3.135V -9 V mA VDDO = 3.465V -25 LCDS INPUT (SDI+, SDI-) Differential Input-Current Threshold IID Common-Mode Input Current IIC Differential Input Impedance ZID 400 µA -300 ±400 +300 IIC = 0µA, VDD = 3.3V ±5% 69 90 114 IIC = 0µA, VDD = 2.8V ±5% 82 108 137 IIC = 0µA, VDD = 2.5V ±5% 95 125 161 IIC = ±300µA, VDD = 3.3V ±5% 67 91 117 IIC = ±300µA, VDD = 2.8V ±5% 86 108 141 Common-Mode Input Impedance ZIC IIC = ±300µA 90 167 375 Input Capacitance CIN SDI+ or SDI- to ground ITOT VDD = VDDO = 2.5V (Note 4) 2 µA Ω Ω pF POWER SUPPLY Supply Current Worst-Case Pattern Supply Current ITOTW Power-Down Supply Current Supply Difference ITOTZ CL = 5pF, VDD = VDDO = 2.5V, Figure 2 (Note 4) PCLKOUT = 10MHz, 100Mbps 8.4 12 PCLKOUT = 20MHz, 200Mbps 9.1 12 PCLKOUT = 10MHz, 100Mbps 9.7 12 PCLKOUT = 20MHz, 200Mbps 11.6 13 0.3 mA mA (Note 4) VSD MAX9225 VDD to MAX9226 VDD VGD MAX9225 to MAX9226 ground difference 3.0 µA -5 +5 % -0.2 +0.2 V GROUND POTENTIAL Ground Difference _______________________________________________________________________________________ 3 MAX9225/MAX9226 DC ELECTRICAL CHARACTERISTICS (MAX9226) MAX9225/MAX9226 10-Bit, Low-Power, 10MHz-to-20MHz Serializer and Deserializer Chipset AC ELECTRICAL CHARACTERISTICS (MAX9225) (VDD = +2.375V to +3.465V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = +2.5V, TA = +25°C.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PCLKIN INPUT REQUIREMENTS (Figure 3) Input Rise Time tR 2 ns Input Fall Time tF 2 ns PCLKIN Period tP 50 100 ns High-Level Pulse Width tPWH 0.3 x tP 0.7 x tP ns Low-Level Pulse Width tPWL 0.3 x tP 0.7 x tP ns Setup Time tS 3 ns Hold Time tH 1 ns AC ELECTRICAL CHARACTERISTICS (MAX9226) (VDD = VDDO = +2.375V to +3.465V, CL = 5pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = VDDO = +2.5V, TA = +25°C.) (Notes 3, 5) PARAMETER SYMBOL MAX UNITS tP Figure 4 50 100 ns High-Level Pulse Width tPWH Figure 4 0.4 x tP 0.6 x tP ns Low-Level Pulse Width tPWL Figure 4 0.4 x tP 0.6 x tP ns Data Valid Before PCLKOUT tVB Figure 4 5 ns Data Valid After PCLKOUT tVA Figure 4 5 ns tPU1 From VDD = VDDO = 2.375V when supplies are ramping up tPU2 From PWRDN low to high tPWRDN From PWRDN high to low PCLKOUT Period CONDITIONS MIN TYP SERIALIZER AND DESERIALIZER LINK Power-Up Time Power-Down Time 11,264 x tP 4096 x tP 2.8 10 ns µs Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground. Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production tested at TA = +85°C. Note 3: Parameters are guaranteed by design and characterization and are not production tested. Limits are set at ±6 sigma. Note 4: ITOT = IDD + IDDO. Note 5: CL includes probe and test jig capacitance. 4 _______________________________________________________________________________________ 10-Bit, Low-Power, 10MHz-to-20MHz Serializer and Deserializer Chipset ODD DIN_ ODD DOUT_ EVEN DIN_ EVEN DOUT_ PCLKIN PCLKOUT Figure 1. Serializer Worst-Case Switching Pattern Figure 2. Deserializer Worst-Case Switching Pattern tP tPWL tPWH VIH PCLKIN VIL VIL tF tR tH tS DIN_ PWRDN VIH VIH VIH VIH VIL VIL VIH IS THE MINIMUM HIGH-LEVEL INPUT, AND VIL IS THE MAXIMUM LOW-LEVEL INPUT (SEE THE DC ELECTRICAL CHARACTERISTICS TABLE) Figure 3. Serializer Input Timing tP tPWH tPWL VOH VOH PCLKOUT VOL VOL tVB DOUT_ VOH tVA VOH VOH VOL VOL VOH IS THE MINIMUM HIGH-LEVEL OUTPUT, AND VOL IS THE MAXIMUM LOW-LEVEL OUTPUT (SEE THE DC ELECTRICAL CHARACTERISTICS TABLE) Figure 4. Deserializer Output Timing _______________________________________________________________________________________ 5 MAX9225/MAX9226 Test Circuits/Timing Diagrams Typical Operating Characteristics (VDD = VDDO = +2.8V, logic input levels = 0 to +2.8V, logic output load CL = 5pF, TA = +25°C, unless otherwise noted.) PCLKIN = 10MHz 4 2.5 2.7 2.9 3.1 3.3 3.5 PCLKIN = 10MHz 4 2 2.5 2.7 2.9 3.1 3.3 2.3 3.5 2.5 2.7 2.9 3.1 3.3 MAX9225 SUPPLY CURRENT vs. FREQUENCY MAX9225 SUPPLY CURRENT vs. FREQUENCY MAX9225 SUPPLY CURRENT vs. FREQUENCY 6 VDD = 2.5V DIN[9:0] = ALL HIGH 8 SUPPLY CURRENT (mA) VDD = 2.8V VDD = 3.3V VDD = 2.8V 6 10 MAX9225 toc05 10 MAX9225 toc04 VDD = 3.3V VDD = 2.5V 4 12 14 16 18 DIN[9:0] = WORST-CASE SWITCHING PATTERN 8 VDD = 3.3V VDD = 2.8V 6 VDD = 2.5V 2 12 10 20 3.5 4 2 2 MAX9225 toc03 6 SUPPLY VOLTAGE (V) 8 14 16 18 20 10 12 14 16 18 20 FREQUENCY (MHz) FREQUENCY (MHz) MAX9225 POWER-DOWN SUPPLY CURRENT vs. FREQUENCY MAX9226 SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX9226 SUPPLY CURRENT vs. SUPPLY VOLTAGE 0.08 PCLKOUT = 20MHz 9 8 0.04 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 0.12 DIN[9:0] = ALL LOW 10 2.5 2.7 2.9 3.1 SUPPLY VOLTAGE (MHz) 3.3 3.5 DIN[9:0] = ALL HIGH 10 PCLKOUT = 20MHz 9 8 PCLKOUT = 10MHz PCLKOUT = 10MHz 7 7 0 11 MAX9226 toc08 MAX9225 toc07 11 MAX9226 toc09 FREQUENCY (MHz) PCLKIN = LOW PWRDN = LOW DIN[9:0] = ALL LOW 2.3 PCLKIN = 20MHz 8 SUPPLY VOLTAGE (V) DIN[9:0] = ALL LOW 10 DIN[9:0] = WORST-CASE SWITCHING PATTERN SUPPLY VOLTAGE (V) 4 6 PCLKIN = 10MHz 2.3 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 10 0.16 6 2 2.3 0.20 PCLKIN = 20MHz 4 2 SUPPLY CURRENT (mA) 6 DIN[9:0] = ALL HIGH 8 10 MAX9225 toc02 PCLKIN = 20MHz 8 10 MAX9225 toc01 DIN[9:0] = ALL LOW SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 10 MAX9225 SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX9225 SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX9225 toc06 MAX9225 SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT (μA) MAX9225/MAX9226 10-Bit, Low-Power, 10MHz-to-20MHz Serializer and Deserializer Chipset 2.3 2.5 2.7 2.9 3.1 SUPPLY VOLTAGE (V) 3.3 3.5 2.3 2.5 2.7 2.9 3.1 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 3.3 3.5 10-Bit, Low-Power, 10MHz-to-20MHz Serializer and Deserializer Chipset PCLKOUT = 20MHz 9 8 MAX9226 toc11 10 VDD = 3.3V VDD = 2.8V 9 VDD = 2.5V 2.5 2.7 2.9 3.1 3.5 3.3 DIN[9:0] = ALL HIGH 10 VDD = 3.3V VDD = 2.8V 9 VDD = 2.5V 8 7 7 10 12 14 16 10 20 18 12 14 16 18 20 SUPPLY VOLTAGE (V) FREQUENCY (MHz) FREQUENCY (MHz) MAX9226 SUPPLY CURRENT vs. FREQUENCY MAX9226 POWER-DOWN SUPPLY CURRENT vs. FREQUENCY MAX9226 DOUT OUTPUT-HIGH VOLTAGE vs. SOURCE CURRENT VDD = 3.3V VDD = 2.8V 9 VDD = 2.5V 8 2.75 2.50 VDDO = 2.375V 0.5 2.25 DOUT (V) SUPPLY CURRENT (μA) 10 SDI+/SDI- PULLED UP TO VDD DOUT[9:0] = ALL LOW MAX9226 toc15 0.6 MAX9226 toc14 DIN[9:0] = WORST-CASE SWITCHING PATTERN MAX9226 toc13 2.3 0.4 VDDO = 2V 2.00 1.75 VDDO = 1.71V 0.3 1.50 7 1.25 0.2 14 16 20 18 2.3 2.5 FREQUENCY (MHz) 2.7 2.9 3.1 MAX9226 DOUT OUTPUT-LOW VOLTAGE vs. SINK CURRENT 0 3.5 0.2 VDDO = +1.71V TO +2.375V 120 0.4 0.6 0.8 1.0 SOURCE CURRENT (mA) MAX9226 DIFFERENTIAL INPUT IMPEDANCE vs. SUPPLY VOLTAGE 160 90 60 MAX9226 toc17 150 3.3 SUPPLY VOLTAGE (V) INPUT IMPEDANCE (Ω) 12 MAX9226 toc16 10 DOUT (mV) SUPPLY CURRENT (mA) 11 8 PCLKOUT = 10MHz 7 11 DIN[9:0] = ALL LOW SUPPLY CURRENT (mA) 10 11 MAX9226 toc10 DIN[9:0] = WORST-CASE SWITCHING PATTERN SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 11 MAX9226 SUPPLY CURRENT vs. FREQUENCY MAX9226 SUPPLY CURRENT vs. FREQUENCY MAX9226 toc12 MAX9226 SUPPLY CURRENT vs. SUPPLY VOLTAGE 140 120 100 30 0 80 0 0.2 0.4 0.6 SINK CURRENT (mA) 0.8 1.0 2.3 2.5 2.7 2.9 3.1 3.3 3.5 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 7 MAX9225/MAX9226 Typical Operating Characteristics (continued) (VDD = VDDO = +2.8V, logic input levels = 0 to +2.8V, logic output load CL = 5pF, TA = +25°C, unless otherwise noted.) 10-Bit, Low-Power, 10MHz-to-20MHz Serializer and Deserializer Chipset MAX9225/MAX9226 Pin Description (MAX9225) PIN 1–7, 14, 15, 16 NAME FUNCTION DIN6–DIN0, Single-Ended Parallel Data Inputs. The 10 data bits are loaded into the input latch on the rising DIN9, DIN8, DIN7 edge of PCLKIN. 1.71V to 3.465V tolerant. Internally pulled down to GND. 8 PCLKIN Parallel Clock Input. The rising edge of PCLKIN (typically the pixel clock) latches the parallel data input. Internally pulled down to GND. 9 PWRDN Power-Down Input. Pull PWRDN low to place the MAX9225/MAX9226 in power-down mode. Drive PWRDN high for normal operation. Internally pulled down to GND. 10 SDO- 11 SDO+ Inverting LCDS Serial-Data Output Noninverting LCDS Serial-Data Output 12 GND Ground 13 VDD Core Supply Voltage. Bypass to GND with 0.1µF and 0.01µF capacitors in parallel as close to the device as possible with the smallest value capacitor closest to the supply pin. — EP Exposed Paddle. Connect EP to ground. Pin Description (MAX9226) PIN 8 NAME FUNCTION 1 GND 2 SDI+ Noninverting LCDS Serial-Data Input 3 SDI- Inverting LCDS Serial-Data Input 4 VDD Core Supply Voltage. Bypass to GND with 0.1µF and 0.01µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. 5 PCLKOUT Parallel Clock Output. Parallel output data are valid on the rising edge of PCLKOUT (typically the pixel clock). 6–15 DOUT0–DOUT9 16 VDDO — EP Ground Single-Ended Parallel Data Output. DOUT[9:0] are valid on the rising edge of PCLKOUT. Output Supply Voltage. Bypass to GND with 0.1µF and 0.01µF capacitors in parallel as close to the device as possible with the smallest value capacitor closest to the supply pin. Exposed Paddle. Connect EP to ground. _______________________________________________________________________________________ 10-Bit, Low-Power, 10MHz-to-20MHz Serializer and Deserializer Chipset PARALLEL TO SERIAL INPUT LATCH DIN[9:0] Functional Diagram (MAX9226) SDO+ SDI+ SDO- SDI- SERIAL TO PARALLEL OUTPUT LATCH DOUT[9:0] TIMING AND CONTROL PCLKIN PWRDN TIMING AND CONTROL PCLKOUT DLL MAX9225 MAX9226 Detailed Description The MAX9225 serializer operates at a 10MHz-to-20MHz parallel clock frequency, serializing 10 bits of parallel input data DIN[9:0] in each cycle of the parallel clock. DIN[9:0] are latched on the rising edge of PCLKIN. The data and internally generated serial clock are combined and transmitted through SDO+/SDO- using multilevel LCDS. The MAX9226 deserializer receives the LCDS signal on SDI+/SDI-. The deserialized data and recovered parallel clock are available at DOUT[9:0] and PCLKOUT. Output data is valid on the rising edge of PCLKOUT. Bit 0 (DIN[0]) is transmitted first. Boundary bits OH1 and OH2 are used by the MAX9226 deserializer to identify the word boundary. OH1 is the inverse polarity of data bit 9 (DIN[9]), and OH2 is the inverse polarity of OH1. Therefore, at least two level transitions are guaranteed in one word. The clock is recovered from the serial input. Serial word format: 0 1 2 3 4 5 6 7 8 9 OH1 OH2 LCDS The MAX9225/MAX9226 use a proprietary multilevel LCDS interface. Figure 5 provides a representation of the data and clock in the multilevel LCDS interface. This interface offers advantages over other chipsets, such as requiring only one differential pair as the transmission medium, the inherently aligned data and clock, and much smaller current levels than the 4mA typically found in traditional LVDS interfaces. MAX9225/MAX9226 Handshaking The handshaking function of the MAX9225/MAX9226 provides bidirectional communication between the two devices in case a word boundary error is detected. Prior to data transmission, the MAX9225 serializer adds boundary bits (OH) to the end of the latched word. These boundary bits are the inverse of the last bit of the latched word. During data transmission, the MAX9226 deserializer continuously monitors the state of the boundary bits of each word. If a word boundary error is detected, the serial link is pulled up to VDD and the MAX9226 powers down. The MAX9225 detects the pullup of the serial link and powers down for 1.0µs. After 1.0µs, the MAX9225 powers up, causing the power-up of the MAX9226. Then the word boundary is reestablished, and data transfer resumes. The handshaking function is disabled when PWRDN is pulled low. _______________________________________________________________________________________ 9 MAX9225/MAX9226 Functional Diagram (MAX9225) MAX9225/MAX9226 10-Bit, Low-Power, 10MHz-to-20MHz Serializer and Deserializer Chipset PARALLEL DATA INPUT PCLK IN DIN[9:0] DIN EXAMPLE INPUT 0 1 2 3 4 5 6 7 8 9 1 1 0 1 0 0 1 0 1 1 LCDS SERIAL-DATA OUTPUT FOR EXAMPLE INPUT (SD0+/SDO-) 1 1 0 1 0 0 1 0 1 1 OH1 OH2 NOTE: OH1 AND OH2 ARE OPPOSITE POLARITY. Figure 5. Multilevel LCDS Output Representation Applications Information PCLKIN Latch Edge The parallel data input of the MAX9225 serializer is latched on the rising edge of PCLKIN. Figure 3 shows the serializer input timing. PCLKOUT Strobe The serial-data output of the MAX9226 deserializer is valid on the rising edge of PCLKOUT. Figure 4 shows the deserializer output timing. Power-Down and Power-Up Driving PWRDN low puts the MAX9225 in power-down mode and sends a pulse to power down the MAX9226. In power-down mode, the DLL is stopped, SDO+/SDOare high impedance to ground and differential, and the LCDS link is weakly biased around (VDD - 0.8V). With PWRDN and all inputs low, the combined MAX9225/ MAX9226 supply current is reduced to 3.5µA or less. Driving PWRDN high starts DLL lock to PCLKIN and initiates a MAX9226 power-up sequence. The MAX9225 10 LCDS output is not driven until the DLL locks. 11,264 clock cycles are required for the power-up and link synchronization before valid DIN can be latched. See Figure 6 for an overall power-up and power-down timing diagram. For normal operation, PCLKIN must be running and settled before driving PWRDN high. If VDD = 0, the LCDS outputs are high impedance to ground and differential. Ground-Shift Tolerance The MAX9225/MAX9226 are designed to function normally in the event of a slight shift in ground potential. However, the MAX9226 deserializer ground must be within ±0.2V relative to the MAX9225 serializer ground to maintain proper operation. MAX9226 Output Buffer Supply (VDDO) The MAX9226 parallel outputs are powered from VDDO, which accepts a +1.71V to +3.465V supply, allowing direct interface to inputs with 1.8V to 3.3V logic levels. ______________________________________________________________________________________ 10-Bit, Low-Power, 10MHz-to-20MHz Serializer and Deserializer Chipset POWERDOWN DATA TRANSFER MAX9225/MAX9226 POWER-UP AND LINK SYNCHRONIZATION IN POWERDOWN IN POWERDOWN tPWRDN PWRDN 1 2 tPU2 PCLKIN DIN_ DON'T CARE 1 LOW DON'T CARE N 1 LOW N DOUT_ PCLKOUT HIGH HIGH Figure 6. MAX9225/MAX9226 Power-Up/Power-Down Sequence Flex Cable, PCB Interconnect, and Connectors Interconnect for LCDS typically has a differential impedance of 100Ω. Use interconnect and connectors that have matched differential impedance to minimize impedance discontinuities. Board Layout and Supply Bypassing Separate the LVTTL/LVCMOS and LCDS signals to prevent crosstalk. A PCB or flex with separate layers for power, ground, and signals is recommended. Bypass each VDD and VDDO pin with high-frequency, surface-mount ceramic 0.1µF and 0.01µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. ESD Protection 1MΩ CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 100pF RD 1.5kΩ DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST Figure 7. Human Body Model ESD Test Circuit Chip Information PROCESS: CMOS The MAX9225/MAX9226 are rated for ±15kV ESD protection using the Human Body Model. The Human Body Model discharge components are CS = 100pF and RD = 1.5kΩ (Figure 7). ______________________________________________________________________________________ 11 MAX9225/MAX9226 10-Bit, Low-Power, 10MHz-to-20MHz Serializer and Deserializer Chipset Pin Configurations GND SDO+ SDO- PWRDN DOUT6 DOUT5 DOUT4 DOUT3 TOP VIEW 12 11 10 9 12 11 10 9 DIN8 15 DOUT8 14 DOUT9 15 5 DIN2 VDDO 16 3 4 1 GND DIN1 DIN3 6 MAX9226 2 TQFN-EP 12 DIN0 DIN4 DIN6 1 7 DIN5 DIN7 16 DOUT7 13 2 3 4 VDD MAX9225 PCLKIN SDI- DIN9 14 8 SDI+ VDD 13 8 DOUT2 7 DOUT1 6 DOUT0 5 PCLKOUT TQFN-EP ______________________________________________________________________________________ 10-Bit, Low-Power, 10MHz-to-20MHz Serializer and Deserializer Chipset 12x16L QFN THIN.EPS (NE - 1) X e E MARKING E/2 D2/2 (ND - 1) X e D/2 AAAA e CL D D2 k CL b 0.10 M C A B E2/2 L E2 0.10 C C L C L 0.08 C A A2 A1 L L e e PACKAGE OUTLINE 8, 12, 16L THIN QFN, 3x3x0.8mm 21-0136 I 1 2 ______________________________________________________________________________________ 13 MAX9225/MAX9226 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) MAX9225/MAX9226 10-Bit, Low-Power, 10MHz-to-20MHz Serializer and Deserializer Chipset Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) PKG 8L 3x3 12L 3x3 16L 3x3 REF. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. A 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 b 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 D 2.90 3.00 3.10 2.90 3.00 3.10 2.90 3.00 3.10 E 2.90 3.00 3.10 2.90 3.00 3.10 2.90 3.00 3.10 0.75 0.45 0.65 0.30 e L 0.65 BSC. 0.35 0.55 0.50 BSC. 0.50 BSC. 0.55 0.40 N 8 12 16 ND 2 3 4 NE 2 3 4 0 A1 A2 k 0.02 0.05 0 0.20 REF 0.25 - 0.02 0.05 0 0.25 - 0.02 0.50 0.05 0.20 REF 0.20 REF - EXPOSED PAD VARIATIONS - 0.25 - PKG. CODES D2 E2 PIN ID JEDEC MIN. NOM. MAX. MIN. NOM. MAX. TQ833-1 0.25 0.70 1.25 0.25 0.70 1.25 0.35 x 45° T1233-1 0.95 1.10 1.25 0.95 1.10 1.25 0.35 x 45° WEED-1 T1233-3 0.95 1.10 1.25 0.95 1.10 1.25 0.35 x 45° WEED-1 WEEC T1233-4 0.95 1.10 1.25 0.95 1.10 1.25 0.35 x 45° WEED-1 T1633-2 0.95 1.10 1.25 0.95 1.10 1.25 0.35 x 45° WEED-2 T1633F-3 0.65 0.80 0.95 0.65 0.80 0.95 0.225 x 45° WEED-2 T1633FH-3 0.65 0.80 0.95 0.65 0.80 0.95 0.225 x 45° WEED-2 T1633-4 0.95 1.10 1.25 0.95 1.10 1.25 0.35 x 45° WEED-2 T1633-5 0.95 1.10 1.25 0.95 1.10 1.25 0.35 x 45° WEED-2 - NOTES: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. N IS THE TOTAL NUMBER OF TERMINALS. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm FROM TERMINAL TIP. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS . DRAWING CONFORMS TO JEDEC MO220 REVISION C. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. WARPAGE NOT TO EXCEED 0.10mm. PACKAGE OUTLINE 8, 12, 16L THIN QFN, 3x3x0.8mm 21-0136 14 ______________________________________________________________________________________ I 2 2 10-Bit, Low-Power, 10MHz-to-20MHz Serializer and Deserializer Chipset REVISION NUMBER REVISION DATE 0 1/06 Initial release 1 12/07 Changed max output short-circuit current from -20 to -25 in EC table; various style changes. DESCRIPTION PAGES CHANGED — 2, 3, 11 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 © 2007 Maxim Integrated Products Springer is a registered trademark of Maxim Integrated Products, Inc. MAX9225/MAX9226 Revision History