19-3955; Rev 0; 1/06 27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer Applications Navigation System Displays In-Vehicle Entertainment Systems Video Cameras LCDs Features ♦ Preemphasis Improves Eye Diagram and Signal Integrity at the Output ♦ Proprietary Data Encoding for DC Balance and Reduced EMI ♦ Control Data Sent During Video Blanking ♦ Five Control Data Inputs are Single-Bit-Error Tolerant ♦ Programmable Phase-Shifted LVDS Signaling Reduces EMI ♦ Output Common-Mode Filter Reduces EMI ♦ Greater Than 10m STP Cable Drive ♦ Wide ±2% Reference Clock Tolerance ♦ ISO 10605 and IEC 61000-4-2 Level 4 ESD Protection ♦ Separate Input Supply Allows Interface to 1.8V to 3.3V Logic ♦ +3.3V Core Supply ♦ Space-Saving TQFP and TQFN Packages ♦ -40°C to +85°C Operating Temperature Range Ordering Information PART TEMP RANGE PINPACKAGE MAX9247ECM+ -40°C to +85°C 48 TQFP MAX9247ETM+* -40°C to +85°C 48 TQFN-EP** PKG CODE C48-5 T4866-1 *Future part—contact factory for availability. **EP = Exposed pad. +Denotes lead-free package. 34 4 33 5 32 6 31 RGB_IN17 CNTL_IN0 CNTL_IN1 30 VCCLVDS OUT+ OUTLVDSGND LVDSGND 24 PCLK_IN I.C. CNTL_IN6 CNTL_IN7 CNTL_IN8 DE_IN CNTL_IN2 CNTL_IN3 CNTL_IN4 CNTL_IN5 GND VCC TQFP 23 25 22 12 PLLGND PRE 21 26 20 11 19 VCCPLL 18 27 17 10 16 CMF PWRDWN 15 28 14 29 9 13 8 PLLGND PRE GND VCC RGB_IN0 RGB_IN1 RGB_IN2 RGB_IN3 RGB_IN4 RGB_IN5 RGB_IN6 37 24 38 23 39 22 40 21 41 20 RGB_IN7 RGB_IN8 RGB_IN9 I.C. PCLK_IN DE_IN CNTL_IN8 CNTL_IN7 44 17 45 16 46 15 47 14 CNTL_IN6 CNTL_IN5 CNTL_IN4 CNTL_IN3 CNTL_IN2 VCC 13 GND 19 42 MAX9247 43 18 48 1 2 3 4 5 6 7 8 9 10 11 12 RGB_IN17 CNTL_IN0 CNTL_IN1 3 RNG0 RNG1 RGB_IN13 RGB_IN14 RGB_IN15 RGB_IN16 35 RGB_IN10 RGB_IN11 RGB_IN12 36 2 GND VCCIN 1 MAX9247 LVDSGND CMF PWRDWN VCCPLL 36 35 34 33 32 31 30 29 28 27 26 25 GND VCCIN RGB_IN10 RGB_IN11 RGB_IN12 RGB_IN13 RGB_IN14 RGB_IN15 RGB_IN16 7 VCCLVDS OUT+ OUTLVDSGND RNG0 RNG1 37 38 RGB_IN1 RGB_IN0 VCC GND 39 40 41 42 RGB_IN5 RGB_IN4 RGB_IN3 RGB_IN2 43 44 45 46 RGB_IN9 RGB_IN8 RGB_IN7 RGB_IN6 47 TOP VIEW 48 Pin Configurations TQFN-EP ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9247 General Description The MAX9247 digital video parallel-to-serial converter serializes 27 bits of parallel data into a serial-data stream. Eighteen bits of video data and 9 bits of control data are encoded and multiplexed onto the serial interface, reducing the serial-data rate. The data-enable input determines when the video or control data is serialized. The MAX9247 pairs with the MAX9248/MAX9250 deserializers to form a complete digital video serial link. Interconnect can be controlled-impedance PC board traces or twisted-pair cable. Proprietary data encoding reduces EMI and provides DC balance. DC balance allows AC-coupling, providing isolation between the transmitting and receiving ends of the interface. The LVDS output is internally terminated with 100Ω. For operating frequencies less than 35MHz, the MAX9247 can also pair with the MAX9218 deserializer. ESD tolerance is specified for ISO 10605 with ±10kV Contact Discharge and ±30kV Air-Gap Discharge. The MAX9247 operates from a +3.3V core supply and features a separate input supply for interfacing to 1.8V to 3.3V logic levels. This device is available in 48-lead TQFP and TQFN packages and is specified from -40°C to +85°C. MAX9247 27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer ABSOLUTE MAXIMUM RATINGS VCC_ to _GND........................................................-0.5V to +4.0V Any Ground to Any Ground...................................-0.5V to +0.5V OUT+, OUT- to LVDSGND ....................................-0.5V to +4.0V OUT+, OUT- Short Circuit to LVDSGND or VCCLVDS .............................................................Continuous OUT+, OUT- Short Through 0.125µF (or smaller), 25V Series Capacitor..........................................-0.5V to +16V RGB_IN[17:0], CNTL_IN[8:0], DE_IN, RNG0, RNG1, PRE, PCLK_IN, PWRDWN, CMF to GND......................-0.5V to (VCCIN + 0.5V) Continuous Power Dissipation (TA = +70°C) 48-Lead TQFP (derate 20.8mW/°C above +70°C) ....1667mW 48-Lead TQFN (derate 37mW/°C above +70°C) .......2963mW ESD Protection Human Body Model (RD = 1.5kΩ, CS = 100pF) All Pins to GND.................................................................±3kV ISO 10605 (RD = 2kΩ, CS = 330pF) Contact Discharge (OUT+, OUT-) to GND.....................±10kV Air-Gap Discharge (OUT+, OUT-) to GND.....................±30kV IEC 61000-4-2 (RD = 330Ω, CS = 150pF) Contact Discharge (OUT+, OUT-) to GND.......................±8kV Air-Gap Discharge (OUT+, OUT-) to GND.....................±15kV Storage Temperature Range .............................-65°C to +150°C Junction Temperature ......................................................+150°C Lead Temperature (soldering, 10s)..................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC_ = +3.0V to +3.6V, RL = 100Ω ±1%, PWRDWN = high, PRE = low, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC_ = +3.3V, TA = +25°C.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SINGLE-ENDED INPUTS (RGB_IN[17:0], CNTL_IN[8:0], DE_IN, PCLK_IN, PWRDWN, RNG_, PRE) VCCIN = 1.71V to < 3V (Note 3) 0.65 x VCCIN VCCIN + 0.3 2 0.3 + VCCIN VCCIN = 1.71V to < 3V (Note 3) -0.3 0.3 x VCCIN VCCIN = 3.0V to 3.6V -0.3 +0.8 VIN = -0.3V to 0 -100 +20 VIN = 0 to (VCCIN + 0.3V) -20 +20 High-Level Input Voltage VIH Low-Level Input Voltage VIL Input Current IIN VCCIN = 1.71V to 3.6V, PWRDWN = high or low Input Clamp Voltage VCL ICL = -18mA VOD Figure 1 ∆VOD Figure 1 VOS Figure 1 ∆VOS Figure 1 VCCIN = 3.0V to 3.6V V V µA -1.5 V 450 mV 20 mV 1.475 V 20 mV ±8 +15 mA 5.5 15 mA +1 µA LVDS OUTPUTS (OUT+, OUT-) Differential Output Voltage Change in VOD Between Complementary Output States Common-Mode Voltage Change in VOS Between Complementary Output States Output Short-Circuit Current IOS Magnitude of Differential Output Short-Circuit Current IOSD Output High-Impedance Current 2 IOZ 250 1.125 VOUT+ or VOUT- = 0 or 3.6V -15 VOD = 0 PWRDWN = low or VCC_ = 0 OUT+ = 0, OUT- = 3.6V 335 1.29 -1 OUT+ = 3.6V, OUT- = 0 _______________________________________________________________________________________ 27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer (VCC_ = +3.0V to +3.6V, RL = 100Ω ±1%, PWRDWN = high, PRE = low, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC_ = +3.3V, TA = +25°C.) (Notes 1, 2) PARAMETER SYMBOL Differential Output Resistance CONDITIONS RO 2.5MHz ICCW RL = 100Ω ±1%, CL = 5pF, continuous 10 transition words UNITS 78 110 147 Ω 15 25 PRE = 0 PRE = 1 27 18 25 23 28 33 39 50 65 27 PRE = 0 10MHz PRE = 1 30 PRE = 0 20MHz PRE = 1 mA 42 PRE = 0 PRE = 1 69 PRE = 0 42MHz ICCZ MAX PRE = 1 35MHz Power-Down Supply Current TYP PRE = 0 5MHz Worst-Case Supply Current MIN 60 PRE = 1 70 75 50 (Note 4) µA AC ELECTRICAL CHARACTERISTICS (VCC_ = +3.0V to +3.6V, RL = 100Ω ±1%, CL = 5pF, PWRDWN = high, PRE = low, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC_ = +3.3V, TA = +25°C.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PCLK_IN TIMING REQUIREMENTS Clock Period tT Clock Frequency Clock Frequency Difference from Deserializer Reference Clock Clock Duty Cycle 23.8 400.0 ns fCLK 2.5 42.0 MHz ∆fCLK -2 +2 % DC Clock Transition Time Figure 2 tHIGH/tT or tLOW/tT, Figure 2 35 50 65 % 2.5 ns tR, tF Figure 2 Output Rise Time tRISE 20% to 80%, VOD ≥ 250mV, Figure 3 PRE = low 280 370 PRE = high 240 320 Output Fall Time tFALL 80% to 20%, VOD ≥ 250mV, Figure 3 PRE = low 280 370 PRE = high 240 320 Input Setup Time tSET Figure 4 3 ns Input Hold Time tHOLD Figure 4 3 ns SWITCHING CHARACTERISTICS ps ps _______________________________________________________________________________________ 3 MAX9247 DC ELECTRICAL CHARACTERISTICS (continued) MAX9247 27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer AC ELECTRICAL CHARACTERISTICS (continued) (VCC_ = +3.0V to +3.6V, RL = 100Ω ±1%, CL = 5pF, PWRDWN = high, PRE = low, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC_ = +3.3V, TA = +25°C.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP 3.10 x tT + 2.0 MAX UNITS 3.10 x tT + 8.0 ns Serializer Delay tSD Figure 5 PLL Lock Time tLOCK Figure 6 17,100 x tT ns Power-Down Delay tPD Figure 7 1 µs Peak-to-Peak Output Jitter tJITT Measured with PRBS input pattern at 840Mbps data rate 150 ps Peak-to-Peak Output Offset Voltage VOS(P-P) 840Mbps data rate, CMF open, Figure 8 22 70 840Mbps data rate, CMF 0.1µF to ground, Figure 8 12 50 mV Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground, except VOD, ∆VOD, and ∆VOS. Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production tested at TA = +25°C. Note 3: Parameters are guaranteed by design and characterization and are not production tested. Limits are set at ±6 sigma. Note 4: All LVTTL/LVCMOS inputs, except PWRDWN at ≤ 0.3V or ≥ VCCIN - 0.3V. PWRDWN is ≤ 0.3V. 4 _______________________________________________________________________________________ 27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer WORST-CASE PATTERN SUPPLY CURRENT vs. FREQUENCY 50 2 METER CAT5 CABLE 100Ω TERMINATION 2 METER CAT5 CABLE 100Ω TERMINATION PRE = LOW REFCLK = 42MHz WITH PREEMPHASIS MAX9247 toc03 PRE = HIGH REFCLK = 42MHz GND 40 100mV/div 100mV/div 30 GND WITHOUT PREEMPHASIS 20 10 0 10 20 30 200ps/div 200ps/div 40 FREQUENCY (MHz) CABLE LENGTH vs. FREQUENCY BIT-ERROR RATE < 10E-9 BIT-ERROR RATE vs. CABLE LENGTH CATS CABLE 45 MAX9247 toc05 1.00E-14 MAX9247 toc04 40 35 1.00E-13 FREQUENCY (MHz) 0 BIT-ERROR RATE SUPPLY CURRENT (mA) 60 MAX9247 toc02 MAX9247 toc01 70 EYE DIAGRAM WITH PREEMPHASIS EYE DIAGRAM WITHOUT PREEMPHASIS 1.00E-12 REFCLK = 42MHz 840Mbps DATA RATE FOR CABLE LENGTH < 10m BER < 1012 1.00E-11 30 25 20 15 10 5 1.00E-10 0 2 4 6 8 CAT5 CABLE LENGTH (m) 10 12 0 2 4 6 8 10 12 14 16 18 20 CABLE LENGTH (m) _______________________________________________________________________________________ 5 MAX9247 Typical Operating Characteristics (VCC_ = +3.3V, RL = 100Ω, TA = +25°C, unless otherwise noted.) 27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer MAX9247 Pin Description 6 PIN NAME FUNCTION 1, 13, 37 GND Input Buffer Supply and Digital Supply Ground 2 VCCIN Input Buffer Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. 3–10, 39–48 RGB_IN10– RGB_IN17, RGB_IN0– RGB_IN9 LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Inputs. Eighteen data bits are loaded into the input latch on the rising edge of PCLK_IN when DE_IN is high. Internally pulled down to GND. 11, 12, 15–21 CNTL_IN0, CNTL_IN1, CNTL_IN2– CNTL_IN8 LVTTL/LVCMOS Control Data Inputs. Control data are latched on the rising edge of PCLK_IN when DE_IN is low. Internally pulled down to GND. 14, 38 VCC 22 DE_IN 23 PCLK_IN Digital Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. LVTTL/LVCMOS Data-Enable Input. Logic-high selects RGB_IN[17:0] to be latched. Logic-low selects CNTL_IN[8:0] to be latched. DE_IN must be switching for proper operation. Internally pulled down to GND. LVTTL/LVCMOS Parallel Clock Input. Latches data and control inputs and provides the PLL reference clock. Internally pulled down to GND. 24 I.C. Internally Connected. Leave floating for normal operation. 25 PRE Preemphasis Enable Input. Drive PRE high to enable preemphasis. 26 PLLGND PLL Supply Ground 27 VCCPLL PLL Supply Voltage. Bypass to PLLGND with 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. 28 PWRDWN 29 CMF 30, 31 LVDSGND 32 OUT- 33 OUT+ LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND. Common-Mode Filter. Optionally connect a capacitor between CMF and ground to filter common-mode switching noise. LVDS Supply Ground Inverting LVDS Serial-Data Output Noninverting LVDS Serial-Data Output 34 VCCLVDS LVDS Supply Voltage. Bypass to LVDSGND with 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. 35 RNG1 LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the PCLK_IN frequency as shown in Table 3. Internally pulled down to GND. 36 RNG0 LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the PCLK_IN frequency as shown in Table 3. Internally pulled down to GND. EP GND Exposed Pad (TQFN Package Only). Connect to GND. _______________________________________________________________________________________ 27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer PRE RGB_IN 1 INPUT LATCH CNTL_IN 0 OUT+ DC BALANCE/ ENCODE PAR-TO-SER OUTCMF DE_IN PCLK_IN RNG0 RNG1 PLL TIMING AND CONTROL MAX9247 PWRDWN RL / 2 OUT+ VOD OUT- VOS RL / 2 GND ((OUT+) + (OUT-)) / 2 OUTVOS(-) VOS(+) VOS(-) OUT+ ∆VOS = |VOS(+) - VOS(-)| VOD(+) VOD = 0V VOD(-) ∆VOD = |VOD(+) - VOD(-)| VOD(-) (OUT+) - (OUT-) Figure 1. LVDS DC Output Load and Parameters _______________________________________________________________________________________ 7 MAX9247 Functional Diagram MAX9247 27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer tT VIHmin tHIGH PCLK_IN VILmax tR tF tLOW Figure 2. Parallel Clock Requirements OUT+ RL OUTCL CL 80% 80% 20% 20% (OUT+) - (OUT-) tFALL tRISE Figure 3. Output Rise and Fall Times VIHmin PCLK_IN VILmax tSET tHOLD RGB_IN[17:0] VIHmin VIHmin VILmax VILmax CNTL_IN[8:0] DE_IN Figure 4. Synchronous Input Timing 8 _______________________________________________________________________________________ 27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer MAX9247 EXPANDED TIME SCALE RGB_IN CNTL_IN N N+1 N+3 N+2 N+4 PCLK_IN N-1 N OUT_ tSD BIT 0 BIT 19 Figure 5. Serializer Delay VILmax PWRDWN tLOCK VOD = 0V HIGH IMPEDANCE (OUT+) - (OUT-) PCLK_IN Figure 6. PLL Lock Time PWRDWN VILmax tPD (OUT+) - (OUT-) HIGH IMPEDANCE PCLK_IN Figure 7. Power-Down Delay _______________________________________________________________________________________ 9 MAX9247 27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer OUT- OUT+ ((OUT+) + (OUT-)) / 2 VOS(P-P) VOS(P-P) Figure 8. Peak-to-Peak Output Offset Voltage Detailed Description The MAX9247 DC-balanced serializer operates at a 2.5MHz-to-42MHz parallel clock frequency, serializing 18 bits of parallel video data RGB_IN[17:0] when the data-enable input DE_IN is high, or 9 bits of parallel control data CNTL_IN[8:0] when DE_IN is low. The RGB video input data are encoded using 2 overhead bits, EN0 and EN1, resulting in a serial word length of 20 bits (see Table 1). Control inputs are mapped to 19 bits and encoded with 1 overhead bit, EN0, also resulting in a 20-bit serial word. Encoding reduces EMI and maintains DC balance across the serial cable. Two transition words, which contain a unique bit sequence, are inserted at the transition boundaries of video-tocontrol and control-to-video phases. Control data inputs C0 to C4 are mapped to 3 bits each in the serial control word (see Table 2). At the deserializer, 2 or 3 bits at the same state determine the state of the recovered bit, providing single-bit-error tolerance for C0 to C4. Control data that may be visible if an error occurs, such as VSYNC and HSYNC, can be connected to these inputs. Control data inputs C5 to C8 are mapped to 1 bit each. Table 1. Serial Video Phase Word Format 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 EN0 EN1 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 Bit 0 is the LSB and is serialized first. EN[1:0] are encoding bits. S[17:0] are encoded symbols. Table 2. Serial Control Phase Word Format 0 EN0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 C0 C0 C0 C1 C1 C1 C2 C2 C2 C3 C3 C3 C4 C4 C4 C5 C6 C7 C8 Bit 0 is the LSB and is serialized first. C[8:0] are the control inputs. 10 ______________________________________________________________________________________ 27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer TRANSITION PHASE TRANSITION PHASE VIDEO PHASE MAX9247 CONTROL PHASE CONTROL PHASE PCLK_IN CNTL_IN DE_IN RGB_IN = NOT SAMPLED BY PCLK_IN Figure 9. Transition Timing Transition Timing The transition words require interconnect bandwidth and displace control data. Therefore, control data is not sampled (see Figure 9): • Two clock cycles before DE_IN goes high • During the video phase • Two clock cycles after DE_IN goes low The last sampled control data are latched at the deserializer control data outputs during the transition and video phases. Video data are latched at the deserializer RGB data outputs during the transition and control phases. Applications Information AC-Coupling Benefits AC-coupling increases the common-mode voltage to the voltage rating of the capacitor. Two capacitors are sufficient for isolation, but four capacitors—two at the serializer output and two at the deserializer input—provide protection if either end of the cable is shorted to a high voltage. AC-coupling blocks low-frequency ground shifts and common-mode noise. The MAX9247 serializer can also be DC-coupled to the MAX9248/ MAX9250 deserializers. Figures 10 and 12 show an AC-coupled serializer and deserializer with two capacitors per link. Figures 11 and 13 show the AC-coupled serializer and deserializer with four capacitors per link. Selection of AC-Coupling Capacitors See Figure 14 for calculating the capacitor values for AC-coupling depending on the parallel clock frequency. The plot shows capacitor values for two- and fourcapacitor-per-link systems. For applications using less than 18MHz clock frequency, use 0.125µF capacitors. Frequency-Range Setting RNG[1:0] The RNG[1:0] inputs select the operating frequency range of the MAX9247 serializer. An external clock within this range is required for operation. Table 3 shows the selectable frequency ranges and corresponding data rates for the MAX9247. Table 3. Parallel Clock Frequency Range Select RNG1 RNG0 PARALLEL CLOCK (MHz) SERIAL-DATA RATE (Mbps) 0 0 2.5 to 5 50 to 100 0 1 5 to10 100 to 200 1 0 10 to 20 200 to 400 1 1 20 to 42 400 to 840 ______________________________________________________________________________________ 11 MAX9247 27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer VCC CMF IN * 82Ω SER-TO-PAR OUT DC BALANCE/ DECODE 0 130Ω 130Ω * PAR-TO-SER CNTL_IN 1 INPUT LATCH RGB_IN DC BALANCE/ ENCODE PRE R/F OUTEN RGB_OUT 1 CNTL_OUT 0 DE_OUT 82Ω DE_IN PCLK_OUT RNG0 PCLK_IN RNG0 RNG1 PLL PLL RNG1 TIMING AND CONTROL REF_IN PWRDWN TIMING AND CONTROL PWRDWN LOCK MAX9247 MAX9250 CERAMIC RF SURFACE-MOUNT CAPACITOR 100Ω DIFFERENTIAL STP CABLE *CAPACITORS CAN BE AT EITHER END. Figure 10. AC-Coupled MAX9247 Serializer and MAX9250 Deserializer with Two Capacitors per Link VCC 130Ω IN OUT CMF 82Ω SER-TO-PAR 130Ω DC BALANCE/ DECODE 0 PAR-TO-SER CNTL_IN 1 INPUT LATCH RGB_IN DC BALANCE/ ENCODE PRE 82Ω 1 0 R/F OUTEN RGB_OUT CNTL_OUT DE_OUT DE_IN RNG0 PCLK_IN RNG0 RNG1 PLL TIMING AND CONTROL RNG1 PCLK_OUT PLL REF_IN PWRDWN TIMING AND CONTROL PWRDWN MAX9247 CERAMIC RF SURFACE-MOUNT CAPACITOR LOCK MAX9250 100Ω DIFFERENTIAL STP CABLE Figure 11. AC-Coupled MAX9247 Serializer and MAX9250 Deserializer with Four Capacitors per Link 12 ______________________________________________________________________________________ 27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer CMF IN- 82Ω 1 RGB_OUT 0 FIFO * SER-TO-PAR OUT R/F IN+ DC BALANCE/ DECODE 0 130Ω 130Ω * PAR-TO-SER CNTL_IN 1 DC BALANCE/ ENCODE RGB_IN INPUT LATCH PRE CNTL_OUT DE_OUT 82Ω DE_IN PCLK_OUT REFCLK PCLK_IN RNG0 RNG1 PLL PLL SSPLL TIMING AND CONTROL SS PWRDWN TIMING AND CONTROL PWRDWN LOCK MAX9247 MAX9248 RNG[0:1] CERAMIC RF SURFACE-MOUNT CAPACITOR 100Ω DIFFERENTIAL STP CABLE *CAPACITORS CAN BE AT EITHER END. Figure 12. AC-Coupled MAX9247 Serializer and MAX9248 Deserializer with Two Capacitors per Link VCC 130Ω R/F OUT CMF IN82Ω 1 RGB_OUT 0 FIFO IN+ SER-TO-PAR 130Ω DC BALANCE/ DECODE 0 PAR-TO-SER CNTL_IN 1 DC BALANCE/ ENCODE RGB_IN INPUT LATCH PRE DE_OUT 82Ω DE_IN PCLK_IN RNG0 RNG1 CNTL_OUT PCLK_OUT REFCLK PLL PLL SSPLL TIMING AND CONTROL PWRDWN TIMING AND CONTROL PWRDWN SS LOCK MAX9247 MAX9248 RNG[0:1] CERAMIC RF SURFACE-MOUNT CAPACITOR 100Ω DIFFERENTIAL STP CABLE Figure 13. AC-Coupled MAX9247 Serializer and MAX9248 Deserializer with Four Capacitors per Link ______________________________________________________________________________________ 13 MAX9247 VCC 27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer MAX9247 LVDS Output Preemphasis (PRE) The MAX9247 features a preemphasis mode where extra current is added to the output and causes the amplitude to increase by 40% to 50% at the transition point. Preemphasis helps to get a faster transition, better eye diagram, and improve signal integrity. See the Typical Operating Characteristics. The additional current is turned on for a short time (360ps, typ) during data transition, and then turned off. Enable preemphasis by driving PRE high. AC-COUPLING CAPACITOR VALUE vs. PARALLEL CLOCK FREQUENCY 140 CAPACITOR VALUE (pF) 120 100 FOUR CAPACITORS PER LINK 80 60 Power-Down and Power-Off 40 20 TWO CAPACITORS PER LINK 0 18 21 24 27 30 33 36 39 42 PARALLEL CLOCK FREQUENCY (MHz) Figure 14. AC-Coupling Capacitor Values vs. Clock Frequency of 18MHz to 42MHz Termination The MAX9247 has an integrated 100Ω output-termination resistor. This resistor damps reflections from induced noise and mismatches between the transmission line impedance and termination resistors at the deserializer input. With PWRDWN = low or with the supply off, the output termination is switched out and the LVDS output is high impedance. Common-Mode Filter The integrated 100Ω output termination is made up of two 50Ω resistors in series. The junction of the resistors is connected to the CMF pin for connecting an optional common-mode filter capacitor. Connect the filter capacitor to ground close to the MAX9247 as shown in Figure 15. The capacitor shunts common-mode switching current to ground to reduce EMI. Driving PWRDWN low stops the PLL, switches out the integrated 100Ω output termination, and puts the output in high impedance to ground and differential. With PWRDWN ≤ 0.3V and all LVTTL/LVCMOS inputs ≤ 0.3V or ≥ VCCIN - 0.3V, supply current is reduced to 50µA or less. Driving PWRDWN high starts PLL lock to PCLK_IN and switches in the 100Ω output termination resistor. The LVDS output is not driven until the PLL locks. The LVDS output is high impedance to ground and 100Ω differential. The 100Ω integrated termination pulls OUT+ and OUT- together while the PLL is locking so that VOD = 0V. If VCC = 0, the output resistor is switched out and the LVDS outputs are high impedance to ground and differential. PLL Lock Time The PLL lock time is set by an internal counter. The lock time is 17,100 PCLK_IN cycles. Power and clock should be stable to meet the lock-time specification. Input Buffer Supply The single-ended inputs (RGB_IN[17:0], CNTL_IN[8:0], DE_IN, RNG0, RNG1, PRE, PCLK_IN, and PWRDWN) are powered from VCCIN. VCCIN can be connected to a 1.71V to 3.6V supply, allowing logic inputs with a nominal swing of VCCIN. If no power is applied to VCCIN when power is applied to VCC, the inputs are disabled and PWRDWN is internally driven low, putting the device in the power-down state. Power-Supply Circuits and Bypassing OUT+ RO / 2 CMF RO / 2 CCMF OUT- The MAX9247 has isolated on-chip power domains. The digital core supply (VCC) and single-ended input supply (VCCIN) are isolated but have a common ground (GND). The PLL has separate power and ground (VCCPLL and PLLGND) and the LVDS input also has separate power and ground (VCCLVDS and LVDSGND). The grounds are isolated by diode connections. Bypass each VCC, VCCIN, VCCPLL, and VCCLVDS pin with high-frequency, surfacemount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. Figure 15. Common-Mode Filter Capacitor Connection 14 ______________________________________________________________________________________ 27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer Cables and Connectors Interconnect for LVDS typically has a differential impedance of 100Ω. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Twisted-pair and shielded twisted-pair cables offer superior signal quality compared to ribbon cable and tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver. Board Layout Separate the LVTTL/LVCMOS inputs and LVDS output to prevent crosstalk. A four-layer PC board with separate layers for power, ground, and signals is recommended. For IEC 61000-4-2, the LVDS outputs are rated for ±8kV Contact Discharge and ±15kV Air-Gap Discharge. The Human Body Model discharge components are CS = 100pF and RD = 1.5kΩ (Figure 17). For the Human Body Model, all pins are rated for ±3kV Contact Discharge. The ISO 10605 discharge components are CS = 330pF and RD = 2kΩ (Figure 18). For ISO 10605, the LVDS outputs are rated for ±10kV contact and ±30kV air discharge. 1MΩ CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 100pF RD 1.5kΩ DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST ESD Protection The MAX9247 ESD tolerance is rated for IEC 61000-42, Human Body Model and ISO 10605 standards. IEC 61000-4-2 and ISO 10605 specify ESD tolerance for electronic systems. The IEC 61000-4-2 discharge components are CS = 150pF and RD = 330Ω (Figure 16). Figure 17. Human Body ESD Test Circuit 50Ω TO 100Ω CHARGE-CURRENTLIMIT RESISTOR 50Ω TO 100Ω CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 150pF HIGHVOLTAGE DC SOURCE RD 330Ω DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST CS 330pF RD 2kΩ DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST Figure 18. ISO 10605 Contact Discharge ESD Test Circuit Chip Information Figure 16. IEC 61000-4-2 Contact Discharge ESD Test Circuit PROCESS: CMOS ______________________________________________________________________________________ 15 MAX9247 LVDS Output The LVDS output is a current source. The voltage swing is proportional to the termination resistance. The output is rated for a differential load of 100Ω ±1%. Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 32L/48L,TQFP.EPS MAX9247 27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.4mm 21-0054 E 1 2 PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.4mm 21-0054 16 E 2 2 ______________________________________________________________________________________ 27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer 48L THIN QFN.EPS PACKAGE OUTLINE, 48L THIN QFN 6x6x0.8mm BODY / 0.4mm LEAD PITCH A 21-0160 1 2 NOTE : 1. ALL DIMENSIONS ARE IN mm. ANGLES IN DEGREES. 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. COPLANARITY SHALL NOT EXCEED 0.08mm. 3. WARPAGE SHALL NOT EXCEED 0.10 mm. 4. PACKAGE LENGTH / PACKAGE WIDTH ARE CONSIDERED AS SPECIAL CHARACTERISTIC. (S) 5. REFER TO JEDEC MO-220. 6. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 7. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. COMMON DIMENSIONS EXPOSED PAD VARIATONS MIN. NOM. MAX. A 0.700 0.750 0.800 A1 0.000 -- -- 0.050 SYMBOLS A2 D2 E2 PKG. CODE MIN. NOM. MAX. MIN. NOM. MAX. T4866-1 4.20 4.30 4.40 4.20 4.30 4.40 0.200 REF. b 0.150 0.200 0.250 D 5.900 6.000 6.100 e 0.400 TYP. E 5.900 6.000 6.050 k 0.250 0.350 0.450 k1 0.350 0.450 0.550 L 0.400 0.500 0.600 L1 0.300 0.400 0.500 N 48 ND 12 NE 12 PACKAGE OUTLINE, 48L THIN QFN 6x6x0.8mm BODY / 0.4mm LEAD PITCH 21-0160 A 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17 © 2006 Maxim Integrated Products Springer Printed USA is a registered trademark of Maxim Integrated Products, Inc. MAX9247 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)