Order this document from Logic Marketing SEMICONDUCTOR TECHNICAL DATA # # " # ## ! The MC88921 Clock Driver utilizes phase–locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for CISC microprocessor or single processor RISC systems. The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay to multiple locations on a board. The PLL also allows the MC88921 to multiply a low frequency input clock and distribute it locally at a higher (2X) system frequency. LOW SKEW CMOS PLL CLOCK DRIVER With Power–Down/ Power–Up Feature • 2X_Q Output Meets All Requirements of the 20, 25 and 33MHz 68040 Microprocessor PCLK Input Specifications • 60 and 66MHz Output to Drive the Pentium Microprocessor • Four Outputs (Q0–Q3) With Output–Output Skew <500ps and Six Outputs Total (Q0–Q3, 2X_Q) With <1ns Skew Each Being Phase and Frequency Locked to the SYNC Input 20 • The Phase Variation From Part–to–Part Between SYNC and the ‘Q’ 1 Outputs Is Less Than 600ps (Derived From the TPD Specification, Which Defines the Part–to–Part Skew) • SYNC Input Frequency Range From 5MHZ to 2X_Q FMax/4 • Additional Outputs Available at 2X the System ‘Q’ Frequency • All Outputs Have ±36mA Drive (Equal High and Low) CMOS Levels. DW SUFFIX SOIC PACKAGE CASE 751D–04 Can Drive Either CMOS or TTL Inputs. All Inputs Are TTL–Level Compatible • Test Mode Pin (PLL_EN) Provided for Low Frequency Testing • Special Power–Down Mode With 2X_Q, Q0, and Q1 Being Reset (With MR), and Other Outputs Remain Running. 2X_Q, Q0 and Q1 Are Guaranteed to Be in Lock 3 Clock Cycles After MR Is Negated Four ‘Q’ outputs (Q0–Q3) are provided with less than 500ps skew between their rising edges. A 2X_Q output runs at twice the ‘Q’ output frequency. The 2X_Q output is ideal for 68040 systems which require a 2X processor clock input. The 2X_Q output meets the tight duty cycle spec of the 20, 25 and 33MHz 68040. The 66MHz 2X_Q output can also be used for driving the clock input of the Pentium Microprocessor while providing multiple 33MHz outputs to drive the support and bus logic. The FBSEL pin allows the user to internally feedback either the Q or the Q/2 frequency providing a 1x or 2x multiplication factor of the reference input. In normal phase–locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the 88921 in a static ‘test mode’. In this mode there is no frequency limitation on the input clock, which is necessary for a low frequency board test environment. A lock indicator output (LOCK) will go HIGH when the loop is in steady state phase and frequency lock. The output will go LOW if phase–lock is lost or when the PLL_EN pin is LOW. The lock output will go HIGH no later than 10ms after the 88921 sees a sync signal and full 5.0V VCC. Pentium is a trademark of the Intel Corporation. 8/95 Motorola, Inc. 1995 1 REV 2 MC88921 Power–Down Mode Functionality The MC88921 has a special feature designed in to allow the processor clock inputs to be reset for total processor power–down, and then to return to phase–locked operation very quickly when the processor is powered–up again. The MR pin resets outputs 2X_Q, Q0 and Q1 only leaving the other outputs operational for other system activity. When MR is negated, all outputs will be operating normally within 3 clock cycles. Q3 1 20 GND VCC 2 19 2X_Q MR 3 18 Q/2 PLL_EN 4 17 VCC VCC(AN) 5 16 Q2 RC1 6 15 GND GND(AN) 7 14 LOCK SYNC 8 13 FBSEL GND 9 12 Q1 11 VCC Q0 10 Pinout: 20–Lead Wide SOIC Package (Top View) CAPACITANCE AND POWER SPECIFICATIONS Symbol Parameter Value Typ Unit Test Conditions CIN Input Capacitance 4.5 pF VCC = 5.0V CPD Power Dissipation Capacitance 40 pF VCC = 5.0V PD1 Power Dissipation at 33MHz With 50Ω Thevenin Termination 15mW/Output 90mW/Device mW VCC = 5.0V T = 25°C PD2 Power Dissipation at 33MHz With 50Ω Parallel Termination to GND 37.5mW/Output 225mW/Device mW VCC = 5.0V T = 25°C MAXIMUM RATINGS* Symbol Parameter Limits Unit VCC, AVCC DC Supply Voltage Referenced to GND –0.5 to 7.0 V Vin DC Input Voltage (Referenced to GND) –0.5 to VCC +0.5 V Vout DC Output Voltage (Referenced to GND) –0.5 to VCC +0.5 V Iin DC Input Current, Per Pin ±20 mA Iout DC Output Sink/Source Current, Per Pin ±50 mA ICC DC VCC or GND Current Per Output Pin ±50 mA Tstg Storage Temperature –65 to +150 °C * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. MOTOROLA 2 TIMING SOLUTIONS BR1333 — REV 5 MC88921 RECOMMENDED OPERATING CONDITIONS Symbol Parameter Limits Unit VCC Supply Voltage 5.0 ±10% V Vin DC Input Voltage 0 to VCC V Vout DC Output Voltage 0 to VCC V TA Ambient Operating Temperature 0 to 70 °C ESD Static Discharge Voltage > 1500 V DC CHARACTERISTICS (TA = –40°C to 85°C; VCC = 5.0V ± 5%) Symbol Parameter VCC Guaranteed Limits Unit Condition VIH Minimum High Level Input Voltage 4.75 5.25 2.0 2.0 V VOUT = 0.1V or VCC – 0.1V VIL Minimum Low Level Input Voltage 4.75 5.25 0.8 0.8 V VOUT = 0.1V or VCC – 0.1V VOH Minimum High Level Output Voltage 4.75 5.25 4.01 4.51 V VIN = VIH or VIL IOH –36mA –36mA VOL Minimum Low Level Output Voltage 4.75 5.25 0.44 0.44 V VIN = VIH or VIL IOH +36mA1 +36mA IIN Maximum Input Leakage Current 5.25 ±1.0 µA VI = VCC, GND mA VI = VCC – 2.1V ICCT Maximum ICC/Input 5.25 2.0 2 IOLD Minimum Dynamic3 Output Current 5.25 88 mA VOLD = 1.0V Max 5.25 –88 mA VOHD = 3.85 Min 5.25 750 µA VI = VCC, GND Minimum Maximum Unit — 5.0 ns 1 f2X_Qń4 200 ns IOHD ICC Maximum Quiescent Supply Current 1. IOL is +12mA for the LOCK output. 2. The PLL_EN input pin is not guaranteed to meet this specification. 3. Maximum test duration 2.0ms, one output loaded at a time. SYNC INPUT TIMING REQUIREMENTS Symbol Parameter tRISE/FALL SYNC Input Rise/Fall Time, SYNC Input From 0.8V to 2.0V tCYCLE, SYNC Input Input Clock Period SYNC Input Duty Cycle Duty Cycle, SYNC Input TIMING SOLUTIONS BR1333 — REV 5 50% ± 25% 3 MOTOROLA MC88921 LOCK 2X_Q LOCK INDICATOR RC1 SYNC1 CH PUMP PFD D Q Q0 Q Q1 Q Q2 R VCO D R PLL_EN 0 1 D ÷2 POWER–ON RESET R D Q MR Q R D “Dummy” Flip–Flop to Maintain Phase–Locked Operation Q Q3 Q Q/2 R D FBSEL R 0 1 Figure 1. MC88921 Logic Block Diagram FREQUENCY SPECIFICATIONS (TA = –40°C to 85°C; VCC = 5.0V ± 5%) Symbol Parameter Guaranteed Minimum Unit Fmax (2X_Q) Maximum Operating Frequency, 2X_Q Output 66 MHz Fmax (‘Q’) Maximum Operating Frequency, Q0–Q3 Outputs 33 MHz 1. Maximum Operating Frequency is guaranteed with the 88921 in a phase–locked condition, and all outputs loaded at 50pF. MOTOROLA 4 TIMING SOLUTIONS BR1333 — REV 5 MC88921 AC CHARACTERISTICS (TA = –40°C to 85°C; VCC = 5.0V ± 5%) Symbol Minimum Maximum Unit Rise/Fall Time, All Outputs into 50Ω Load 0.3 1.6 ns tRISE – 0.8V to 2.0V tFALL – 2.0V to 0.8V tRISE/FALL1 2X_Q Output Rise/Fall Time into a 20pF Load, With Termination Specified in AppNote 3 0.5 1.6 ns tRISE – 0.8V to 2.0V tFALL – 2.0V to 0.8V tpulse width(a)1 (Q0, Q1, Q2, Q3) Output Pulse Width Q0, Q1, Q2, Q3 at VCC/2 0.5tcycle – 0.55 0.5tcycle + 0.55 ns 50Ω Load Terminated to VCC/2 (See Application Note 3) tpulse width(b)1 (2X_Q Output) Output Pulse Width 2X_Q at VCC/2 0.5tcycle – 0.55 0.5tcycle + 0.55 ns 50Ω Load Terminated to VCC/2 (See Application Note 3) tPD1,4 SYNC – Q/2 SYNC Input to Q Output Delay (Measured at SYNC and Q/2 Pins) –0.75 –0.15 ns With 1MΩ From RC1 to An VCC (See Application Note 2) +1.25 7 +3.25 7 ns With 1MΩ From RC1 to An GND (See Application Note 2) tRISE/FALL1 All Outputs Parameter Condition tSKEWr1,2 (Rising) Output–to–Output Skew Between Outputs Q0–Q3 (Rising Edge Only) — 500 ps Into a 50Ω Load Terminated to VCC/2 (See Timing Diagram in Figure 6) tSKEWf1,2 (Falling) Output–to–Output Skew Between Outputs Q0–Q3 (Falling Edge Only) — 1.0 ns Into a 50Ω Load Terminated to VCC/2 (See Timing Diagram in Figure 6) tSKEWall1,2 Output–to–Output Skew 2X_Q, Q0–Q3 Rising — 1.0 ns Into a 50Ω Load Terminated to VCC/2 (See Timing Diagram in Figure 6) tLOCK3 Phase–Lock Acquisition Time, All Outputs to SYNC Input 1 10 ms tPHL MR – Q Propagation Delay, MR to Any Output (High–Low) 1.5 13.5 ns tREC, MR to SYNC6 Reset Recovery Time rising MR edge to falling SYNC edge 9 — ns tREC, MR to Normal Operation Recovery Time for Outputs 2X_Q, Q0, Q1 to Return to Normal PLL Operation — 3 Clock Cycles (Q Frequency) ns tW, MR LOW6 Minimum Pulse Width, MR input Low 5 — ns Into a 50Ω Load Terminated to VCC/2 1. These specifications are not tested, they are guaranteed by statistical characterization. See Application Note 1 for a discussion of this methodology. 2. Under equally loaded conditions and at a fixed temperature and voltage. 3. With VCC fully powered–on: tCLOCK Max is with C1 = 0.1µF; tLOCK Min is with C1 = 0.01µF. 4. See Application Note 4 for the distribution in time of each output referenced to SYNC. 5. Refer to Application Note 3 to translate signals to a 1.5V threshold. 6. Specification is valid only when the PLL_EN pin is low. 7. This is a typical specification only, worst case guarantees are not provided. TIMING SOLUTIONS BR1333 — REV 5 5 MOTOROLA MC88921 Application Notes these two specs to be guaranteed by Motorola, the termination scheme shown in Figure 3 must be used. For applications which require 1.5V thresholds, but do not require a tight duty cycle the RP resistor can be ignored. 1. Several specifications can only be measured when the MC88921 is in phase–locked operation. It is not possible to have the part in phase–lock on ATE (automated test equipment). Statistical characterization techniques were used to guarantee those specifications which cannot be measured on the ATE. MC88921 units were fabricated with key transistor properties intentionally varied to create a 14 cell designed experimental matrix. IC performance was characterized over a range of transistor properties (represented by the 14 cells) in excess of the expected process variation of the wafer fabrication area. 4. The tPD spec (SYNC to Q/2) guarantees how close the Q/2 output will be locked to the reference input connected to the SYNC input (including temperature and voltage variation). This also tells what the skew from the Q/2 output on one part connected to a given reference input, to the Q/2 output on one or more parts connected to that reference input (assuming equal delay from the reference input to the SYNC input of each part). Therefore the tPD spec is equivalent to a part–to–part specification. However, to correctly predict the skew from a given output on one part to any other output on one or more other parts, the distribution of each output in relation to the SYNC input must be known. This distribution for the MC88921 is provided in Table 1. 2. A 1MΩ resistor tied to either Analog VCC or Analog GND, as shown in Figure 2, is required to ensure no jitter is present on the MC88921 outputs. This technique causes a phase offset between the SYNC input and the Q0 output, measured at the pins. The tPD spec describes how this offset varies with process, temperature, and voltage. The specs were arrived at by measuring the phase relationship for the 14 lots described in note 1 while the part was in phase–locked operation. The actual measurements were made with a 10MHz SYNC input (1.0ns edge rate from 0.8V to 2.0V). The phase measurements were made at 1.5V. See Figure 2 for a graphical description. TABLE 1. Distribution of Each Output versus SYNC 3. Two specs (tRISE/FALL and tPULSE Width 2X_Q output, see AC Specifications) guarantee that the MC88921 meets the 20MHz, 25MHz and 33MHz 68040 P–Clock input specification (at 40MHz, 50MHz, and 66MHz). For Output –(ps) +(ps) 2X_Q Q0 Q1 Q2 Q3 Q/2 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD RC1 EXTERNAL LOOP FILTER 330Ω 0.1µF ANALOG VCC 1M REFERENCE RESISTOR R2 C1 1M REFERENCE RESISTOR RC1 330Ω 0.1µF ANALOG GND R2 C1 ANALOG GND WITH THE 1MΩ RESISTOR TIED IN THIS FASHION THE TPD SPECIFICATION, MEASURED AT THE INPUT PINS IS: WITH THE 1MΩ RESISTOR TIED IN THIS FASHION THE TPD SPECIFICATION, MEASURED AT THE INPUT PINS IS: tPD = 2.25ns ± 1.0ns (TYPICAL VALUES) 3V tPD = –0.80ns ± 0.30ns 3V SYNC INPUT SYNC INPUT 2.25ns OFFSET –0.8ns OFFSET 5V 5V Q0 OUTPUT Q0 OUTPUT Figure 2. Depiction of the Fixed SYNC to Q0 Offset (tPD) Which Is Present When a 1MΩ Resistor Is Tied to VCC or Ground MOTOROLA 6 TIMING SOLUTIONS BR1333 — REV 5 MC88921 88921 2X_Q OUTPUT Zo (CLOCK TRACE) Rs RP Rs = Zo – 7Ω 68040 P–CLOC K INPUT RP = 1.5Zo Figure 3. MC68040 P–Clock Input Termination Scheme 16.5MHz CRYSTAL OSCILLATOR 2X_Q SYNC Q0 Q1 Q2 Q3 66MHz P–CLOCK OUTPUT 33MHz B–CLOCK AND SYSTEM OUTPUTS MR PLL_EN Figure 4. Logical Representation of the MC88921 With Input/Output Frequency Relationships SYNC Input tCYCLE SYNC Input tSKEWall tSKEWf tSKEWr tSKEWf tSKEWr Q0–Q3 Outputs 2X_Q Output Figure 5. Output/Input Switching Waveforms and Timing Relationships Timing Notes 1. The MC88921 aligns rising edges of the outputs and the SYNC input, therefore the SYNC input does not require a 50% duty cycle. 2. All skew specs are measured between the VCC/2 crossing point of the appropriate output edges. All skews are specified as ‘windows’, not as a ± deviation around a center point. TIMING SOLUTIONS BR1333 — REV 5 7 MOTOROLA MC88921 The tPD window for a given ∆T and ∆VCC is given by the following regression formula: The tPD spec includes the full temperature range from 0°C to 70°C and the full VCC range from 4.75V to 5.25V. If the ∆T and ∆VCC is a given system are less than the specification limits, the tPD spec window will be reduced. TBD Notes Concerning Loop Filter and Board Layout Issues 1. Figure 7 shows a loop filter and analog isolation scheme which will be effective in most applications. The following guidelines should be followed to ensure stable and jitter–free operation: purpose of the bypass filtering scheme shown in Figure 7 is to give the 88921 additional protection from the power supply and ground plane transients that can occur in a high frequency, high speed digital system. 1a. All loop filter and analog isolation components should be tied as close to the package as possible. Stray current passing through the parasitics of long traces can cause undesirable voltage transients at the RC1 pin. 1c. There are no special requirements set forth for the loop filter resistors (1M and 330Ω). The loop filter capacitor (0.1uF) can be a ceramic chip capacitor, the same as a standard bypass capacitor. 1b. The 47Ω resistors, the 10µF low frequency bypass capacitor, and the 0.1µF high frequency bypass capacitor form a wide bandwidth filter that will make the 88921 PLL insensitive to voltage transients from the system digital VCC supply and ground planes. This filter will typically ensure that a 100mV step deviation on the digital VCC supply will cause no more than a 100ps phase deviation on the 88921 outputs. A 250mV step deviation on VCC using the recommended filter values will cause no more than a 250ps phase deviation; if a 25µF bypass capacitor is used (instead of 10µF) a 250mV VCC step will cause no more than a 100ps phase deviation. 1d. The 1M reference resistor injects current into the internal charge pump of the PLL, causing a fixed offset between the outputs and the SYNC input. This also prevents excessive jitter caused by inherent PLL dead–band. If the VCO (2X_Q output) is running above 40MHz, the 1M resistor provides the correct amount of current injection into the charge pump (2–3µA). 2. In addition to the bypass capacitors used in the analog filter of Figure 7, there should be a 0.1µF bypass capacitor between each of the other (digital) four VCC pins and the board ground plane. This will reduce output switching noise caused by the 88921 outputs, in addition to reducing potential for noise in the ‘analog’ section of the chip. These bypass capacitors should also be tied as close to the 88921 package as possible. If good bypass techniques are used on a board design near components which may cause digital VCC and ground noise, the above described VCC step deviations should not occur at the 88921’s digital VCC supply. The BOARD VCC 47Ω 5 1MΩ 10µF LOW FREQ BIAS ANALOG VCC 330Ω 0.1µF HIGH FREQ BIAS ANALOG LOOP FILTER/VCO SECTION OF THE MC88921 20–PIN SOIC PACKAGE (NOT DRAWN TO SCALE) 6 RC1 7 ANALOG GND 0.1µF (LOOP FILTER CAP) 47Ω BOARD GND A SEPARATE ANALOG POWER SUPPLY IS NOT NECESSARY AND SHOULD NOT BE USED. FOLLOWING THESE PRESCRIBED GUIDELINES IS ALL THAT IS NECESSARY TO USE THE MC88921 IN A NORMAL DIGITAL ENVIRONMENT. Figure 6. Recommended Loop Filter and Analog Isolation Scheme for the MC88921 MOTOROLA 8 TIMING SOLUTIONS BR1333 — REV 5 MC88921 16.5MHz X–TAL OSCILLATOR 2X_Q 66MHz Pentium Microprocessor PCLK ASIC SYNC Q1 Q2 Q3 ASIC 33MHz MEMORY MODULE Figure 7. Typical MC88921/Pentium Microprocessor System Configuration TIMING SOLUTIONS BR1333 — REV 5 9 MOTOROLA MC88921 OUTLINE DIMENSIONS DW SUFFIX SOIC PACKAGE CASE 751D-03 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. 751D-01, AND -02 OBSOLETE, NEW STANDARD 751D-03. -A20 11 1 10 -B- P 0.25 (0.010) M B M 10 PL G DIM R X 45° C -T- SEATING PLANE M K D 20 PL 0.25 (0.010) M T B S A S F J MILLIMETERS MIN MAX A 12.65 12.95 7.60 B 7.40 2.65 C 2.35 0.49 D 0.35 0.90 F 0.50 1.27 BSC G J 0.25 0.32 K 0.10 0.25 M 7° 0° P 10.05 10.55 R 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0° 7° 0.395 0.415 0.010 0.029 Motorola reserves the right to make changes without further notice to any products herein. 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Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315 MFAX: [email protected] –TOUCHTONE (602) 244–6609 INTERNET: http://Design–NET.com HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 MOTOROLA ◊ CODELINE 10 *MC88921/D* MC88921/D TIMING SOLUTIONS BR1333 — REV 5