MOTOROLA MC88PL117FN

SEMICONDUCTOR TECHNICAL DATA
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The MC88PL117 utilizes proven phase–locked loop clock driver
technology to create a large fan–out, multiple frequency and phase, low
skew clock driver. The 88PL117 provides the clock frequencies
necessary to drive systems using the PowerPC 601 microprocessor
and the Pentium microprocessor (see applications section for details).
A total of 14 high current, matched impedance outputs are available in 8
programmable output frequency and phase configurations. Output
frequencies are referenced to a system frequency, Q, and are available at
2X, 1X, and 1/2X the Q frequency. Four programmable input frequency
multiplication ratios can be programmed to provide outputs at 1X, 2X, and
4X the system frequency Q. Details on the programmable configurations
can be found in the applications section of this data sheet.
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Clock Driver for PowerPC 601 and Pentium Microprocessors
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Dedicated feedback output
CMOS PLL
CLOCK DRIVER
14 programmable outputs
Maximum output–to–output skew of 500ps for a single frequency
Maximum output–to–output skew of 500ps for multiple frequencies
fMAX of 2X_Q = 120MHz
One output with programmable phase capability
±36mA DC current outputs drive 50Ω transmission lines
FN SUFFIX
52–LEAD PLASTIC LEADLESS
CHIP CARRIER (PLCC)
CASE 778–02
A lock indicator output (LOCK) goes high when steady–state
phase–lock is achieved
• OE/MR 3–state control
Two selectable clock inputs
PLL enable pin for testability
Dynamic Switch Between SYNC Inputs
One output (QFEED) is dedicated for feedback. It is located physically close to the FEEDBACK input pin to minimize the
feedback line length. External delay (increased wire length) or logic can be inserted in the feedback path if necessary. Proper
termination of the feedback line is necessary for any line length over one inch.
One output is provided with up to eight selectable 1/8 or 1/4 period (45° or 90°) delay increments. Three control pins, ∅2, ∅1
and ∅0, program the eight increments; the increment/phase shift positions are shown in Table 3. in the applications section.
All outputs can be 3–stated (high impedance) during board–level testing with the OE/MR pin; the QFEED and LOCK outputs
will not be 3–stated, which allows the 88PL117 to remain in a phase–locked condition. Correct phase and frequency coherency
will be guaranteed one to two cycles after bringing the OE/MR pin high. The PLL_EN pin disables the PLL and gates the SYNC
input signal directly into the internal clock distribution network to provide low frequency testability. Two selectable SYNC inputs
(SYNC0 and SYNC1) are provided for clock redundancy or ease of testability. The device is guaranteed to lock to the new SYNC
input when the REF_SEL input is switched dynamically.
A phase–lock indicator output (LOCK) stays low when the part is out of lock (start–up, etc.) and goes high when steady–state
phase–lock is achieved. The lock indicator circuitry works reliably for VCO frequencies down to 55MHz. For VCO frequencies
less than 55MHz, no guarantees are offered for the lock indicator output.
The MC88PL117 VCO is capable of operating at frequencies higher than the output divider and feedback structures are able
to follow. When the VCO is in the mode described above, it is referred to as “runaway” and the device will not lock. The condition
usually occurs at power–up. To avoid runaway, it is recommended that the device be fully powered before a sync signal is
applied.
PowerPC is a trademark of International Business Machines Corporation.
1/97
 Motorola, Inc. 1997
1
REV 4
MC88PL117
QFEED VCC
46
45
FEEDBACK GND
44
43
AVCC
FIL
AGND
GND
Q13
VCC
Q12
42
41
40
39
38
37
36
REF_SEL SYNC1
35
34
LOCK
47
33
SYNC0
OE/MR
48
32
DVDD
Q0
49
31
DGND
VCC
50
30
Q∅
Q1
51
29
Q11
GND
52
28
VCC
Q2
1
27
Q10
VCC
2
26
GND
Q3
3
25
Q9
GND
4
24
VCC
OPT0
5
23
Q8
OPT1
6
22
GND
OPT2
7
21
PLL_EN
MC88PL117
8
9
MULT0 MULT1
10
11
12
13
14
15
16
17
18
19
20
GND
Q4
VCC
Q5
GND
Q6
VCC
Q7
∅0
∅1
∅2
Pinout: 52–Lead PLCC (Top View)
MOTOROLA
2
TIMING SOLUTIONS
BR1333 — Rev 6
MC88PL117
LOCK INDICATOR
CIRCUITRY
LOCK
EXTERNAL
FILTER PIN
SYNC0
SYNC1
0
1
CH
PUMP
PFD
VCO
Disable
REF_SEL
0 1
FEEDBACK
PLL_EN
D
Q
Q0
Q
Q13
Q
QFEED
Q
Q∅
R
OPT2
OUTPUT
FREQUENCY
AND PHASE
CONTROL
LOGIC
OPT1
OPT0
POWER–ON
RESET
D
R
MULT1
MULT0
FEEDBACK
LOGIC
D
R
∅2
∅1
∅0
D
PHASE DELAY
LOGIC
R
OE/MR
MC88PL117 Block Diagram (Logical Representation)
TIMING SOLUTIONS
BR1333 — Rev 6
3
MOTOROLA
MC88PL117
Explanation of Programmable Frequency Configurations
and OPT2 for each of the eight output configurations. The
input levels of MULT0 and MULT1 are varied in these figures
to represent the different feedback (multiplication)
frequencies. The frequency of the phase shift output, Q∅, is
also indicated in the figures. Tables 1. and 2. lists all 18
input/output frequency configurations. Table 3. gives the Q∅
phase shift increments.
The MC88PL117 has six different output frequency
configurations. Figures 1 to 6 graphically depict these output
configurations. There are also three feedback frequency
options, which yields a total of 18 unique input–to–output
frequency configurations. All configurations use ‘Q’ as the
system frequency frame of reference. Therefore all output
and feedback frequencies are referenced as a multiple of Q.
Figures 1 to 6 also indicate the input levels of OPT0, OPT1,
MC88PL117
FIL
H
H
L
Q/2 In (40MHz)
OE/MR
PLL_EN
REF_SEL
SYNC0
SYNC1
FEEDBACK
L
L
L
OPT2
OPT1
OPT0
L
H
L
∅2
∅1
∅0
L
H
MULT1
MULT0
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
2X_Q (120MHz)
2X_Q (120MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q∅
0° Phase Shift at 60MHz
MC88PL117
FIL
H
H
L
Q/4 In (20MHz)
OE/MR
PLL_EN
REF_SEL
SYNC0
SYNC1
FEEDBACK
L
L
H
OPT2
OPT1
OPT0
H
H
H
∅2
∅1
∅0
L
L
MULT1
MULT0
LOCK
Figure 1. Output Frequency Configuration 1
(OPT0 = L, OPT1 = L, OPT2 = L
Q/2 Input Frequency, MULT0 = H, MULT1 = L)
MC88PL117
H
H
L
Q/2 In (30MHz)
OE/MR
PLL_EN
REF_SEL
SYNC0
SYNC1
FEEDBACK
L
H
L
OPT2
OPT1
OPT0
L
H
L
∅2
∅1
∅0
L
H
MULT1
MULT0
Q∅
0° Phase Shift at 30MHz
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
2X_Q (120MHz)
2X_Q (120MHz)
2X_Q (120MHz)
2X_Q (120MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q∅
0° Phase Shift at 60MHz
LOCK
Figure 2. Output Frequency Configuration 2
(OPT0 = H, OPT1 = L, OPT2 = L
Q/4 Input Frequency, MULT0 = L, MULT1 = L)
MC88PL117
FIL
H
H
L
Q/2 In (30MHz)
OE/MR
PLL_EN
REF_SEL
SYNC0
SYNC1
FEEDBACK
L
H
H
OPT2
OPT1
OPT0
L
H
L
∅2
∅1
∅0
L
H
MULT1
MULT0
QFEED
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q∅
0° Phase Shift at 60MHz
QFEED
LOCK
Figure 3. Output Frequency Configuration 3
(OPT0 = L, OPT1 = H, OPT2 = L
Q/2 Input Frequency, MULT0 = H, MULT1 = L)
MOTOROLA
2X_Q (120MHz)
2X_Q (120MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
QFEED
QFEED
FIL
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
LOCK
Figure 4. Output Frequency Configuration 4
(OPT0 = H, OPT1 = H, OPT2 = L
Q/2 Input Frequency, MULT0 = H, MULT1 = L)
4
TIMING SOLUTIONS
BR1333 — Rev 6
MC88PL117
MC88PL117
FIL
H
H
L
Q/4 In (16.5MHz)
OE/MR
PLL_EN
REF_SEL
SYNC0
SYNC1
FEEDBACK
H
L
L
OPT2
OPT1
OPT0
H
H
H
∅2
∅1
∅0
L
L
MULT1
MULT0
MC88PL117
FIL
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q∅
0° Phase Shift at 30MHz
H
H
L
Q In (80MHz)
OE/MR
PLL_EN
REF_SEL
SYNC0
SYNC1
FEEDBACK
H
H
H
OPT2
OPT1
OPT0
L
H
L
∅2
∅1
∅0
H
H
MULT1
MULT0
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
2X_Q (120MHz)
2X_Q (120MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q∅
0° Phase Shift at 60MHz
QFEED
QFEED
LOCK
Figure 5. Output Frequency Configuration 5
(OPT0 = L, OPT1 = L, OPT2 = H
Q/4 Input Frequency, MULT0 = L, MULT1 = L)
LOCK
Figure 6. Output Frequency Configuration 6
(OPT0 = H, OPT1 = H, OPT2 = H
Q Input Frequency, MULT0 = H, MULT1 = H)
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) TA =0° C to + 70° C, VCC = 5.0 V ± 5%
Parameter
Target Limit
Unit
Minimum High–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
4.75
5.25
2.0
2.0
V
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
4.75
5.25
0.8
0.8
V
VOH
Minimum High–Level Output
Voltage
Vin = VIH or VIL
IOH = –36 mA 1
4.75
5.25
4.01
4.51
V
VOL
Maximum Low–Level Output
Voltage
Vin = VIH or VIL
IOL = 36 mA 1
4.75
5.25
0.44
0.44
V
Maximum Input Leakage Current
VI = VCC or GND
5.25
±1.0
µA
mA
Iin
ICCT
Maximum ICC/Input
VI = VCC – 2.1 V
5.25
2.0 2
IOLD
Minimum Dynamic Output Current 3
VOLD = 1.0V Max
5.25
88
mA
VOHD = 3.85V Min
5.25
–88
mA
VI = VCC or GND
5.25
1.0
mA
5.25
±50 4
µA
IOHD
ICC
1.
2.
3.
4.
Test Conditions
VCC
V
VIH
Symbol
Maximum Quiescent Supply
Current (per Package)
IOZ
Maximum 3–State Leakage Current
VI = VIH or VIL;VO = VCC or GND
IOL and IOH are 12mA and –12mA respectively for the LOCK output.
The PLL_EN input pin is not guaranteed to meet this specification.
Maximum test duration is 2.0ms, one output loaded at a time.
Specification value for IOZ is preliminary, will be finalized upon ‘MC’ status.
TIMING SOLUTIONS
BR1333 — Rev 6
5
MOTOROLA
MC88PL117
PRELIMINARY AC ELECTRICAL CHARACTERISTICS (TA = 0 to 70°C, VCC = 5.0V ±5%)
Target Specifications
Symbol
Parameter
Min
Max
Unit
Condition
tskewr
Output–to–Output Skew (Same Frequency,
Coincident Rising Edges)
500
ps
50Ω Load2
tskewrall
Output–to–Output Skew (Any Frequency,
Coincident Rising Edges, Q0–Q13, QFEED)
500
ps
50Ω Load2
tskewp
Part–to–Part Skew1
1.0
ns
50Ω Load2
tr/tf
Output Rise/Fall Time (0.8 to 2.0V)
0.15
1.0
ns
50Ω Load2
tPULSE
Output Pulse Width, All Outputs2 (Measured at
VCC/2)
0.5tCYCLE – 0.5
0.5tCYCLE + 0.5
ns
50Ω Load2
tpd
SYNC Input to
FEEDBACK Delay
fSYNC=15MHz
fSYNC=20MHz
fSYNC=25MHz
fSYNC=30MHz
–200
–200
–100
0
400
400
500
600
ps
Feedback=Q,Q/2
fSYNC=15MHz
–50
JitterCC
Cycle–to–Cycle Jitter (Clock Period Stability)
fMAX
Maximum Output Frequency for 2X_Q Outputs
fMAX
550
Feedback=Q/4
±250
ps
8
120
MHz
50Ω Load2
Maximum Output Frequency for Q Outputs
4
60
MHz
50Ω Load2
fMAX
Maximum Output Frequency for Q/2 Outputs
2
30
MHz
50Ω Load2
tskew∅
Phase Accuracy of Q∅ versus Q or Q/2
Phase Offset – 750
Phase Offset + 250
ps
1. This assumes that each device is running off of the same clock source with zero skew between clock source signals. A small amount of negative
offset may be present between SYNC and FEEDBACK (tPD Spec).
2. 50Ω load terminated to VCC/2.
MOTOROLA
6
TIMING SOLUTIONS
BR1333 — Rev 6
MC88PL117
TABLE 1. PROGRAMMABLE OUTPUT CONFIGURATIONS (Q is system reference frequency)
Output Configuration Number
OPT2
OPT1
OPT0
No of 2X_Q
Outputs
No of Q
Outputs
No of Q/2
Outputs
1
L
L
L
2
12
0
2
L
L
H
2
4
8
3
L
H
L
4
10
0
4
L
H
H
0
14
0
5
H
L
L
0
7
7
6
H
H
H
2
12
0
TABLE 2. PROGRAMMABLE INPUT FREQUENCY MODES (Multiplication factors)
Input Frequency Mode
MULT1
MULT0
Input Frequency
1
L
L
Q/4
2
L
H
Q/2
3
H
H
Q
TABLE 3. Q∅ PROGRAMMABLE PHASE INCREMENTS FOR Q AND Q/2 OUTPUTS
∅2
∅1
∅0
Q∅ Phase
to Q Outputs1
Q∅/2 Phase
to Q Outputs2
∅2
∅1
∅0
Q∅ Phase
to Q Outputs1
Q∅/2 Phase
to Q Outputs2
L
L
L
180°
45°
H
L
L
180°
225°
L
L
H
90°
90°
H
L
H
90°
270°
L
H
L
0°
135°
H
H
L
0°
315°
L
H
H
270°
180°
H
H
H
270°
360°
1. Valid for output configurations 1, 3, 4, 6, 8
2. Valid for output configurations 2, 5, 7
Applications Information
suitable for PowerPC 601 or Pentium Microprocessor based
designs.
Introduction
The 88PL117 provides the necessary clock frequencies
for the PowerPC 601 and Pentium Microprocessors. With
output frequency capabilities up to 120MHz and the ability to
also generate half and quarter frequency clocks the 88PL117
simplifies the system implementation of a PowerPC 601 or
Pentium Microprocessor. This section will overview the clock
re quir em ent s of th e Po w e rPC 6 0 1 a n d P enti um
Microprocessors and apply those to the specification limits of
the 88PL117 to demonstrate compatibility. Although not
exhaustive the intent is to provide a basic set of guidelines on
system implementation. For more cost sensitive applications
which require fewer clocks the designer should refer to the
MC88915TFN133 data sheet for an alternative clock driver
TIMING SOLUTIONS
BR1333 — Rev 6
Figures 7 and 8 illustrate two common output config–
urations of the 88PL117 which will facilitate POWERPC 601
(MPC601) system designs. Figure 7 would prove beneficial
for high frequency processor designs where the bus clock
would likely run at one fourth the 2X_PCLK input. In this
configuration a 2X_Q output of the 88PL117 can drive the
2X_PCLK of the PowerPC 601 processor while a Q and Q/2
output can drive the PCLK_EN and BCLK_EN inputs
respectively. For designs where the system bus will run at
half the frequency of the 2X_PCLK (same frequency as the
internal processor clock) a larger number of Q outputs would
be required. Figure 8 could be used in this situation with a
7
MOTOROLA
MC88PL117
drive the BCLK_EN input. The Q∅ output can be phase
delayed relative to the 2X_Q output to ensure the hold time
requirement of the MPC601 processor will be met.
2X_Q output driving the 2X_PCLK input and a Q output
driving the PCLK_EN. In this implementation the BCLK_EN
input of the MPC601 is simply tied LOW.
MC88PL117
FIL
H
H
L
Q/4 In (15MHz)
OE/MR
PLL_EN
REF_SEL
SYNC0
SYNC1
FEEDBACK
L
L
H
OPT2
OPT1
OPT0
H
H
H
∅2
∅1
∅0
L
L
MULT1
MULT0
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
2X_Q (120MHz)
2X_Q (120MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q∅
0° Phase Shift at 30MHz
2X_PCLK
PCLK_EN
BCLK_EN
1/2 FREQUENCY BUS CLOCKING
2X_PCLK
QFEED
PCLK_EN
LOCK
BCLK_EN
Figure 7. 88PL117 Output Configuration 1 for
Driving the MPC601 Microprocessor
FULL FREQUENCY BUS CLOCKING
Figure 9. MPC601 Processor Clocking Waveforms
MC88PL117
FIL
H
H
L
Q/2 In (25MHz)
OE/MR
PLL_EN
REF_SEL
SYNC0
SYNC1
FEEDBACK
L
L
L
OPT2
OPT1
OPT0
L
H
L
∅2
∅1
∅0
L
H
MULT1
MULT0
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
2X_Q (100MHz)
2X_Q (100MHz)
Q (50MHz)
Q (50MHz)
Q (50MHz)
Q (50MHz)
Q (50MHz)
Q (50MHz)
Q (50MHz)
Q (50MHz)
Q (50MHz)
Q (50MHz)
Q (50MHz)
Q (50MHz)
Q∅
0° Phase Shift at 50MHz
2X_Q
Q
Q/2
Q∅ (45°)
QFEED
Figure 10. 88PL117 Output Waveforms
LOCK
The 88PL117 features CMOS level outputs to minimize
edge transition time and optimize transmission line driving
capability. The MPC601 processor inputs are TTL level
compatible inputs and therefore specification limits are
calculated from TTL level thresholds. The specification limits
of concern are the input duty cycle and input pulse width
requirements outlined in the MPC601 specification for the
2X_PCLK input. Figure 11 demonstrates the termination
technique required on the 2X_Q output of the 88PL117 to
ensure compatibility with the 2X_PCLK input of the MPC601
processor. At 100 or 120MHz, the 2X_Q output threshold
must be shifted down to the 1.4V threshold to meet the input
pulse width specification limits. The termination scheme in
Figure 11 creates a voltage division which essentially
translates the CMOS threshold down to a TTL threshold,
while at the same time effectively terminating the
transmission line. The 88PL117 exhibits a very tight duty
cycle specification at CMOS thresholds. Therefore, once
translated via the termination scheme of Figure 11, the
MPC601 processor input specifications are easily met.
Figure 8. 88PL117 Output Configuration 2 for
Driving the MPC601 Microprocessor
Driving the PowerPC 601 Microprocessor
Figures 9 and 10 illustrate the required waveforms for
driving the MPC601 processor in both bus clock frequency
modes. Figure 10 illustrates the relationship between the
2X_Q, Q and Q/2 outputs of the 88PL117. For the case of the
BCLK_EN input being held LOW, the setup and hold
specifications for PCLK_EN are automatically satisfied by the
internal design of the 88PL117. For the first case pictured in
Figure 9, there may be a potential problem: the hold time
spec for BCLK_EN rising to 2X_PCLK is 0ns. Because there
can be up to ±250ps skew between the 2X_Q and Q/2
outputs of the 88PL117, this hold spec may be violated. This
situation can be remedied in one of two ways: first extra PCB
etch can be added to the Q/2 output to delay it relative to the
2X_Q output; or secondly, the Q∅ output can be used to
MOTOROLA
8
TIMING SOLUTIONS
BR1333 — Rev 6
MC88PL117
88PL117
2X_Q
Output
Rs
ZO (CLOCK TRACE)
MPC601
2X_PCLK
Input
Rp
Rs = Zo – 7Ω
Rp = 1.5 Zo
Figure 11. MPC601 2X_PCLK Input Termination Scheme
BOARD VCC
47Ω
ANALOG VCC
10µF LOW
FREQ BYPASS
0.1µF HIGH
FREQ
BYPASS
470K
330Ω
FIL
ANALOG LOOP FILTER/VCO
SECTION
0.1µF (LOOP
FILTER CAP)
ANALOG GND
47Ω
BOARD GND
A SEPARATE ANALOG POWER SUPPLY IS NOT NECESSARY AND
SHOULD NOT BE USED. FOLLOWING THESE PRESCRIBED GUIDELINES
IS ALL THAT IS NECESSARY TO USE THE MC88PL117 IN A NORMAL
DIGITAL ENVIRONMENT.
Figure 12. Recommended Loop Filter and Analog Isolation Scheme
Notes Concerning Loop Filter and Board Layout Issues
on a board design near components which may cause
digital VCC and ground noise, the above described VCC
step deviations should not occur at the digital VCC
supply. The purpose of the bypass filtering scheme
shown in Figure 12 is to give the chip additional
protection from the power supply and ground plane
transients that can occur in a a high frequency, high
speed digital system.
1 Figure 12 shows a loop filter and analog isolation scheme
which will be effective in most applications. The following
guidelines should be followed to ensure stable and
jitter–free operation:
1aAll loop filter and analog isolation components should
be tied as close to the package as possible. Stray
current passing through the parasitics of long traces
can cause undesirable voltage transients at the FIL pin.
1bThe 47Ω resistors, the 10µF low frequency bypass
capacitor, and the 0.1µF high frequency bypass
capacitor form a wide bandwidth filter that will minimize
the PLL’s sensitivity to voltage transients from the
system digital VCC supply and ground planes. This filter
will typically ensure that a 100mV step deviation on the
digital VCC supply will cause no more than a 100pS
phase deviation on the device outputs. A 250mV step
deviation on VCC using the recommended filter values
should cause no more than a 250pS phase deviation; if
a 25µF bypass capacitor is used (instead of 10µF) a
250mV VCC step should cause no more than a 100pS
phase deviation. If good bypass techniques are used
TIMING SOLUTIONS
BR1333 — Rev 6
1c There are no special requirements set forth for the loop
filter resistors (470K and 330Ω). The loop filter
capacitor (0.1µF) can be a ceramic chip capacitor, the
same as a standard bypass capacitor.
2 In addition to the bypass capacitors used in the analog
filter of Figure 12, there should be a 0.1µF bypass
capacitor between each of the other (digital) nine VCC pins
and the board ground plane. This will reduce output
switching noise caused by the high current outputs, in
addition to reducing potential for noise in the ‘analog’
section of the chip. These bypass capacitors should also
be tied as close to the package as possible.
9
MOTOROLA
MC88PL117
OUTLINE DIMENSIONS
FN SUFFIX
PLASTIC PACKAGE
CASE 778-02
ISSUE C
0.007 (0.18)
B
Y BRK
–N–
M
T L–M
0.007 (0.18)
U
M
S
N
S
T L–M
S
N
S
D
Z
–M–
–L–
W
D
52
1
V
A
0.007 (0.18)
M
T L–M
S
N
S
R
0.007 (0.18)
M
T L–M
S
N
S
E
C
0.004 (0.100)
–T– SEATING
J
VIEW S
G
PLANE
G1
S
T L–M
S
H
N
S
0.007 (0.18)
M
T L–M
S
N
S
K1
K
F
0.007 (0.18)
M
T L–M
S
N
VIEW S
MOTOROLA
S
T L–M
S
N
S
VIEW D–D
Z
0.010 (0.25)
G1
0.010 (0.25)
X
10
S
NOTES:
1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE
TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT
MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE MEASURED
AT DATUM –T–, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE
BURRS AND INTERLEAD FLASH, BUT INCLUDING
ANY MISMATCH BETWEEN THE TOP AND BOTTOM
OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE
H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.785
0.795
0.785
0.795
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
–––
0.025
–––
0.750
0.756
0.750
0.756
0.042
0.048
0.042
0.048
0.042
0.056
–––
0.020
2_
10 _
0.710
0.730
0.040
–––
MILLIMETERS
MIN
MAX
19.94
20.19
19.94
20.19
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
–––
0.64
–––
19.05
19.20
19.05
19.20
1.07
1.21
1.07
1.21
1.07
1.42
–––
0.50
2_
10 _
18.04
18.54
1.02
–––
TIMING SOLUTIONS
BR1333 — Rev 6
MC88PL117
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
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JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
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51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
TIMING SOLUTIONS
BR1333 — Rev 6
◊
11
MC88PL117/D
MOTOROLA