SEMICONDUCTOR TECHNICAL DATA The MC88LV915T Clock Driver utilizes phase–locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for high performance PC’s and workstations. The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay to multiple components on a board. The PLL also allows the MC88LV915T to multiply a low frequency input clock and distribute it locally at a higher (2X) system frequency. Multiple 88LV915’s can lock onto a single reference clock, which is ideal for applications when a central system clock must be distributed synchronously to multiple boards (see Figure 4 on Page 9). LOW SKEW CMOS PLL CLOCK DRIVER Five “Q” outputs (Q0–Q4) are provided with less than 500 ps skew between their rising edges. The Q5 output is inverted (180° phase shift) from the “Q” outputs. The 2X_Q output runs at twice the “Q” output frequency, while the Q/2 runs at 1/2 the “Q” frequency. The VCO is designed to run optimally between 20 MHz and the 2X_Q Fmax specification. The wiring diagrams in Figure 2 detail the different feedback configurations which create specific input/output frequency relationships. Possible frequency ratios of the “Q” outputs to the SYNC input are 2:1, 1:1, and 1:2. The FREQ_SEL pin provides one bit programmable divide–by in the feedback path of the PLL. It selects between divide–by–1 and divide–by–2 of the VCO before its signal reaches the internal clock distribution section of the chip (see the block diagram on page 2). In most applications FREQ_SEL should be held high (÷1). If a low frequency reference clock input is used, holding FREQ_SEL low (÷2) will allow the VCO to run in its optimal range (>20MHz). In normal phase–locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the 88LV915T in a static “test mode”. In this mode there is no frequency limitation on the input clock, which is necessary for a low frequency board test environment. The second SYNC input can be used as a test clock input to further simplify board–level testing (see detailed description on page 11). Pulling the OE/RST pin low puts the clock outputs 2X_Q, Q0–Q4, Q5 and Q/2 into a high impedance state (3–state). After the OE/RST pin goes back high Q0–Q4, Q5 and Q/2 will be reset in the low state, with 2X_Q being the inverse of the selected SYNC input. Assuming PLL_EN is low, the outputs will remain reset until the 88LV915 sees a SYNC input pulse. A lock indicator output (LOCK) will go high when the loop is in steady–state phase and frequency lock. The LOCK output will go low if phase–lock is lost or when the PLL_EN pin is low. The LOCK output will go high no later than 10ms after the 88LV915 sees a SYNC signal and full 5V VCC. Features • Five Outputs (Q0–Q4) with Output–Output Skew < 500 ps each being phase and frequency locked to the SYNC input • The phase variation from part–to–part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the tPD specification, which defines the part–to–part skew) • • • • Input/Output phase–locked frequency ratios of 1:2, 1:1, and 2:1 are available Input frequency range from 5MHz – 2X_Q FMAX spec. Additional outputs available at 2X and +2 the system “Q” frequency. Also a Q (180° phase shift) output available All outputs have ±36 mA drive (equal high and low) at CMOS levels, and can drive either CMOS or TTL inputs. All inputs are TTL–level compatible. ±88mA IOL/IOH specifications guarantee 50Ω transmission line switching on the incident edge • Test Mode pin (PLL_EN) provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy purposes. All outputs can go into high impedance (3–state) for board test purposes • Lock Indicator (LOCK) accuracy indicates a phase–locked state Yield Surface Modeling and YSM are trademarks of Motorola, Inc. 1/97 Motorola, Inc. 1997 1 REV 2 MC88LV915T Pinout: 28–Lead PLCC (Top View) OE/RST VCC 4 3 Q5 GND Q4 VCC 2X_Q 2 1 28 27 26 FEEDBACK 5 25 Q/2 REF_SEL 6 24 GND SYNC[0] 7 23 Q3 VCC(AN) 8 22 VCC RC1 9 21 Q2 GND(AN) 10 20 GND SYNC[1] 11 19 LOCK 12 13 FREQ_SEL GND 14 Q0 15 16 17 18 VCC Q1 GND PLL_EN FN SUFFIX PLASTIC PLCC CASE 776–02 PIN SUMMARY MOTOROLA Pin Name Num I/O SYNC[0] SYNC[1] REF_SEL FREQ_SEL FEEDBACK RC1 Q(0–4) Q5 2x_Q Q/2 LOCK OE/RST PLL_EN VCC,GND 1 1 1 1 1 1 5 1 1 1 1 1 1 11 Input Input Input Input Input Input Output Output Output Output Output Input Input Function Reference clock input Reference clock input Chooses reference between sync[0] & Sync[1] Doubles VCO Internal Frequency (low) Feedback input to phase detector Input for external RC network Clock output (locked to sync) Inverse of clock output 2 x clock output (Q) frequency (synchronous) Clock output(Q) frequency ÷ 2 (synchronous) Indicates phase lock has been achieved (high when locked) Output Enable/Asynchronous reset (active low) Disables phase–lock for low freq. testing Power and ground pins (note pins 8, 10 are “analog” supply pins for internal PLL only) 2 TIMING SOLUTIONS BR1333 — Rev 6 MC88LV915T MC88LV915T BLOCK DIAGRAM LOCK FEEDBACK SYNC (0) SYNC (1) 0 1 M U X PHASE/FREQ. CHARGE PUMP/LOOP FILTER DETECTOR VOLTAGE CONTROLLED OSCILLATOR EXTERNAL REC NETWORK (RC1 Pin) REF_SEL 2x_Q 1 0 PLL_EN MUX D (÷1) CP 1 DIVIDE BY TWO Q (÷2) Q0 Q R M U X 0 D Q Q1 Q Q2 Q Q3 Q Q4 Q Q5 Q Q/2 CP R FREQ_SEL OE/RST D CP R D CP R D CP R D CP R D CP R TIMING SOLUTIONS BR1333 — Rev 6 3 MOTOROLA MC88LV915T MAXIMUM RATINGS* Symbol Parameter Limits Unit VCC, AVCC DC Supply Voltage Referenced to GND –0.5 to 7.0 V Vin DC Input Voltage (Referenced to GND) –0.5 to VCC +0.5 V Vout DC Output Voltage (Referenced to GND) –0.5 to VCC +0.5 V Iin DC Input Current, Per Pin ±20 mA Iout DC Output Sink/Source Current, Per Pin ±50 mA ICC DC VCC or GND Current Per Output Pin ±50 mA Tstg Storage Temperature –65 to +150 °C * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Limits Unit VCC Supply Voltage 3.3 ±0.3 V Vin DC Input Voltage 0 to VCC V Vout DC Output Voltage 0 to VCC V TA Ambient Operating Temperature 0 to 70 °C ESD Static Discharge Voltage > 1000 V DC CHARACTERISTICS (TA = 0°C to 70°C; VCC = 3.3V ± 0.3V) Symbol Parameter VCC Guaranteed Limits Unit Condition VIH Minimum High Level Input Voltage 3.0 3.3 2.0 2.0 V VOUT = 0.1V or VCC – 0.1V VIL Minimum Low Level Input Voltage 3.0 3.3 0.8 0.8 V VOUT = 0.1V or VCC – 0.1V VOH Minimum High Level Output Voltage 3.0 3.3 2.4 2.7 V VIN = VIH or VIL IOH= –24mA VOL Minimum Low Level Output Voltage 3.0 3.3 0.44 0.44 V VIN = VIH or VIL IOH= 24mA IIN Maximum Input Leakage Current 3.6 ±1.0 µA VI = VCC, GND ICCT Maximum ICC/Input 3.6 2.0 mA VI = VCC – 2.1V IOLD Minimum Dynamic3 Output Current 3.6 +50 mA VOLD = 1.25V 3.6 –50 mA VOHD =2.35V 3.6 TBD µA VI = VCC, GND Minimum Maximum Unit — 5.0 ns 1 f2X_Qń4 100 ns IOHD ICC Maximum Quiescent Supply Current 1. IOL is +12mA for the RST_OUT output. 2. The PLL_EN input pin is not guaranteed to meet this specification. 3. Maximum test duration 2.0ms, one output loaded at a time. SYNC INPUT TIMING REQUIREMENTS Symbol Parameter tRISE/FALL SYNC Input Rise/Fall Time, SYNC Input From 0.8V to 2.0V tCYCLE, SYNC Input Input Clock Period SYNC Input Duty Cycle Duty Cycle, SYNC Input MOTOROLA 50% ± 25% 4 TIMING SOLUTIONS BR1333 — Rev 6 MC88LV915T FREQUENCY SPECIFICATIONS (TA = 0°C to 70°C; VCC = 3.3V ± 0.3V) Symbol Parameter Guaranteed Minimum Unit Fmax (2X_Q) Maximum Operating Frequency, 2X_Q Output 100 MHz Fmax (‘Q’) Maximum Operating Frequency, Q0–Q3 Outputs 50 MHz NOTE: Maximum Operating Frequency is guaranteed with the 88LV926 in a phase–locked condition. AC CHARACTERISTICS (TA =0° C to +70° C, VCC = 3.3V ±0.3V, Load = 50Ω Terminated to VCC/2) Symbol Parameter Min Max Unit 0.5 2.0 ns Into a 50Ω Load Terminated to VCC/2 0.5tCYCLE – 0.5 1 0.5tCYCLE + 0.5 1 ns Into a 50Ω Load Terminated to VCC/2 ns Into a 50Ω Load Terminated to VCC/2 tRISE/FALL Outputs Rise/Fall Time, All Outputs (Between 0.8 to 2.0V) tPULSE WIDTH (Q0–Q4, Q5, Q/2) Output Pulse Width: Q0, Q1, Q2, Q3, Q4, Q5, Q/2 @ VCC/2 tPULSE WIDTH (2X_Q Output) Output Pulse Width: 2X_Q @ 1.5V 40MHz 66MHz 80MHz 100MHz 0.5tCYCLE – 1.5 0.5tCYCLE – 1.0 0.5tCYCLE – 1.0 0.5tCYCLE – 1.0 0.5tCYCLE + 0.5 0.5tCYCLE + 0.5 0.5tCYCLE + 0.5 0.5tCYCLE + 0.5 tCYCLE (2x_Q Output) Cycle–to–Cycle Variation 2x_Q @ VCC/2 40MHz 66MHz 80MHz 100MHz tCYCLE – 600ps tCYCLE – 300ps tCYCLE – 300ps tCYCLE – 400ps tCYCLE + 600ps tCYCLE + 300ps tCYCLE + 300ps tCYCLE + 400ps tPD2 SYNC Feedback (With 1MΩ from RC1 to An VCC) Condition ns SYNC Input to Feedback Delay 66MHz (Measured at SYNC0 or 1 and 80MHz FEEDBACK Input Pins) 100MHz –1.65 –1.45 –1.25 –1.05 –0.85 –0.65 tSKEWr3 (Rising) See Note 4 Output–to–Output Skew Between Outputs Q0–Q4, Q/2 (Rising Edges Only) — 500 ps All Outputs Into a Matched 50Ω Load Terminated to VCC/2 tSKEWf3 (Falling) Output–to–Output Skew Between Outputs Q0–Q4 (Falling Edges Only) — 750 ps All Outputs Into a Matched 50Ω Load Terminated to VCC/2 tSKEWall3 Output–to–Output Skew 2X_Q, Q/2, Q0–Q4 Rising, Q5 Falling — 750 ps All Outputs Into a Matched 50Ω Load Terminated to VCC/2 tLOCK4 Time Required to Acquire Phase–Lock From Time SYNC Input Signal is Received 1.0 10 ms Also Time to LOCK Indicator High tPZL5 Output Enable Time OE/RST to 2X_Q, Q0–Q4, Q5, and Q/2 3.0 14 ns Measured With the PLL_EN Pin Low tPHZ,tPLZ5 Output Disable Time OE/RST to 2X_Q, Q0–Q4, Q5, and Q/2 3.0 14 ns Measured With the PLL_EN Pin Low 1. 2. 3. 4. TCYCLE in this spec is 1/Frequency at which the particular output is running. The TPD specification’s min/max values may shift closer to zero if a larger pullup resistor is used. Under equally loaded conditions and at a fixed temperature and voltage. With VCC fully powered–on, and an output properly connected to the FEEDBACK pin. tLOCK maximum is with C1 = 0.1µF, tLOCK minimum is with C1 = 0.01µF. 5. The tPZL, tPHZ, tPLZ minimum and maximum specifications are estimates, the final guaranteed values will be available when ‘MC’ status is reached. TIMING SOLUTIONS BR1333 — Rev 6 5 MOTOROLA MC88LV915T Applications Information for All Versions SYNC INPUT (SYNC[1] or SYNC[0]) tCYCLE SYNC INPUT t PD FEEDBACK INPUT Q/2 OUTPUT tSKEWf tSKEWALL tSKEWr tSKEWf tSKEWR Q0 – Q4 OUTPUTS tCYCLE “Q” OUTPUTS Q5 OUTPUT 2X_Q OUTPUT Figure 1. Output/Input Switching Waveforms and Timing Diagrams (These waveforms represent the hook–up configuration of Figure 2a on page 7) Timing Notes: • The MC88LV915T aligns rising edges of the FEEDBACK input and SYNC input, therefore the SYNC input does not require a 50% duty cycle. • All skew specs are measured between the VCC/2 crossing point of the appropriate output edges.All skews are specified as ‘windows’, not as a ± deviation around a center point. • If a “Q” output is connected to the FEEDBACK input (this situation is not shown), the “Q” output frequency would match the SYNC input frequency, the 2X_Q output would run at twice the SYNC frequency, and the Q/2 output would run at half the SYNC frequency. MOTOROLA 6 TIMING SOLUTIONS BR1333 — Rev 6 MC88LV915T 100MHz SIGNAL 25MHz FEEDBACK SIGNAL HIGH LOW 25MHz INPUT CRYSTAL OSCILLATOR EXTERNAL LOOP FILTER RST Q5 FEEDBACK REF_SEL Q4 1:2 Input to “Q” Output Frequency Relationship 2X_Q Q/2 SYNC[0] MC88LV915T ANALOG VCC Q3 RC1 ANALOG GND Q2 FQ_SEL Q0 50MHz “Q” CLOCK OUTPUTS In this application, the Q/2 output is connected to the FEEDBACK input. The internal PLL will line up the positive edges of Q/2 and SYNC, thus the Q/2 frequency will equal the SYNC frequency. The “Q” outputs (Q0–Q4, Q5) will always run at 2X the Q/2 frequency, and the 2X_Q output will run at 4X the Q/2 frequency. Allowable Input Frequency Range: Q1 PLL_EN 5MHz to (2X_Q FMAX Spec)/4 (for FREQ_SEL HIGH) 2.5MHz to (2X_Q FMAX Spec)/8 (for FREQ_SEL LOW) Note: If the OE/RST input is active, a pull–up or pull–down resistor isn’t necessary at the FEEDBACK pin so it won’t when the fed back output goes into 3–state. HIGH HIGH Figure 2a. Wiring Diagram and Frequency Relationships With Q/2 Output Feed Back 100MHz SIGNAL 50MHz FEEDBACK SIGNAL HIGH LOW CRYSTAL OSCILLATOR 50MHZ INPUT EXTERNAL LOOP FILTER RST Q5 FEEDBACK REF_SEL Q4 2X_Q Q/2 SYNC[0] MC88LV915T ANALOG VCC Q3 RC1 ANALOG GND Q2 FQ_SEL Q0 1:1 Input to “Q” Output Frequency Relationship 25MHz SIGNAL Q1 PLL_EN Allowable Input Frequency Range: 10MHz to (2X_Q FMAX Spec)/2 (for FREQ_SEL HIGH) 5MHz to (2X_Q FMAX Spec)/4 (for FREQ_SEL LOW) HIGH HIGH In this application, the Q4 output is connected to the FEEDBACK input. The internal PLL will line up 50MHz the positive edges of Q4 and SYNC, thus the Q4 frequency (and the rest of the “Q” outputs) will “Q” CLOCK equal the SYNC frequency. The Q/2 output will alOUTPUTS ways run at 1/2 the “Q” frequency, and the 2X_Q output will run at 2X the “Q” frequency. Figure 2b. Wiring Diagram and Frequency Relationships With Q4 Output Feed Back 100MHz FEEDBACK SIGNAL HIGH LOW CRYSTAL OSCILLATOR 100MHz INPUT EXTERNAL LOOP FILTER RST Q4 Q5 FEEDBACK REF_SEL MC88LV915T SYNC[0] ANALOG VCC RC1 ANALOG GND FQ_SEL HIGH Q0 2X_Q Q/2 2:1 Input to “Q” Output Frequency Relationship 25MHz SIGNAL Q3 50MHz “Q” CLOCK OUTPUTS Q2 Q1 PLL_EN In this application, the 2X_Q output is connected to the FEEDBACK input. The internal PLL will line up the positive edges of 2X_Q and SYNC, thus the 2X_Q frequency will equal the SYNC frequency. The Q/2 output will always run at 1/4 the 2X_Q frequency, and the “Q” outputs will run at 1/2 the 2X_Q frequency. Allowable Input Frequency Range: HIGH 20MHz to (2X_Q FMAX Spec) (for FREQ_SEL HIGH) 10MHz to (2X_Q FMAX Spec)/2 (for FREQ_SEL LOW) Figure 2c. Wiring Diagram and Frequency Relationships with 2X_Q Output Feed Back TIMING SOLUTIONS BR1333 — Rev 6 7 MOTOROLA MC88LV915T BOARD VCC 47Ω 10µF LOW FREQ BYPASS 0.1µF HIGH FREQ BYPASS 1MΩ 8 ANALOG VCC 9 RC1 330Ω 0.1µF (LOOP FILTER CAP) 10 ANALOG LOOP FILTER/VCO SECTION OF THE MC88LV915T 28–PIN PLCC PACKAGE (NOT DRAWN TO SCALE) ANALOG GND 47Ω BOARD GND A SEPARATE ANALOG POWER SUPPLY IS NOT NECESSARY AND SHOULD NOT BE USED. FOLLOWING THESE PRESCRIBED GUIDELINES IS ALL THAT IS NECESSARY TO USE THE MC88LV915T IN A NORMAL DIGITAL ENVIRONMENT. Figure 3. Recommended Loop Filter and Analog Isolation Scheme for the MC88LV915T Notes Concerning Loop Filter and Board Layout Issues 1. Figure 3 shows a loop filter and analog isolation scheme which will be effective in most applications. The following guidelines should be followed to ensure stable and jitter–free operation: The purpose of the bypass filtering scheme shown in Figure 3 is to give the 88LV915T additional protection from the power supply and ground plane transients that can occur in a high frequency, high speed digital system. 1a.All loop filter and analog isolation components should be tied as close to the package as possible. Stray current passing through the parasitics of long traces can cause undesirable voltage transients at the RC1 pin. 1c.There are no special requirements set forth for the loop filter resistors (1MΩ and 330Ω). The loop filter capacitor (0.1µF) can be a ceramic chip capacitior, the same as a standard bypass capacitor. 1b.The 47Ω resistors, the 10µF low frequency bypass capacitor, and the 0.1µF high frequency bypass capacitor form a wide bandwidth filter that will minimize the 88LV915T’s sensitivity to voltage transients from the system digital VCC supply and ground planes. This filter will typically ensure that a 100mV step deviation on the digital VCC supply will cause no more than a 100pS phase deviation on the 88LV915T outputs. A 250mV step deviation on VCC using the recommended filter values should cause no more than a 250pS phase deviation; if a 25µF bypass capacitor is used (instead of 10µF) a 250mV VCC step should cause no more than a 100pS phase deviation. 1d.The 1M reference resistor injects current into the internal charge pump of the PLL, causing a fixed offset between the outputs and the SYNC input. This also prevents excessive jitter caused by inherent PLL dead–band. If the VCO (2X_Q output) is running above 40MHz, the 1MΩ resistor provides the correct amount of current injection into the charge pump (2–3µA). For the TFN55, 70 or 100, if the VCO is running below 40MHz, a 1.5MΩ reference resistor should be used (instead of 1MΩ). 2. In addition to the bypass capacitors used in the analog filter of Figure 3, there should be a 0.1µF bypass capacitor between each of the other (digital) four VCC pins and the board ground plane. This will reduce output switching noise caused by the 88LV915T outputs, in addition to reducing potential for noise in the ‘analog’ section of the chip. These bypass capacitors should also be tied as close to the 88LV915T package as possible. If good bypass techniques are used on a board design near components which may cause digital VCC and ground noise, the above described VCC step deviations should not occur at the 88LV915T’s digital VCC supply. MOTOROLA 8 TIMING SOLUTIONS BR1333 — Rev 6 MC88LV915T MC88LV915T CMMU CMMU CPU CMMU CMMU CMMU CMMU CMMU CPU CMMU CMMU CMMU CPU CARD PLL CLOCK @f 2f SYSTEM CLOCK SOURCE CPU CARD MC88LV915T PLL DISTRIBUTE CLOCK @ f 2f CLOCK @ 2f AT POINT OF USE MC88LV915T PLL 2f MEMORY CARDS MEMORY CONTROL CLOCK @ 2f AT POINT OF USE Figure 4. Representation of a Potential Multi–Processing Application Utilizing the MC88LV915T for Frequency Multiplication and Low Board–to–Board Skew MC88LV915T System Level Testing Functionality 3–state functionality has been added to the 100MHz version of the MC88LV915T to ease system board testing. Bringing the OE/RST pin low will put all outputs (except for LOCK) into the high impedance state. As long as the PLL_EN pin is low, the Q0–Q4, Q5, and the Q/2 outputs will remain reset in the low state after the OE/RST until a falling SYNC edge is seen. The 2X_Q output will be the inverse of the SYNC signal in this mode. If the 3–state functionality will be used, a pull–up or pull–down resistor must be tied to the FEEDBACK input pin to prevent it from floating when the fedback output goes into high impedance. With the PLL_EN pin low the selected SYNC signal is gated directly into the internal clock distribution network, bypassing and disabling the VCO. In this mode the outputs are directly driven by the SYNC input (per the block diagram). This mode can also be used for low frequency board testing. Note: If the outputs are put into 3–state during normal PLL operation, the loop will be broken and phase–lock will be lost. It will take a maximum of 10mS (tLOCK spec) to regain phase–lock after the OE/RST pin goes back high. TIMING SOLUTIONS BR1333 — Rev 6 9 MOTOROLA MC88LV915T OUTLINE DIMENSIONS FN SUFFIX PLASTIC PACKAGE CASE 776–02 ISSUE D 0.007 (0.180) B T L–M M N S T L–M S S Y BRK –N– 0.007 (0.180) U M N S D Z –M– –L– W 28 D X G1 0.010 (0.250) T L–M S N S S V 1 VIEW D–D A 0.007 (0.180) R 0.007 (0.180) M T L–M S N S C M T L–M S N 0.007 (0.180) H Z M T L–M N S S S K1 E 0.004 (0.100) G J S K SEATING PLANE F VIEW S G1 0.010 (0.250) –T– T L–M S N S M T L–M S N S VIEW S NOTES: 1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). MOTOROLA 0.007 (0.180) 10 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 ––– 0.025 ––– 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 ––– 0.020 2_ 10_ 0.410 0.430 0.040 ––– MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 ––– 0.64 ––– 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 ––– 0.50 2_ 10_ 10.42 10.92 1.02 ––– TIMING SOLUTIONS BR1333 — Rev 6 MC88LV915T Motorola reserves the right to make changes without further notice to any products herein. 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How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405; Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315 Mfax: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://www.mot.com/sps/ ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 TIMING SOLUTIONS BR1333 — Rev 6 ◊ 11 MC88LV915T/D MOTOROLA