MAXIM MAX1204AEPP

19-1179; Rev 0; 1/97
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
The MAX1204 is a 10-bit data-acquisition system
specifically designed for use in applications with mixed
+5V (analog) and +3V (digital) supply voltages. It operates with a single +5V analog supply or dual ±5V analog supplies, and combines an 8-channel multiplexer,
internal track/hold, and serial interface with high conversion speed and low power consumption.
A 4-wire serial interface connects directly to
SPI™/Microwire™ devices without external logic, and a
serial strobe output allows direct connection to
TMS320-family digital signal processors. The MAX1204
uses either the internal clock or an external serialinterface clock to perform successive-approximation
analog-to-digital conversions. The serial interface operates at up to 2MHz.
The MAX1204 features an internal 4.096V reference and
a reference-buffer amplifier that simplifies gain trim. It
also has a VL pin that supplies power to the digital outputs. Output logic levels (3V, 3.3V, or 5V) are determined
by the value of the voltage applied to this pin.
A hard-wired SHDN pin and two software-selectable
power-down modes are provided. Accessing the serial
interface automatically powers up the device. A quick
turn-on time allows the MAX1204 to be shut down
between conversions, enabling the user to optimize
supply currents. By customizing power-down between
conversions, supply current can drop below 10µA at
reduced sampling rates.
The MAX1204 is available in 20-pin SSOP and DIP
packages, and is specified for the commercial, extended, and military temperature ranges.
____________________________Features
♦ 8-Channel Single-Ended or 4-Channel
Differential Inputs
♦ Operates from +5V Single or ±5V Dual Supplies
♦ User-Adjustable Output Logic Levels
(2.7V to 5.25V)
♦ Low Power: 1.5mA (operating mode)
2µA (power-down mode)
♦ Internal Track/Hold, 133kHz Sampling Rate
♦ Internal 4.096V Reference
♦ SPI/Microwire/TMS320-Compatible
4-Wire Serial Interface
♦ Software-Configurable Unipolar/Bipolar Inputs
♦ 20-Pin DIP/SSOP
♦ Pin-Compatible 12-Bit Upgrade: MAX1202
______________Ordering Information
PART
TEMP. RANGE PIN-PACKAGE
INL
(LSB)
MAX1204ACPP
0°C to +70°C
20 Plastic DIP
±1/2
MAX1204BCPP
MAX1204ACAP
MAX1204BCAP
0°C to +70°C
0°C to +70°C
0°C to +70°C
20 Plastic DIP
20 SSOP
20 SSOP
±1
±1/2
±1
Ordering Information continued at end of data sheet.
__________________Pin Configuration
________________________Applications
5V/3V Mixed-Supply Systems
Data Acquisition
Process Control
Battery-Powered Instruments
Medical Instruments
Typical Operating Circuit appears on last page.
SPI is a registered trademark of Motorola, Inc.
Microwire is a registered trademark of National Semiconductor Corp.
TOP VIEW
CH0
1
20 VDD
CH1
2
19 SCLK
CH2
3
CH3
4
CH4
5
16 SSTRB
CH5
6
15 DOUT
CH6
7
14 VL
CH7
8
13 GND
VSS
9
12 REFADJ
18 CS
MAX1204
17 DIN
11 REF
SHDN 10
DIP/SSOP
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
MAX1204
_______________General Description
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V
VL ...............................................................-0.3V to (VDD + 0.3V)
VSS to GND...............................................................+0.3V to -6V
VDD to VSS ..............................................................-0.3V to +12V
CH0–CH7 to GND ............................(VSS - 0.3V) to (VDD + 0.3V)
CH0–CH7 Total Input Current...........................................±20mA
REF to GND ................................................-0.3V to (VDD + 0.3V)
REFADJ to GND .........................................-0.3V to (VDD + 0.3V)
Digital Inputs to GND .................................-0.3V to (VDD + 0.3V)
Digital Outputs to GND .................................-0.3V to (VL + 0.3V)
Digital Output Sink Current .................................................25mA
Continuous Power Dissipation (TA = +70°C)
Plastic DIP (derate 11.11mW/°C above +70°C) ...........889mW
SSOP (derate 8.00mW/°C above +70°C) .....................640mW
CERDIP (derate 11.11mW°C above +70°C) .................889mW
Operating Temperature Ranges
MAX1204_C_P .....................................................0°C to +70°C
MAX1204_E_P ..................................................-40°C to +85°C
MAX1204BMJP ...............................................-55°C to +125°C
Storage Temperature Range .............................-60°C to +150°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +5V ±5%, VL = 2.7V to 3.6V; VSS = 0V or -5V ±5%; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion
cycle (133ksps); 4.7µF capacitor at REF; TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 1)
Resolution
10
Relative Accuracy (Note 2)
INL
Differential Nonlinearity
DNL
Offset Error
Gain Error (Note 3)
Gain Temperature Coefficient
Bits
MAX1204A
±0.5
MAX1204B
±1.0
No missing codes over temperature
±1.0
MAX1204A
±1.0
MAX1204B
±2.0
MAX1204A
±1.0
MAX1204B
±2.0
External reference, 4.096V
Channel-to-Channel
Offset Matching
LSB
LSB
LSB
LSB
±0.8
ppm/°C
±0.1
LSB
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 4.096Vp-p, 133ksps, 2.0MHz external clock, bipolar input mode)
Signal-to-Noise + Distortion Ratio
SINAD
66
dB
Total Harmonic Distortion
(up to the 5th harmonic)
THD
-70
dB
Spurious-Free Dynamic Range
SFDR
70
dB
Channel-to-Channel Crosstalk
VIN = 4.096Vp-p, 65kHz (Note 4)
-75
dB
Small-Signal Bandwidth
-3dB rolloff
4.5
MHz
800
kHz
Full-Power Bandwidth
2
_______________________________________________________________________________________
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
(VDD = +5V ±5%, VL = 2.7V to 3.6V; VSS = 0V or -5V ±5%; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion
cycle (133ksps); 4.7µF capacitor at REF; TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CONVERSION RATE
Conversion Time (Note 5)
tCONV
Track/Hold Acquisition Time
tACQ
Internal clock
External clock, 2MHz, 12 clocks/conversion
5.5
10
6
1.5
µs
µs
Aperture Delay
10
ns
Aperture Jitter
<50
ps
Internal Clock Frequency
1.7
MHz
External Clock-Frequency Range
External compensation mode, 4.7µF
0.1
2.0
Internal compensation mode (Note 6)
0.1
0.4
0
2.0
Used for data transfer only
MHz
ANALOG INPUT
Input Voltage Range, SingleEnded and Differential (Note 7)
Unipolar, VSS = 0V
Multiplexer Leakage Current
On/off leakage current, VCH_ = ±5V
Input Capacitance
(Note 6)
VREF
Bipolar, VSS = -5V
±VREF / 2
±0.01
±1
16
V
µA
pF
INTERNAL REFERENCE
REF Output Voltage
TA = +25°C
4.076
4.096
REF Short-Circuit Current
VREF Temperature Coefficient
Load Regulation (Note 8)
Capacitive Bypass at REF
4.116
V
30
mA
MAX1204AC
±30
±50
MAX1204AE
±30
±60
MAX1204B
±30
0mA to 0.5mA output load
2.5
Internal compensation mode
0
External compensation mode
4.7
Capacitive Bypass at REFADJ
mV
µF
0.01
REFADJ Adjustment Range
ppm/°C
µF
±1.5
%
EXTERNAL REFERENCE AT REF (Buffer disabled, VREF = 4.096V)
2.50
Input Voltage Range
Input Current
VDD +
50mV
200
Input Resistance
12
REF Input Current in Shutdown
REFADJ Buffer Disable Threshold
SHDN = 0V
VDD 50mV
350
µA
10
µA
kΩ
20
1.5
V
V
_______________________________________________________________________________________
3
MAX1204
ELECTRICAL CHARACTERISTICS (continued)
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
ELECTRICAL CHARACTERISTICS (continued)
VDD = +5V ±5%, VL = 2.7V to 3.6V; VSS = 0V or -5V ±5%; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion
cycle (133ksps); 4.7µF capacitor at REF; TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
EXTERNAL REFERENCE AT REFADJ
Capacitive Bypass at REF
Internal compensation mode
0
External compensation mode
4.7
Reference-Buffer Gain
µF
1.68
REFADJ Input Current
V/V
±50
POWER REQUIREMENTS
4
µA
Positive Supply Voltage
VDD
Negative Supply Voltage
VSS
Positive Supply Current
IDD
Negative Supply Current
ISS
Logic Supply Voltage
VL
Logic Supply Current (Notes 6, 10)
IVL
Positive Supply Rejection
(Note 11)
µA
5 ±5%
V
0 or -5 ±5%
V
Operating mode
1.5
2.5
Fast power-down (Note 9)
30
70
Full power-down (Note 9)
2
10
Operating mode and fast power-down
50
Full power-down
10
2.70
VL = VDD = 5V
mA
µA
µA
5.25
V
10
µA
PSR
VDD = 5V ±5%; external reference, 4.096V;
full-scale input
±0.06
±0.5
mV
Negative Supply Rejection
(Note 11)
PSR
VSS = -5V ±5%; external reference, 4.096V;
full-scale input
±0.01
±0.5
mV
Logic Supply Rejection
(Note 12)
PSR
External reference, 4.096V; full-scale input
±0.06
±0.5
mV
_______________________________________________________________________________________
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
(VDD = +5V ±5%, VL = 2.7V to 5.25V; VSS = 0V or -5V ±5%; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion
cycle (133ksps); 4.7µF capacitor at REF; TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER
SYMBOL
DIN, SCLK, CS Input High Voltage
VIH
DIN, SCLK, CS Input Low Voltage
VIL
CONDITIONS
DIGITAL INPUTS: DIN, SCLK, CS, SHDN
DIN, SCLK, CS Input Hysteresis
DIN, SCLK, CS Input Leakage
MIN
MAX
2.0
VHYST
VIN = 0V or VDD
DIN, SCLK, CS Input Capacitance
CIN
(Note 6)
SHDN Input High Voltage
VSH
VDD - 0.5
SHDN Input Mid-Voltage
VSM
1.5
SHDN Voltage, Floating
VFLT
SHDN Input Low Voltage
VSL
SHDN Input Current, High
ISH
SHDN = VDD
SHDN Input Current, Low
ISL
SHDN = 0V
-4.0
SHDN = open
-100
SHDN = open
UNITS
V
0.8
V
±1
µA
15
pF
0.15
IIN
SHDN Maximum Allowed
Leakage, Mid-Input
TYP
V
V
VDD - 1.5
2.75
V
V
0.5
V
4.0
µA
µA
100
nA
DIGITAL OUTPUTS: DOUT, SSTRB (VL = 2.7V to 3.6V)
Output Voltage Low
VOL
Output Voltage High
VOH
Three-State Leakage Current
Three-State Output Capacitance
IL
COUT
ISINK = 3mA
0.4
ISINK = 6mA
ISOURCE = 1mA
0.3
VL - 0.5
V
V
CS = VL
CS = VL (Note 6)
±10
µA
15
pF
DIGITAL OUTPUTS: DOUT, SSTRB (VL = 4.75V to 5.25V)
Output Voltage Low
VOL
Output Voltage High
VOH
Three-State Leakage Current
Three-State Output Capacitance
IL
COUT
ISINK = 5mA
0.4
ISINK = 8mA
ISOURCE = 1mA
CS = 5V
CS = 5V (Note 6)
0.3
4
V
V
±10
µA
15
pF
_______________________________________________________________________________________
5
MAX1204
ELECTRICAL CHARACTERISTICS
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
TIMING CHARACTERISTICS
(VDD = +5V ±5%, VL = 2.7V to 3.6V, VSS = 0V or -5V ±5%, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
Acquisition Time
DIN to SCLK Setup
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
tACQ
1.5
µs
tDS
100
ns
DIN to SCLK Hold
tDH
SCLK Fall to Output Data Valid
tDO
CLOAD = 100pF
0
ns
240
CS Fall to Output Enable
tDV
ns
CLOAD = 100pF
240
CS Rise to Output Disable
tTR
ns
CLOAD = 100pF
240
ns
20
CS to SCLK Rise Setup
tCSS
100
ns
CS to SCLK Rise Hold
tCSH
0
ns
SCLK Pulse Width High
tCH
200
ns
SCLK Pulse Width Low
tCL
200
ns
SCLK Fall to SSTRB
CLOAD = 100pF
240
ns
tSDV
External clock mode only, CLOAD = 100pF
240
ns
CS Rise to SSTRB Output
Disable (Note 6)
tSTR
External clock mode only, CLOAD = 100pF
240
ns
SSTRB Rise to SCLK Rise
(Note 6)
tSCK
Internal clock mode only
CS Fall to SSTRB Output Enable
(Note 6)
tSSTRB
0
ns
Tested at VDD = 5.0V; VSS = 0V; unipolar input mode.
Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is
calibrated.
Note 3: Internal reference, offset nulled.
Note 4: On-channel grounded; sine-wave applied to all off-channels.
Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: Guaranteed by design. Not subject to production testing.
Note 7: Common-mode range for analog inputs is from VSS to VDD.
Note 8: External load should not change during the conversion for specified accuracy.
Note 9: Shutdown supply current is measured with VL at 3.3V, and with all digital inputs tied to either VL or GND (Figure 12c);
REFADJ = GND.
Note 10: Logic supply current is measured with the digital outputs (DOUT and SSTRB) disabled (CS high). When the outputs are
active (CS low), the logic supply current depends on fSCLK, and on the static and capacitive load at DOUT and SSTRB.
Note 11: Measured at VSUPPLY +5% and VSUPPLY -5% only.
Note 12: Measured at VL = 2.7V and VL = 3.6V.
Note 1:
Note 2:
6
_______________________________________________________________________________________
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
1.6
1.4
1.2
1.0
1.8
1.6
1.4
1.2
1.0
4.5
4.7
4.9
5.1
5.3
5.5
6
REFADJ = GND
SHUTDOWN SUPPLY CURRENT (µA)
1.8
MAX1204 TOC02
MAX1204 TOC01
2.0
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
2.0
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
SUPPLY CURRENT
vs. TEMPERATURE
MAX1204 TOC03
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
5
4
3
2
1
0
-60
SUPPLY VOLTAGE (V)
-20
20
60
100
140
TEMPERATURE (°C)
-60
-20
20
60
100
140
TEMPERATURE (°C)
______________________________________________________________Pin Description
PIN
NAME
1–8
CH0–CH7
9
VSS
FUNCTION
Sampling Analog Inputs
Negative Supply Voltage. Tie VSS to -5V ±5% or GND.
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1204 down to 10µA (max) supply
current; otherwise, the MAX1204 is fully operational. Pulling SHDN to VDD puts the reference-buffer
amplifier in internal compensation mode. Letting SHDN float puts the reference-buffer amplifier in
external compensation mode.
10
SHDN
11
REF
12
REFADJ
13
GND
14
VL
15
DOUT
Serial-Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.
16
SSTRB
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX1204 begins the analogto-digital conversion and goes high when the conversion is finished. In external clock mode, SSTRB
pulses high for one clock period before the MSB decision. High impedance when CS is high (external
clock mode).
17
DIN
Serial-Data Input. Data is clocked in at SCLK’s rising edge.
18
CS
Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is high, DOUT is
high impedance.
19
SCLK
20
VDD
Reference Buffer Output/ADC Reference Input. In internal reference mode, the reference buffer
provides a 4.096V nominal output, externally adjustable at REFADJ. In external reference mode,
disable the internal buffer by pulling REFADJ to VDD.
Input to the Reference-Buffer Amplifier. Tie REFADJ to VDD to disable the reference-buffer amplifier.
Ground; IN- Input for Single-Ended Conversions
Supply Voltage for Digital Output Pins. Voltage applied to VL determines the positive output swing of
the Digital Outputs (DOUT, SSTRB).
Serial-Clock Input. SCLK clocks data in and out of serial interface. In external clock mode, SCLK also
sets the conversion speed. (Duty cycle must be 40% to 60% in external clock mode.)
Positive Supply Voltage, +5V ±5%
_______________________________________________________________________________________
7
MAX1204
__________________________________________Typical Operating Characteristics
(VDD = 5V ±5%; VL = 2.7V to 3.6V; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
4.7µF capacitor at REF; TA = +25°C; unless otherwise noted.)
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
+3.3V
DOUT
DOUT
3k
3k
CLOAD
CLOAD
GND
GND
a. High-Z to VOH and VOL to VOH
b. High-Z to VOL and VOH to VOL
Figure 1. Load Circuits for Enable Time
+3.3V
3k
DOUT
CS
SCLK
18
19
DIN
17
SHDN
10
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
1
2
3
4
5
6
7
8
GND
13
DOUT
3k
CLOAD
GND
INPUT
SHIFT
REGISTER
INT
CLOCK
CONTROL
LOGIC
OUTPUT
SHIFT
REGISTER
ANALOG
INPUT
MUX
REFADJ
12
REF
11
16
DOUT
SSTRB
T/H
CLOCK
IN SAR
ADC
OUT
REF
+2.44V
REFERENCE
CLOAD
15
20k
A ≈ 1.68
20
14
9
+4.096V
VDD
VL
VSS
MAX1204
GND
a. VOH to High-Z
b. VOL to High-Z
Figure 2. Load Circuits for Disable Time
Figure 3. Block Diagram
_______________Detailed Description
GND during a conversion. To do this, connect a 0.1µF
capacitor from IN- (of the selected analog input) to
GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the input control word’s
last bit is entered. The T/H switch opens at the end of
the acquisition interval, retaining charge on CHOLD as a
sample of the signal at IN+.
The MAX1204 uses a successive-approximation conversion technique and input track/hold (T/H) circuitry to
convert an analog signal to a 10-bit digital output. A
flexible serial interface provides easy interface to 3V
microprocessors (µPs). Figure 3 is the MAX1204 block
diagram.
Pseudo-Differential Input
Figure 4 shows the analog-to-digital converter’s
(ADC’s) analog comparator’s sampling architecture. In
single-ended mode, IN+ is internally switched to
CH0–CH7 and IN- is switched to GND. In differential
mode, IN+ and IN- are selected from pairs of CH0/CH1,
CH2/CH3, CH4/CH5, and CH6/CH7. Configure the
channels using Tables 3 and 4.
In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential such that only the signal at IN+ is
sampled. The return side (IN-) must remain stable within ±0.5LSB (±0.1LSB for best results) with respect to
8
The conversion interval begins with the input multiplexer switching CHOLD from the positive input (IN+) to the
negative input (IN-). In single-ended mode, IN- is simply GND. This unbalances node ZERO at the comparator’s input. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node
ZERO to 0V within the limits of 10-bit resolution. This
action is equivalent to transferring a charge of 16pF x
[(VIN+) - (VIN-)] from C HOLD to the binary-weighted
capacitive DAC, which in turn forms a digital representation of the analog input signal.
_______________________________________________________________________________________
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
The time required for the T/H to acquire an input signal is
a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
acquisition time increases and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal, and is also the minimum time needed for the
signal to be acquired. It is calculated by the following:
tACQ = 7 x (RS + RIN) x 16pF
where RIN = 9kΩ, RS = the source impedance of the
input signal, and tACQ is never less than 1.5µs. Note that
source impedances below 4kΩdo not significantly affect
the ADC’s AC performance. Higher source impedances
VL
+3V
can be used if an input capacitor is connected to the
analog inputs, as shown in Figure 5. Note that the input
capacitor forms an RC filter with the input source impedance, limiting the ADC’s signal bandwidth.
CAPACITIVE DAC
REF
CH0
CH1
INPUT
MUX
CH4
CH5
ZERO
16pF
CH2
CH3
COMPARATOR
CHOLD
–
+
CSWITCH
9k
RIN
HOLD
TRACK
CH6
CH7
T/H
SWITCH
GND
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN– CHANNEL.
SINGLE-ENDED MODE: IN+ = CHO–CH7, IN- = GND.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4/CH5, CH6/CH7.
Figure 4. Equivalent Input Circuit
VDD
+5V
OSCILLOSCOPE
0.1µF
0.1µF
GND
MAX1204
0V TO
4.096V
ANALOG 0.01µF
INPUT
CH7
SCLK
VSS
SSTRB
CS
DOUT
SCLK
+3V
DIN
2MHz
OSCILLATOR
CH1
CH2
CH3
CH4
SSTRB
C2
0.01µF
REFADJ
DOUT
REF
SHDN
N.C.
C1
4.7µF
FULL-SCALE ANALOG INPUT
Figure 5. Quick-Look Circuit
_______________________________________________________________________________________
9
MAX1204
Track/Hold
The T/H enters tracking mode on the falling clock edge
after the fifth bit of the 8-bit control word is shifted in. The
T/H enters hold mode on the falling clock edge after the
eighth bit of the control word is shifted in. IN- is connected to GND if the converter is set up for single-ended
inputs, and the converter samples the “+” input. IN- connects to the “-” input if the converter is set up for differential inputs, and the difference of  |N+ - IN- is sampled.
The positive input connects back to IN+ at the end of
the conversion, and CHOLD charges to the input signal.
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
Table 1a. Unipolar Full Scale
and Zero Scale
REFERENCE
Internal
External
ZERO
SCALE
Table 1b. Bipolar Full Scale, Zero Scale,
and Negative Full Scale
FULL SCALE
0V
+4.096V
at REFADJ
0V
VREFADJ x 1.68
at REF
0V
VREF
REFERENCE
Internal
External
-4.096V/2
at
REFADJ
at REF
Input Bandwidth
The ADC’s input tracking circuitry has a 4.5MHz
small-signal bandwidth. Therefore, it is possible to digitize high-speed transient events and measure periodic
signals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Analog Input Range and Input Protection
Internal protection diodes, which clamp the analog
inputs to VDD and VSS, allow the analog input pins to
swing from (VSS - 0.3V) to (VDD + 0.3V) without damage. However, for accurate conversions near full scale,
the inputs must not exceed VDD by more than 50mV, or
be lower than VSS by 50mV.
If the analog input exceeds 50mV beyond the supplies, do not forward bias the protection diodes of
off-channels over 2mA, as excessive current
degrades on-channel conversion accuracy.
The full-scale input voltage depends on the voltage at
REF (Tables 1a and 1b).
Quick Look
Use the circuit of Figure 5 to quickly evaluate the
MAX1204’s analog performance. The MAX1204 requires
that a control byte be written to DIN before each conversion. Tying DIN to +3V feeds in control byte $FF hex,
10
NEGATIVE
ZERO
FULL SCALE
FULL SCALE SCALE
0V
+4.096V / 2
-1/2 VREFADJ x
1.68
0V
+1/2 VREFADJ
x 1.68
-1/2 VREF
0V
+1/2 VREF
which triggers single-ended unipolar conversions on
CH7 in external clock mode without powering down
between conversions. In external clock mode, the
SSTRB output pulses high for one clock period before
the most significant bit of the conversion result shifts out
of DOUT. Varying the analog input to CH7 alters the
sequence of bits from DOUT. A total of 15 clock cycles
per conversion is required. All SSTRB and DOUT output
transitions occur on SCLK’s falling edge.
How to Start a Conversion
Clocking a control byte into DIN starts conversion on
the MAX1204. With CS low, each rising edge on SCLK
clocks a bit from DIN into the MAX1204’s internal shift
register. After CS falls, the first logic “1” bit defines the
control byte’s MSB. Until this first “start” bit arrives, any
number of logic “0” bits can be clocked into DIN with
no effect. Table 2 shows the control-byte format.
The MAX1204 is fully compatible with Microwire and SPI
devices. For SPI, select the correct clock polarity and
sampling edge in the SPI control registers: set CPOL =
0 and CPHA = 0. Microwire and SPI both transmit a byte
and receive a byte at the same time. Using the Typical
Operating Circuit , the simplest software interface
requires only three 8-bit transfers to perform a conversion (one 8-bit transfer to configure the ADC, and two
more 8-bit transfers to clock out the conversion result).
______________________________________________________________________________________
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
MAX1204
Table 2. Control-Byte Format
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
START
SEL 2
SEL 1
SEL 0
UNI/BIP
SGL/DIF
PD1
PD0
Bit
Name
7 (MSB)
START
6
5
4
SEL2
SEL1
SEL0
3
UNI/BIP
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an
analog input signal from 0V to VREF can be converted; in bipolar mode, the signal can range
from -VREF / 2 to +VREF / 2.
2
SGL/DIF
1 = single ended, 0 = differential. Selects single-ended or differential conversions. In singleended mode, input signal voltages are referred to GND. In differential mode, the voltage difference between two channels is measured. (Tables 3 and 4.)
1
0 (LSB)
Description
The first logic 1 bit after CS goes low defines the beginning of the control byte.
These three bits select which of the eight channels is used for the conversion
(Tables 3 and 4).
Selects clock and power-down modes.
PD1
PD0
Mode
0
0
Full power-down (IDD = 2µA, internal reference)
0
1
Fast power-down (IDD = 30µA, internal reference)
1
0
Internal clock mode
1
1
External clock mode
PD1
PD0
Table 3. Channel Selection in Single-Ended Mode (SGL/DIF = 1)
SEL2
SEL1
SEL0
CH0
0
0
0
+
1
0
0
0
0
1
1
0
1
0
1
0
1
1
0
0
1
1
1
1
1
CH1
CH2
CH3
CH4
CH5
CH6
CH7
GND
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
Table 4. Channel Selection in Differential Mode (SGL/DIF = 0)
SEL2
SEL1
SEL0
CH0
CH1
0
0
0
+
–
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
–
CH2
CH3
+
–
CH4
CH5
+
–
CH6
CH7
+
–
–
+
+
–
+
–
+
______________________________________________________________________________________
11
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
Simple Software Interface
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.
1) Set up the control byte for external clock mode and
call it TB1. TB1’s format should be: 1XXXXX11 binary,
where the Xs denote the particular channel and
conversion mode selected.
2) Use a general-purpose I/O line on the CPU to pull
CS on the MAX1204 low.
3) Transmit TB1 and simultaneously receive a byte
and call it RB1. Ignore RB1.
4) Transmit a byte of all zeros ($00 hex) and simultaneously receive byte RB2.
5) Transmit a byte of all zeros ($00 hex) and simultaneously receive byte RB3.
6) Pull CS on the MAX1204 high.
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion padded
with one leading zero, two trailing sub-bits (S1 and S0),
and three trailing zeros. Total conversion time is a function of the serial clock frequency and the amount of idle
time between 8-bit transfers. To avoid excessive T/H
droop, make sure that the total conversion time does
not exceed 120µs.
Digital Output
In unipolar input mode, the output is straight binary
(Figure 15); for bipolar inputs, the output is two’scomplement (Figure 16). Data is clocked out at SCLK’s
falling edge in MSB-first format. The digital output logic
level is adjusted with the VL pin. This allows DOUT and
SSTRB to interface with 3V logic without the risk of
overdrive. The MAX1204’s digital inputs are designed
to be compatible with 3V CMOS logic as well as 5V
logic.
Internal and External Clock Modes
The MAX1204 can use either an external serial clock
or the internal clock to perform the successiveapproximation conversion. In both clock modes, the
external clock shifts data in and out of the MAX1204.
The T/H acquires the input signal as the last three bits
of the control byte are clocked into DIN. Bits PD1 and
PD0 of the control byte program the clock mode.
Figures 7–10 show the timing characteristics common
to both modes.
12
External Clock
In external clock mode, the external clock not only shifts
data in and out, but it also drives the A/D conversion
steps. SSTRB pulses high for one clock period after the
last bit of the control byte. Successive-approximation bit
decisions are made and appear at DOUT on each of the
next 12 SCLK falling edges (Figure 6). SSTRB and
DOUT go into a high-impedance state when CS goes
high; after the next CS falling edge, SSTRB outputs a
logic low. Figure 8 shows the SSTRB timing in external
clock mode.
The conversion must complete in some minimum time or
droop on the sample-and-hold can degrade conversion
results. Use internal clock mode if the clock period
exceeds 10µs or if serial-clock interruptions could cause
the conversion interval to exceed 120µs.
Internal Clock
In internal clock mode, the MAX1204 generates its own
conversion clock. This frees the µP from running the
SAR conversion clock, and allows the conversion
results to be read back at the processor’s convenience,
at any clock rate from zero to 2MHz. SSTRB goes low
at the start of the conversion, then goes high when the
conversion is complete. SSTRB is low for a maximum of
10µs, during which time SCLK should remain low for
best noise performance. An internal register stores data
while the conversion is in progress. SCLK clocks the
data out at this register at any time after the conversion
is complete. After SSTRB goes high, the next falling
clock edge produces the MSB of the conversion at
DOUT, followed by the remaining bits in MSB-first format (Figure 9). CS does not need to be held low once a
conversion is started. Pulling CS high prevents data
from being clocked into the MAX1204 and three-states
DOUT, but it does not adversely affect an internal
clock-mode conversion already in progress. When
internal clock mode is selected, SSTRB does not go
high impedance when CS goes high.
Figure 10 shows the SSTRB timing in internal clock
mode. Data can be shifted in and out of the MAX1204 at
clock rates up to 2.0MHz if the acquisition time, tACQ, is
kept above 1.5µs.
______________________________________________________________________________________
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
MAX1204
CS
tACQ
SCLK
1
4
8
12
16
20
24
UNI/ SGL/
SEL2 SEL1 SEL0 BIP DIF PD1 PD0
DIN
START
SSTRB
RB3
RB2
RB1
B9
MSB
DOUT
ADC STATE
B8
B7
B6
ACQUISITION
1.5µs
(SCLK = 2MHz)
IDLE
B5
B4
B3
B2
B1
B0
LSB
S1
S0
CONVERSION
FILLED WITH
ZEROS
IDLE
Figure 6. 24-Bit External-Clock-Mode Conversion Timing (Microwire/SPI Compatible)
•••
CS
tCSH
tCSS
tCH
tCL
tCSH
•••
SCLK
tDS
tDH
•••
DIN
tDV
tDO
tTR
•••
DOUT
Figure 7. Detailed Serial-Interface Timing
CS
SSTRB
•••
•••
•••
•••
tSTR
tSDV
tSSTRB
SCLK
•••
tSSTRB
•••
PD0 CLOCKED IN
Figure 8. External Clock-Mode SSTRB Detailed Timing
______________________________________________________________________________________
13
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
CS
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
18
19
20
21
22
23
24
SGL/
SEL2 SEL1 SEL0 UNI/
DIP DIF PD1 PD0
DIN
START
SSTRB
tCONV
B9
MSB
DOUT
ACQUISITION CONVERSION
1.5µs
10µs MAX
(SCLK = 2MHz)
IDLE
ADC STATE
B8
B7
B0
LSB
S1
S0
FILLED WITH
ZEROS
IDLE
Figure 9. Internal Clock Mode Timing
CS • • •
tCONV
tCSS
tSCK
tCSH
SSTRB • • •
tSSTRB
SCLK • • •
PD0 CLOCK IN
NOTE: KEEP SCLK LOW DURING CONVERSION FOR BEST NOISE PERFORMANCE.
Figure 10. Internal Clock Mode SSTRB Detailed Timing
Data Framing
CS’s falling edge does not start a conversion on the
MAX1204. The first logic high clocked into DIN is interpreted as a start bit and defines the first bit of the control
byte. A conversion starts on SCLK’s falling edge after the
eighth bit of the control byte (the PD0 bit) is clocked into
DIN. The start bit is defined as:
The first high bit clocked into DIN with CS low anytime the converter is idle; (e.g., after VDD is applied).
or
MAX1204 can run is 15 clocks/conversion. Figure 11a
shows the serial-interface timing necessary to perform
a conversion every 15 SCLK cycles in external clock
mode. If CS is low and SCLK is continuous, guarantee
a start bit by first clocking in 16 zeros.
Most microcontrollers (µCs) require that conversions
occur in multiples of eight SCLK clocks; 16 clocks per
conversion is typically the fastest that a µC can drive
the MAX1204. Figure 11b shows the serial-interface
timing necessary to perform a conversion every 16
SCLK cycles in external clock mode.
The first high bit clocked into DIN after bit 3 (B3) of a
conversion in progress appears at DOUT.
If a falling edge on CS forces a start bit before B3
becomes available, the current conversion is terminated and a new one started. Thus, the fastest the
14
______________________________________________________________________________________
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
MAX1204
CS
1
8
15 1
8
15
1
SCLK
S
DIN
CONTROL BYTE 0
DOUT
S
S
CONTROL BYTE 1
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
CONTROL BYTE 2
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
CONVERSION RESULT 1
CONVERSION RESULT 0
SSTRB
Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing
CS
•••
SCLK
•••
DIN
DOUT
S
S
CONTROL BYTE 0
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
CONVERSION RESULT 0
•••
CONTROL BYTE 1
B9
B8 B7 B6 B5 • • •
CONVERSION RESULT 1
Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing
__________ Applications Information
Power-On Reset
When power is first applied and if SHDN is not pulled
low, internal power-on reset circuitry activates the
MAX1204 in internal clock mode, ready to convert with
SSTRB = high. After the power supplies are stabilized,
the internal reset time is 100µs. No conversions should
be performed during this phase. SSTRB is high on
power-up, and if CS is low, the first logical 1 on DIN is
interpreted as a start bit. Until a conversion takes
place, DOUT shifts out zeros.
Reference-Buffer Compensation
In addition to its shutdown function, SHDN also selects
internal or external compensation. The compensation
affects both power-up time and maximum conversion
speed. Compensated or not, the minimum clock rate is
100kHz due to droop on the sample-and-hold.
Float SHDN to select external compensation. The Typical
Operating Circuit uses a 4.7µF capacitor at REF. A value
of 4.7µF or greater ensures stability and allows converter
operation at the 2MHz full clock speed. External compensation increases power-up time (see the section
Choosing Power-Down Mode, and Table 5).
Internal compensation requires no external capacitor at
REF, and is selected by pulling SHDN high. Internal compensation allows for the shortest power-up times, but is
only available using an external clock up to 400kHz.
Power-Down
Choosing Power-Down Mode
You can save power by placing the converter in a
low-current shutdown state between conversions.
Select full power-down or fast power-down mode via
bits 1 and 0 of the DIN control byte with SHDN high or
floating (Tables 2 and 6). Pull SHDN low at any time to
______________________________________________________________________________________
15
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
shut down the converter completely. SHDN overrides
bits 1 and 0 of the control byte.
Full power-down mode turns off all chip functions
that draw quiescent current, reducing IDD and ISS typically to 2µA.
Fast power-down mode turns off all circuitry except the
bandgap reference. With fast power-down mode, the
supply current is 30µA. Power-up time can be shortened
to 5µs in internal compensation mode.
The IDD shutdown current can increase if any digital input
(DIN, SCLK, CS) is held high in either power-down mode.
The actual shutdown current depends on the state of the
digital inputs, the voltage applied to the digital inputs
(VIH), the supply voltage (VDD), and the operating temperature. Figure 12c shows the maximum IDD increase for
each digital input held high in power-down mode for different operating conditions. This current is cumulative, so if
all three digital inputs are held high, the additional shutdown current is three times the value shown in Figure 12c.
In both software power-down modes, the serial interface
remains operational, but the ADC does not convert.
Table 5 shows how the choice of reference-buffer compensation and power-down mode affects both power-up
delay and maximum sample rate.
In external compensation mode, power-up time is 20ms
with a 4.7µF compensation capacitor (200ms with a 33µF
capacitor) when the capacitor is initially fully discharged.
From fast power-down, start-up time can be eliminated
by using low-leakage capacitors that do not discharge
more than 1/2LSB while shut down. In power-down, the
capacitor has to supply the current into the reference
(typically 1.5µA) and the transient currents at power-up.
Figures 12a and 12b show the various power-down
sequences in both external and internal clock modes.
Software Power-Down
Software power-down is activated using bits PD1 and
PD0 of the control byte. As shown in Table 6, PD1 and
PD0 also specify clock mode. When software powerdown is asserted, the ADC continues to operate in the
last specified clock mode until the conversion is complete. The ADC then powers down into a low
quiescent-current state. In internal clock mode, the
interface remains active and conversion results can be
clocked out even though the MAX1204 has already
entered a software power-down.
The first logical 1 on DIN is interpreted as a start bit
and powers up the MAX1204. Following the start bit,
the control byte also determines clock and power-down
modes. For example, if the control byte contains PD1 =
1, the chip remains powered up. If PD1 = 0,
power-down resumes after one conversion.
Table 5. Typical Power-Up Delay Times
POWER-UP
DELAY (µs)
MAXIMUM
SAMPLING RATE
(ksps)
Fast
5
26
Full
300
26
Fast/Full
See Figure 14c
133
Disabled
Fast
2
133
Disabled
Full
2
133
REFERENCE
BUFFER
REFERENCE-BUFFER
COMPENSATION MODE
Enabled
Internal
Enabled
Internal
Enabled
External
REFERENCE
CAPACITOR
(µF)
4.7
Table 6. Software Shutdown and
Clock Mode
16
DEVICE MODE
POWER-DOWN
MODE
Table 7. Hard-Wired Shutdown and
Compensation Mode
SHDN
DEVICE
MODE
REFERENCE-BUFFER
COMPENSATION
PD1
PD0
1
1
External clock mode
VDD
Enabled
Internal compensation
1
0
Internal clock mode
Floating
Enabled
External compensation
0
1
Fast power-down mode
0
0
Full power-down mode
GND
Full
Power-Down
N/A
STATE
______________________________________________________________________________________
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
INTERNAL
MAX1204
CLOCK
MODE
EXTERNAL
EXTERNAL
SHDN
SETS FAST
POWER-DOWN
MODE
SETS EXTERNAL
CLOCK MODE
DIN
S X X X X X 1 1
DOUT
SETS EXTERNAL
CLOCK MODE
SX X XX X 0 1
S XX XXX 1 1
DATA VALID
(10 + 2 DATA BITS)
DATA VALID
(10 + 2 DATA BITS)
POWERED UP
MODE
DATA
INVALID
POWERED UP
FAST
POWER-DOWN
FULL
POWERDOWN
POWERED
UP
Figure 12a. Timing Diagram for Power-Down Modes (External Clock)
CLOCK
MODE
DIN
INTERNAL CLOCK MODE
S X X X X X 1 0
SX X XX X 0 0
DOUT
SSTRB
MODE
SETS FULL
POWER-DOWN
SETS INTERNAL
CLOCK MODE
S
DATA VALID
DATA VALID
CONVERSION
CONVERSION
POWERED UP
FULL
POWER-DOWN
POWERED
UP
Figure 12b. Timing Diagram for Power-Down Modes (Internal Clock)
Hardware Power-Down
The SHDN pin places the converter into full
power-down mode. Unlike the software power-down
modes, conversion is not completed; it stops coincidentally with SHDN being brought low. There is no
power-up delay if an external reference, which is not
shut down, is used. SHDN also selects internal or
external reference compensation (Table 7).
Power-Down Sequencing
The MAX1204’s automatic power-down modes can
save considerable power when operating at less than
maximum sample rates. The following sections discuss
the various power-down sequences.
Lowest Power at up to
500 Conversions per Channel per Second
Figure 14a depicts MAX1204’s power consumption for one
or eight channel conversions using full power-down mode
and internal reference compensation. A 0.01µF bypass
capacitor at REFADJ forms an RC filter with the internal
20kΩ reference resistor, with a 0.2ms time constant. To
achieve full 10-bit accuracy, 10 time constants (or 2ms in
this example) are required for the reference buffer to settle.
When exiting FULLPD, waiting this 2ms in FASTPD mode
(instead of just exiting FULLPD mode and returning to normal operating mode) reduces power consumption by a
factor of 10 or more (Figure 13).
______________________________________________________________________________________
17
Lowest Power at Higher Throughputs
Figure 14b shows power consumption with externalreference compensation in fast power-down, with one and
eight channels converted. The external 4.7µF compensation requires a 50µs wait after power-up. This circuit combines fast multichannel conversion with the lowest power
consumption possible. Full power-down mode can
increase power savings in applications where the
MAX1204 is inactive for long periods of time, but where
intermittent bursts of high-speed conversions are required.
External and Internal References
The MAX1204 can be used with an internal or external
reference. An external reference can be connected
directly at the REF terminal or at the REFADJ pin.
40
SUPPLY CURRENT PER INPUT (µA)
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
35
(VDD - VIH) = 2.55V
30
An internal buffer is designed to provide 4.096V at REF
for the MAX1204. Its internally trimmed 2.44V reference
is buffered with a 1.68 nominal gain.
Internal Reference
The MAX1204’s full-scale range with internal reference is
4.096V with unipolar inputs and ±2.048V with bipolar
inputs. The internal reference voltage is adjustable to
±1.5% with the circuit of Figure 17.
External Reference
An external reference can be placed at either the input
(REFADJ) or the output (REF) of the MAX1204’s internal
buffer amplifier. The REFADJ input impedance is typically 20kΩ. At REF, the input impedance is a minimum of
12kΩ for DC currents. During conversion, an external
reference at REF must deliver up to 350µA DC load current and have an output impedance of 10Ω or less. If the
reference has higher output impedance or is noisy,
bypass it close to the REF pin with a 4.7µF capacitor.
Using the buffered REFADJ input makes buffering of
the external reference unnecessary. To use the direct
REF input, disable the internal buffer by tying REFADJ
to V DD . In power-down, the input bias current to
REFADJ can be as much as 25µA with REFADJ tied to
VDD. Pull REFADJ to GND to minimize the input bias
current in power-down.
25
20
15
(VDD - VIH) = 2.25V
10
(VDD - VIH) = 1.95V
5
Transfer Function and Gain Adjust
0
Figure 15 depicts the nominal, unipolar input/output
(I/O) transfer function, and Figure 16 shows the bipolar
I/O transfer function. Code transitions occur halfway
between successive integer LSB values. Output coding
is binary with 1 LSB = 4mV (4.096V/1024) for
unipolar operation and 1 LSB = 4mV [(4.096V/2 -4.096V/2)/1024] for bipolar operation.
-20
-60
20
60
100
140
TEMPERATURE (°C)
Figure 12c. Additional IDD Shutdown Supply Current vs. V IH
for Each Digital Input at a Logic 1
COMPLETE CONVERSION SEQUENCE
2ms WAIT
DIN
CH1
(ZEROS)
1
00
FULLPD
1
01
FASTPD
1
(ZEROS)
CH7
11
NOPD
1
00
FULLPD
2.5V
REFADJ
0V
4V
τ = RC = 20kΩ x CREFADJ
REF
0V
tBUFFEN ≈ 15µs
Figure 13. MAX1204 FULLPD/FASTPD Power-Up Sequence
18
______________________________________________________________________________________
1
01
FASTPD
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
3.0
2.5
POWER-UP DELAY (ms)
8 CHANNELS
MAX186-14A
AVERAGE SUPPLY CURRENT (µA)
2ms FASTPD WAIT
400kHz EXTERNAL CLOCK
INTERNAL COMPENSATION
MAX1204
FULL POWER-DOWN
1000
100
1 CHANNEL
10
2.0
1.5
1.0
0.5
0
1
0
50 100 150 200 250 300 350 400 450 500
CONVERSIONS PER CHANNEL PER SECOND
Figure 14a. MAX1204 Supply Current vs. Sample Rate/Second,
FULLPD, 400kHz Clock
AVERAGE SUPPLY CURRENT (µA)
10,000
8 CHANNELS
1000
1 CHANNEL
2MHz EXTERNAL CLOCK
EXTERNAL COMPENSATION
50µs WAIT
10
0
2k
4k
6k
8k
10k
12k
14k
16k
0.001
0.01
0.1
1
10
TIME IN SHUTDOWN (sec)
Figure 14c. Typical Power-Up Delay vs. Time in Shutdown
(especially clock) lines parallel to one another, or digital
lines underneath the ADC package.
Figure 18 shows the recommended system-ground connections. Establish a single-point analog ground (star
ground point) at GND. Connect all other analog grounds
to this ground. No other digital system ground should be
connected to this single-point analog ground. The
ground return to the power supply should be low impedance and as short as possible for noise-free operation.
FAST POWER-DOWN
100
0.0001
18k
CONVERSIONS PER CHANNEL PER SECOND
High-frequency noise in the VDD power supply may affect
the high-speed comparator in the ADC. Bypass these
supplies to the single-point analog ground with 0.1µF and
4.7µF bypass capacitors close to the MAX1204. Minimize
capacitor lead lengths for best supply-noise rejection. If
the +5V power supply is very noisy, a 10Ω resistor can
be connected as a lowpass filter, as shown in Figure 18.
Figure 14b. MAX1204 Supply Current vs. Sample Rate/Second,
FASTPD, 2MHz Clock
Figure 17, the Reference-Adjust Circuit, shows how to
adjust ADC gain in applications that use the internal
reference. The circuit provides ±1.5% (±16LSBs) of
gain-adjustment range.
Layout, Grounding, Bypassing
For best performance, use printed circuit boards.
Wire-wrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digital
______________________________________________________________________________________
19
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
OUTPUT CODE
+5V
MAX1204
FULL-SCALE
TRANSITION
11 . . . 111
510k
100k
11 . . . 110
12
REFADJ
11 . . . 101
0.01µF
24k
FS = +4.096V
1LSB = FS
1024
Figure 17. Reference-Adjust Circuit
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
0
1
2
3
SUPPLIES
FS
INPUT VOLTAGE (LSBs)
FS - 3/2LSB
+5V
-5V
+3V
GND
+3V
DGND
Figure 15. Unipolar Transfer Function, 4.096V = Full Scale
R* = 10Ω
VDD
OUTPUT CODE
000 . . . 010
VSS
VL
MAX1204
011 . . . 111
011 . . . 110
GND
FS = +4.096V
2
1LSB = +4.096V
1024
*OPTIONAL
Figure 18. Power-Supply Grounding Connection
000 . . . 001
000 . . . 000
111 . . . 111
111 . . . 110
111 . . . 101
100 . . . 001
100 . . . 000
-FS
0V
+FS - 1LSB
INPUT VOLTAGE (LSBs)
Figure 16. Bipolar Transfer Function, ±4.096V/2 = Full Scale
20
DIGITAL
CIRCUITRY
______________________________________________________________________________________
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
XF
CLKX
1) The TMS320 should be configured with CLKX (transmit clock) as an active-high output clock and CLKR
(TMS320 receive clock) as an active-high input clock.
The TMS320’s CLKX and CLKR are tied together with
the MAX1204’s SCLK input.
2) The MAX1204’s CS is driven low by the TMS320’s
XF_ I/O port to enable data to be clocked into the
MAX1204’s DIN.
3) Write an 8-bit word (1XXXXX11) to the MAX1204 to
initiate a conversion and place the device into external clock mode. Refer to Table 2 to select the proper
XXXXX bit values for your specific application.
MAX1204
TMS320CL3x to MAX1204 Interface
Figure 19 shows an application circuit to interface the
MAX1204 to the TMS320 in external clock mode. Figure
20 is the timing diagram for this interface circuit.
Use the following steps to initiate a conversion in the
MAX1204 and to read the results.
CS
SCLK
TMS320LC3x
CLKR
4) The MAX1204’s SSTRB output is monitored via the
TMS320’s FSR input. A falling edge on the SSTRB
output indicates that the conversion is in progress
and data is ready to be received from the MAX1204.
5) The TMS320 reads in one data bit on each of the
next 16 rising edges of SCLK. These data bits represent the 10-bit conversion result followed by two
sub-bits and four trailing bits, which should be
ignored.
MAX1204
DX
DIN
DR
DOUT
FSR
SSTRB
Figure 19. MAX1204 to TMS320 Serial Interface
6) Pull CS high to disable the MAX1204 until the next
conversion is initiated.
CS
SCLK
DIN
START
SEL2
SEL1
SEL0
UNI/BIP SGL/DIF
PD1
PD0
HIGH
IMPEDANCE
SSTRB
DOUT
MSB
LSB
HIGH
IMPEDANCE
Figure 20. TMS320 Serial-Interface Timing Diagram
______________________________________________________________________________________
21
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
_Ordering Information (continued)
PART
TEMP. RANGE PIN-PACKAGE
__________Typical Operating Circuit
+5V
INL
(LSB)
MAX1204AEPP
-40°C to +85°C
20 Plastic DIP
±1/2
MAX1204BEPP
MAX1204AEAP
MAX1204BEAP
MAX1204BMJP
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
20 Plastic DIP
20 SSOP
20 SSOP
20 CERDIP*
±1
±1/2
±1
±1
VDD
CH0
0V to
4.096V
ANALOG
INPUTS
+3V
MAX1204 VL
GND
CH7
SCLK
REF
C1
4.7µF
___________________Chip Information
C2
0.01µF
DIN
DOUT
REFADJ
CPU
I/O
SCK (SK)
MOSI (SO)
MISO (SI)
SSTRB
SHDN
TRANSISTOR COUNT: 2503
SUBSTRATE CONNECTED TO VSS
22
C4
0.1µF
VSS
CS
*Contact factory for availability.
VDD
C3
0.1µF
______________________________________________________________________________________
VSS
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
DIM
A
A1
B
C
D
E
e
H
L
α
α
E
H
C
L
INCHES
MILLIMETERS
MIN
MAX
MIN
MAX
0.068
0.078
1.73
1.99
0.002
0.008
0.05
0.21
0.010
0.015
0.25
0.38
0.004
0.008
0.09
0.20
SEE VARIATIONS
0.205
0.209
5.20
5.38
0.0256 BSC
0.65 BSC
0.301
0.311
7.65
7.90
0.025
0.037
0.63
0.95
0˚
8˚
0˚
8˚
DIM PINS
e
A
B
D
D
D
D
D
SSOP
SHRINK
SMALL-OUTLINE
PACKAGE
A1
14
16
20
24
28
INCHES
MILLIMETERS
MAX
MIN MAX MIN
6.33
0.239 0.249 6.07
6.33
0.239 0.249 6.07
7.33
0.278 0.289 7.07
8.33
0.317 0.328 8.07
0.397 0.407 10.07 10.33
21-0056A
D
DIM
A
A1
A2
A3
B
B1
C
D
D1
E
E1
e
eA
eB
L
α
D1
E
E1
D
A2
A
A3
α
A1
C
B1
B
MILLIMETERS
MIN
MAX
–
5.08
0.38
–
3.18
3.81
1.40
2.03
0.41
0.56
1.27
1.65
0.20
0.30
25.78
26.54
1.02
1.78
7.62
8.26
6.10
7.11
2.54 BSC
7.62 BSC
–
10.16
2.92
3.81
0˚
15˚
21-333A
L
e
INCHES
MAX
MIN
0.200
–
–
0.015
0.150
0.125
0.080
0.055
0.022
0.016
0.065
0.050
0.012
0.008
1.045
1.015
0.070
0.040
0.325
0.300
0.280
0.240
0.100 BSC
0.300 BSC
0.400
–
0.150
0.115
15˚
0˚
eA
eB
20-PIN PLASTIC
DUAL-IN-LINE
PACKAGE
______________________________________________________________________________________
23
MAX1204
________________________________________________________Package Information
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
___________________________________________Package Information (continued)
DIM
S1
S
E1
D
A
E
A
B
B1
C
D
E
E1
e
L
L1
Q
S
S1
α
INCHES
MAX
MIN
0.200
–
0.023
0.014
0.065
0.038
0.015
0.008
1.060
–
0.310
0.220
0.320
0.290
0.100 BSC
0.200
0.125
–
0.150
0.070
0.015
0.080
–
–
0.005
15˚
0˚
MILLIMETERS
MIN
MAX
–
5.08
0.36
0.58
0.97
1.65
0.20
0.38
–
26.92
5.59
7.87
7.37
8.13
2.54 BSC
3.18
5.08
3.81
–
0.38
1.78
–
2.03
0.13
–
0˚
15˚
21-335C
α
Q
L
L1
e
B1
B
C
20-PIN CERAMIC
DUAL-IN-LINE
PACKAGE
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1997 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.