19-0464; Rev 3; 5/09 +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs Features The MAX148/MAX149 10-bit data-acquisition systems combine an 8-channel multiplexer, high-bandwidth track/hold, and serial interface with high conversion speed and low power consumption. They operate from a single +2.7V to +5.25V supply, and sample to 133ksps. Both devices’ analog inputs are software configurable for unipolar/bipolar and single-ended/differential operation. S 8-Channel Single-Ended or 4-Channel Differential The 4-wire serial interface connects directly to SPIK/ QSPIK and MICROWIREK devices without external logic. A serial-strobe output allows direct connection to TMS320-family digital signal processors. The MAX148/ MAX149 use either the internal clock or an external serial-interface clock to perform successive-approximation analog-to-digital conversions. The MAX149 has an internal 2.5V reference, while the MAX148 requires an external reference. Both parts have a reference-buffer amplifier with a Q1.5% voltageadjustment range. These devices provide a hard-wired SHDN pin and a software-selectable power-down, and can be programmed to automatically shut down at the end of a conversion. Accessing the serial interface automatically powers up the MAX148/MAX149, and the quick turn-on time allows them to be shut down between all conversions. This technique can cut supply current to under 60FA at reduced sampling rates. The MAX148/MAX149 are available in a 20-pin DIP and a 20-pin SSOP. Inputs S Single-Supply Operation: +2.7V to +5.25V S Internal 2.5V Reference (MAX149) S Low Power: 1.2mA (133ksps, 3V Supply) 54µA (1ksps, 3V Supply) 1µA (Power-Down Mode) S SPI/QSPI/MICROWIRE/TMS320-Compatible 4-Wire Serial Interface S Software-Configurable Unipolar or Bipolar Inputs S 20-Pin DIP/SSOP Packages Ordering Information TEMP RANGE PINPACKAGE INL (LSB) MAX148ACPP 0°C to +70°C 20 Plastic DIP ±1/2 MAX148BCPP 0°C to +70°C 20 Plastic DIP ±1 MAX148ACAP 0°C to +70°C 20 SSOP ±1/2 MAX148BCAP 0°C to +70°C 20 SSOP ±1 PART† Ordering Information continued at end of data sheet. †Contact factory for availability of alternate surface-mount package. Specify lead-free by placing + by the part number when ordering. *Contact factory for availability of CERDIP package, and for processing to MIL-STD-883B. Not available in lead-free. For 4-channel versions of these devices, see the MAX1248/MAX1249 data sheet. Typical Operating Circuit +3V Applications Portable Data Logging Data Acquisition Medical Instruments Process Control DGND MAX149 CH7 AGND VREF COM CPU CS SCLK DIN DOUT SSTRB SHDN I/O SCK (SK) MOSI (SO) MISO (SI) 4.7FF READJ Pin Configuration appears at end of data sheet. 0.01FF VDD 0.1FF O TO +2.5V ANALOG INPUTS Battery-Powered Instruments Pen Digitizers VDD CH0 VSS SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX148/MAX149 General Description MAX148/MAX149 +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs ABSOLUTE MAXIMUM RATINGS VDD to AGND, DGND...............................................-0.3V to +6V AGND to DGND....................................................-0.3V to +0.3V CH0–CH7, COM to AGND, DGND............ -0.3V to (VDD + 0.3V) VREF, REFADJ to AGND............................-0.3V to (VDD + 0.3V) Digital Inputs to DGND............................................-0.3V to +6V Digital Outputs to DGND........................... -0.3V to (VDD + 0.3V) Digital Output Sink Current.................................................25mA Continuous Power Dissipation (TA = +70NC) Plastic DIP (derate 11.11mW/NC above +70NC)...........889mW SSOP (derate 8.00mW/NC above +70NC).....................640mW CERDIP (derate 11.11mW/NC above +70NC)...............889mW Operating Temperature Ranges MAX148_C_P/MAX149_C_P............................... 0NC to +70NC MAX148_E_P/MAX149_E_P............................. -40NC to +85NC MAX148_MJP/MAX149_MJP......................... -55NC to +125NC MAX149BMAP................................................ -55NC to +125NC Storage Temperature Range............................. -60NC to +150NC Lead Temperature (soldering, 10s).................................+300NC Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +2.7V to +5.25V; COM = 0; fSCLK = 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX149—4.7FF capacitor at VREF pin; MAX148—external reference, VREF = 2.500V applied to VREF pin; TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY (Note 1) Resolution 10 Relative Accuracy (Note 2) INL Differential Nonlinearity DNL Offset Error Gain Error (Note 3) Bits MAX14_A ±0.5 MAX14_B ±1.0 No missing codes over temperature ±1 MAX14_A ±0.15 ±1 MAX14_B ±0.15 ±2 MAX14_A ±1 MAX14_B ±2 LSB LSB LSB LSB Gain Temperature Coefficient ±0.25 ppm/°C Channel-to-Channel Offset Matching ±0.05 LSB DYNAMIC SPECIFICATIONS (10kHz Sine-Wave Input, 0 to 2.500VP-P, 133ksps, 2.0MHz External Clock, Bipolar Input Mode) Signal-to-Noise + Distortion Noise SINAD 66 dB Up to the 5th harmonic -70 dB 70 dB Channel-to-Channel Crosstalk 65kHz, 2.500VP-P (Note 4) -75 dB Small-Signal Bandwidth -3dB rolloff 2.25 MHz 1.0 MHz Total Harmonic Distortion THD Spurious-Free Dynamic Range SFDR Full-Power Bandwidth CONVERSION RATE Conversion Time (Note 5) Track/Hold Acquisition Time tCONV Internal clock, SHDN = unconnected 5.5 7.5 Internal clock, SHDN = VDD 35 65 External clock = 2MHz, 12 clocks/ conversion 6 tACQ 1.5 μs μs Aperture Delay 30 ns Aperture Jitter < 50 ps 2 _______________________________________________________________________________________ +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs (VDD = +2.7V to +5.25V; COM = 0; fSCLK = 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX149—4.7FF capacitor at VREF pin; MAX148—external reference, VREF = 2.500V applied to VREF pin; TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CONVERSION RATE (continued) Internal Clock Frequency External Clock Frequency SHDN = unconnected 1.8 SHDN = VDD Data transfer only MHz 0.225 0.1 2.0 1 2.0 MHz ANALOG/COM INPUTS Input Voltage Range, SingleEnded and Differential (Note 6) Unipolar, COM = 0 Multiplexer Leakage Current On/off leakage current, VCH_ = 0 or VDD 0 to VREF Bipolar, COM = VREF/2 ±VREF/2 ±0.01 Input Capacitance ±1 16 V μA pF INTERNAL REFERENCE (MAX149 Only, Reference Buffer Enabled) VREF Output Voltage TA = +25°C (Note 7) 2.470 2.500 VREF Short-Circuit Current 30 VREF Temperature Coefficient MAX149 Load Regulation (Note 8) 0 to 0.2mA output load Capacitive Bypass at VREF 2.530 Internal compensation mode 0 External compensation mode 4.7 Capacitive Bypass at REFADJ mA ±30 ppm/°C 0.35 mV μF 0.01 REFADJ Adjustment Range V μF ±1.5 % EXTERNAL REFERENCE AT VREF (Buffer Disabled) VREF Input Voltage Range (Note 9) VREF Input Current VDD + 50mV 1.0 VREF = 2.500V VREF Input Resistance 100 18 Shutdown VREF Input Current 150 25 0.01 μA kΩ 10 VDD 0.5 REFADJ Buffer-Disable Threshold V µA V EXTERNAL REFERENCE AT REFADJ Capacitive Bypass at VREF Reference Buffer Gain REFADJ Input Current Internal compensation mode 0 External compensation mode 4.7 µF MAX149 2.06 MAX148 2.00 V/V MAX149 ±50 MAX148 ±10 µA _______________________________________________________________________________________ 3 MAX148/MAX149 ELECTRICAL CHARACTERISTICS (continued) MAX148/MAX149 +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs ELECTRICAL CHARACTERISTICS (continued) (VDD = +2.7V to +5.25V; COM = 0; fSCLK = 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX149—4.7FF capacitor at VREF pin; MAX148—external reference, VREF = 2.500V applied to VREF pin; TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (DIN, SCLK, CS, SHDN) DIN, SCLK, CS Input High Voltage VIH DIN, SCLK, CS Input Low Voltage VIL DIN, SCLK, CS Input Hysteresis VHYST VDD ≤ 3.6V 2.0 VDD > 3.6V 3.0 0.8 0.2 DIN, SCLK, CS Input Leakage IIN VIN = 0 or VDD DIN, SCLK, CS Input Capacitance CIN (Note 10) ±0.01 SHDN Input High Voltage VSH VDD 0.4 SHDN Input Mid Voltage VSM 1.1 SHDN Input Low Voltage VSL SHDN Input Current SHDN Voltage, Unconnected IS VFLT SHDN Maximum Allowed Leakage, Mid Input V V ±1 µA 15 pF V VDD 1.1 SHDN = 0 or VDD SHDN = unconnected V 0.4 V ±4.0 µA VDD/2 SHDN = unconnected V V ±100 nA DIGITAL OUTPUTS (DOUT, SSTRB) Output-Voltage Low VOL Output-Voltage High VOH Three-State Leakage Current Three-State Output Capacitance IL COUT ISINK = 5mA 0.4 ISINK = 16mA 0.8 VDD 0.5 ISOURCE = 0.5mA CS = VDD V V ±0.01 CS = VDD (Note 10) ±10 µA 15 pF 5.25 V POWER REQUIREMENTS Positive Supply Voltage Positive Supply Current VDD IDD 2.70 Operating mode, full-scale VDD = 5.25V input (Note 11) VDD = 3.6V 1.6 3.0 1.2 2.0 VDD = 5.25V 3.5 15 VDD = 3.6V 1.2 10 30 70 Full power-down Fast power-down (MAX149) Supply Rejection (Note 12) PSR Full-scale input, external reference = 2.500V, VDD = 2.7V to 5.25V ±0.3 4 _______________________________________________________________________________________ mA µA mV +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs (VDD = +2.7V to +5.25V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Acquisition Time SYMBOL CONDITIONS MIN TYP MAX UNITS tACQ 1.5 μs DIN to SCLK Setup tDS 100 ns DIN to SCLK Hold tDH 0 SCLK Fall to Output Data Valid tDO Figure 1 CS Fall to Output Enable tDV Figure 1 tTR Figure 2 CS Rise to Output Disable ns MAX14_ _C/E 20 200 MAX14_ _M 20 240 ns 240 ns 240 ns CS to SCLK Rise Setup tCSS 100 ns CS to SCLK Rise Hold tCSH 0 ns SCLK Pulse Width High tCH 200 ns SCLK Pulse Width Low SCLK Fall to SSTRB tCL tSSTRB 200 ns Figure 1 240 ns CS Fall to SSTRB Output Enable tSDV External clock mode only, Figure 1 240 ns CS Rise to SSTRB Output Disable tSTR External clock mode only, Figure 2 240 ns SSTRB Rise to SCLK Rise tSCK Internal clock mode only (Note 7) 0 ns Note 1: Tested at VDD = 2.7V; COM = 0; unipolar single-ended input mode. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. Note 3: MAX149—internal reference, offset nulled; MAX148—external reference (VREF = +2.500V), offset nulled. Note 4: Ground “on” channel; sine wave applied to all “off” channels. Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. Note 6: The common-mode range for the analog inputs is from AGND to VDD. Note 7: Sample tested to 0.1% AQL. Note 8: External load should not change during conversion for specified accuracy. Note 9: ADC performance is limited by the converter’s noise floor, typically 300FVP-P. Note 10:Guaranteed by design. Not subject to production testing. Note 11:The MAX148 typically draws 400FA less than the values shown. Note 12:Measured as |VFS(2.7V) - VFS(5.25V)|. _______________________________________________________________________________________ 5 MAX148/MAX149 TIMING CHARACTERISTICS Typical Operating Characteristics (VDD = 3.0V, VREF = 2.500V, fSCLK = 2.0MHz, CLOAD = 20pF, TA = +25NC, unless otherwise noted.) MAX149 0.075 0.050 MAX148 -0.05 VDD = 2.7V 0.100 INL (LSB) 0 0.125 MAX148-MAX149 toc02 0.100 INL (LSB) 0.05 INL (LSB) 0.125 MAX148-MAX149 toc01 0.10 INTEGRAL NONLINEARITY vs. TEMPERATURE MAX148-MAX149 toc03 INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE INTEGRAL NONLINEARITY vs. CODE MAX149 0.075 0.050 MAX148 0.025 0.025 -0.10 0 1024 0 2.25 CLOAD = 50pF MAX149 1.50 1.25 CLOAD = 20pF 1.00 0.75 4.75 5.25 MAX148 3.0 0.50 2.75 3.25 3.75 4.25 SUPPLY VOLTAGE (V) FULL POWER-DOWN 2.5 2.0 1.5 1.0 0.5 4.75 5.25 1.1 1.0 MAX148 0.9 RL0AD = J CODE = 1010101000 0.8 -60 -20 20 60 TEMPERATURE (NC) 100 2.75 3.25 3.75 4.25 SUPPLY VOLTAGE (V) 4.75 140 2.5015 2.5010 2.5005 2.5000 2.4995 2.25 5.25 1.6 2.75 3.25 3.75 4.25 SUPPLY VOLTAGE (V) 4.75 5.25 MAX149 INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE MAX148-MAX149 toc08 2.0 SHUTDOWN CURRENT (mA) MAX149 140 100 2.5020 SHUTDOWN CURRENT vs. TEMPERATURE MAX148-MAX149 toc07 1.3 20 60 TEMPERATURE (NC) 2.4990 2.25 SUPPLY CURRENT vs. TEMPERATURE 1.2 -20 MAX149 INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE 0 2.25 -60 MAX148-MAX149 toc06 SUPPLY CURRENT (mA) 1.75 RL = J CODE = 1010101000 SHUTDOWN SUPPLY CURRENT (FA) 2.00 3.25 3.75 4.25 SUPPLY VOLTAGE (V) SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX148-MAX149 toc04 SUPPLY CURRENT vs. SUPPLY VOLTAGE 2.75 1.2 0.8 0.4 0 2.501 VDD = 5.25V 2.500 VDD = 3.6V 2.499 MAX148-MAX149 toc09 768 INTERNAL REFERENCE VOLTAGE (V) 512 CODE INTERNAL REFERENCE VOLTAGE (V) 256 MAX148-MAX149 toc05 0 SUPPLY CURRENT (mA) MAX148/MAX149 +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs VDD = 2.7V 2.498 2.497 2.496 2.495 2.494 -60 -20 20 60 TEMPERATURE (NC) 100 140 -60 -20 20 60 TEMPERATURE (NC) 6 _______________________________________________________________________________________ 100 140 +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs PIN NAME 1–8 CH0–CH7 9 COM Ground Reference for Analog Inputs. COM sets zero-code voltage in single-ended mode. Must be stable to ±0.5 LSB. SHDN Three-Level Shutdown Input. Pulling SHDN low shuts the MAX148/MAX149 down; otherwise, they are fully operational. Pulling SHDN high puts the reference-buffer amplifier in internal compensation mode. Leaving SHDN unconnected puts the reference-buffer amplifier in external compensation mode. 11 VREF Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In internal reference mode (MAX149 only), the reference buffer provides a 2.500V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to VDD. 12 REFADJ 13 AGND Analog Ground 14 DGND Digital Ground 15 DOUT Serial-Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high. 16 SSTRB Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX148/MAX149 begin the A/D conversion, and goes high when the conversion is finished. In external clock mode, SSTRB pulses high for one clock period before the MSB decision. High impedance when CS is high (external clock mode). 17 DIN Serial-Data Input. Data is clocked in at SCLK’s rising edge. 18 CS Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is high impedance. 19 SCLK Serial-Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets the conversion speed (duty cycle must be 40% to 60%). 20 VDD 10 FUNCTION Sampling Analog Inputs Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to VDD. Positive Supply Voltage VDD VDD 6kI 6kI DOUT DOUT 6kI DOUT CLOAD 50pF CLOAD 50pF DOUT CLOAD 50pF 6kI DGND DGND DGND a) HIGH-Z TO VOH AND VOL TO VOH b) HIGH-Z TO VOL AND VOH TO VOL Figure 1. Load Circuits for Enable Time a) VOH TO HIGH-Z CLOAD 50pF DGND b) VOL TO HIGH-Z Figure 2. Load Circuits for Disable Time _______________________________________________________________________________________ 7 MAX148/MAX149 Pin Description MAX148/MAX149 +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs Detailed Description The MAX148/MAX149 analog-to-digital converters (ADCs) use a successive-approximation conversion technique and input track/hold (T/H) circuitry to convert an analog signal to a 10-bit digital output. A flexible serial interface provides easy interface to microprocessors (FPs). Figure 3 is a block diagram of the MAX148/ MAX149. Pseudo-Differential Input The sampling architecture of the ADC’s analog comparator is illustrated in the equivalent input circuit (Figure 4). In single-ended mode, IN+ is internally switched to CH0–CH7, and IN- is switched to COM. In differential mode, IN+ and IN- are selected from the following pairs: CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7. Configure the channels with Tables 2 and 3. In differential mode, IN- and IN+ are internally switched to either of the analog inputs. This configuration is pseudo-differential to the effect that only the signal at IN+ is sampled. The return side (IN-) must remain stable within Q0.5 LSB (Q0.1 LSB for best results) with respect to AGND during a conversion. To accomplish this, connect a 0.1FF capacitor from IN- (the selected analog input) to AGND. During the acquisition interval, the channel selected as the positive input (IN+) charges capacitor CHOLD. The acquisition interval spans three SCLK cycles and ends on the falling SCLK edge after the last bit of the input CS SCLK DIN SHDN VREF The conversion interval begins with the input multiplexer switching CHOLD from the positive input (IN+) to the negative input (IN-). In single-ended mode, IN- is simply COM. This unbalances node ZERO at the comparator’s input. The capacitive DAC adjusts during the remainder of the conversion cycle to restore node ZERO to 0 within the limits of 10-bit resolution. This action is equivalent to transferring a 16pF x [(VIN+) - (VIN-)] charge from CHOLD to the binary-weighted capacitive DAC, which in turn forms a digital representation of the analog input signal. Track/Hold The T/H enters its tracking mode on the falling clock edge after the fifth bit of the 8-bit control word has been shifted in. It enters its hold mode on the falling clock edge after the eighth bit of the control word has been shifted in. If the converter is set up for single-ended inputs, IN- is connected to COM, and the converter samples the “+” input. If the converter is set up for differential inputs, IN- connects to the “-” input, and the difference of |IN+ - IN-| is sampled. At the end of the conversion, the positive input connects back to IN+, and CHOLD charges to the input signal. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal’s source impedance is high, the acquisition time lengthens, and more time must be 18 19 17 10 1 2 3 4 5 6 7 8 9 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM REFADJ control word has been entered. At the end of the acquisition interval, the T/H switch opens, retaining charge on CHOLD as a sample of the signal at IN+. 12 11 INPUT SHIFT REGISTER CONTROL LOGIC CAPACITIVE DAC INT CLOCK VREF OUTPUT SHIFT REGISTER ANALOG INPUT MUX +1.21V REFERENCE (MAX149) T/H CLOCK IN 10+2-BIT SAR ADC OUT REF A ≈ 2.06* 20kΩ 15 16 20 14 13 +2.500V MAX148 MAX149 DOUT SSTRB VDD DGND AGND CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM INPUT MUX CHOLD + COMPARATOR ZERO 16pF CSWITCH TRACK RIN 9kΩ HOLD T/H SWITCH AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL. SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM. DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7. *A ≈ 2.00 (MAX148) Figure 3. Block Diagram Figure 4. Equivalent Input Circuit 8 _______________________________________________________________________________________ +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs +3V OSCILLOSCOPE 0.1µF DGND SCLK AGND MAX148 MAX149 0 TO +2.500V ANALOG INPUT 0.01µF +3V CH7 1000pF MAX872 SSTRB CS DOUT* SCLK +3V 2.5V VOUT COM REFADJ VREF C1 0.1µF +3V DIN 2MHz OSCILLATOR CH1 CH2 CH3 CH4 DOUT SSTRB COMP SHDN N.C. OPTIONAL FOR MAX149, REQUIRED FOR MAX148 *FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX) Figure 5. Quick-Look Circuit allowed between conversions. The acquisition time, tACQ, is the maximum time the device takes to acquire the signal, and is also the minimum time needed for the signal to be acquired. It is calculated by the following equation: tACQ = 7 x (RS + RIN) x 16pF where RIN = 9kI, RS = the source impedance of the input signal, and tACQ is never less than 1.5Fs. Note that source impedances below 4kI do not significantly affect the ADC’s AC performance. Higher source impedances can be used if a 0.01FF capacitor is connected to the individual analog inputs. Note that the input capacitor forms an RC filter with the input source impedance, limiting the ADC’s signal bandwidth. Input Bandwidth The ADC’s input tracking circuitry has a 2.25MHz small-signal bandwidth, so it is possible to digitize highspeed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. To avoid highfrequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. Analog Input Protection Internal protection diodes, which clamp the analog input to VDD and AGND, allow the channel input pins to swing from AGND - 0.3V to VDD + 0.3V without damage. However, for accurate conversions near full scale, the inputs must not exceed VDD by more than 50mV or be lower than AGND by 50mV. If the analog input exceeds 50mV beyond the supplies, do not forward bias the protection diodes of off channels over 2mA. Quick Look To quickly evaluate the MAX148/MAX149’s analog performance, use the circuit of Figure 5. The MAX148/ MAX149 require a control byte to be written to DIN before each conversion. Tying DIN to +3V feeds in control bytes of $FF (HEX), which trigger single-ended unipolar conversions on CH7 in external clock mode without powering down between conversions. In external clock mode, the SSTRB output pulses high for one clock period before the most significant bit of the conversion result is shifted out of DOUT. Varying the analog input to CH7 will alter the sequence of bits from DOUT. A total of 15 clock cycles is required per conversion. All transitions of the SSTRB and DOUT outputs occur on the falling edge of SCLK. _______________________________________________________________________________________ 9 MAX148/MAX149 VDD MAX148/MAX149 +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs Table 1. Control-Byte Format BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) START SEL2 SEL1 SEL0 UNI/BIP SGL//DIF PD1 PD0 BIT NAME 7(MSB) START 6 5 4 SEL2 SEL1 SEL0 These three bits select which of the eight channels are used for the conversion (Tables 2 and 3) 3 UNI/BIP 1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an analog input signal from 0 to VREF can be converted; in bipolar mode, the signal can range from -VREF/2 to +VREF/2. 2 SGL/DIF 1 = single ended, 0 = differential. Selects single-ended or differential conversions. In singleended mode, input signal voltages are referred to COM. In differential mode, the voltage difference between two channels is measured (Tables 2 and 3). 1 PD1 0(LSB) DESCRIPTION The first logic “1” bit after CS goes low defines the beginning of the control byte. Selects clock and power-down modes. PD1 PD0 0 0 Full power-down 0 1 Fast power-down (MAX149 only) 1 0 Internal clock mode 1 1 External clock mode PD0 Mode Table 2. Channel Selection in Single-Ended Mode (SGL/DIF = 1) SEL2 SEL1 SEL0 CH0 0 0 0 + 1 0 0 0 0 1 1 0 1 0 1 0 1 1 0 0 1 1 1 1 1 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM - + + How to Start a Conversion Start a conversion by clocking a control byte into DIN. With CS low, each rising edge on SCLK clocks a bit from DIN into the MAX148/MAX149’s internal shift register. After CS falls, the first arriving logic “1” bit defines the control byte’s MSB. Until this first “start” bit arrives, any number of logic “0” bits can be clocked into DIN with no effect. Table 1 shows the control-byte format. The MAX148/MAX149 are compatible with SPI/QSPI and MICROWIRE devices. For SPI, select the correct clock + + + + + - polarity and sampling edge in the SPI control registers: set CPOL = 0 and CPHA = 0. MICROWIRE, SPI, and QSPI all transmit a byte and receive a byte at the same time. Using the Typical Operating Circuit, the simplest software interface requires only three 8-bit transfers to perform a conversion (one 8-bit transfer to configure the ADC, and two more 8-bit transfers to clock out the conversion result). See Figure 20 for MAX148/ MAX149 QSPI connections. 10 ������������������������������������������������������������������������������������� +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs SEL2 SEL1 SEL0 CH0 CH1 0 0 0 + - 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 - CH2 CH3 + - CH4 CH5 + - CH6 CH7 + - - + + - + - + CS tACQ SCLK 1 DIN SSTRB 4 SEL2 SEL1 SEL0 8 UNI/ SGL/ BIP DIF PD1 12 16 20 24 PD0 START RB2 RB1 B9 MSB DOUT B8 B7 B6 RB3 B5 B4 B3 B2 B1 B0 LSB S1 S0 FILLED WITH ZEROS ACQUISITION A/D STATE IDLE 1.5Fs CONVERSION IDLE (fSCLK = 2MHz) Figure 6. 24-Clock External Clock Mode Conversion Timing (MICROWIRE and SPI-Compatible, QSPI-Compatible with fSCLK P 2MHz) Simple Software Interface Make sure the CPU’s serial interface runs in master mode so the CPU generates the serial clock. Choose a clock frequency from 100kHz to 2MHz. 1) Set up the control byte for external clock mode and call it TB1. TB1 should be of the format: 1XXXXX11 binary, where the Xs denote the particular channel and conversion mode selected. 2) Use a general-purpose I/O line on the CPU to pull CS low. 3) Transmit TB1 and, simultaneously, receive a byte and call it RB1. Ignore RB1. 4) Transmit a byte of all zeros ($00 hex) and, simultaneously, receive byte RB2. 5) Transmit a byte of all zeros ($00 hex) and, simultaneously, receive byte RB3. 6) Pull CS high. Figure 6 shows the timing for this sequence. Bytes RB2 and RB3 contain the result of the conversion, padded with one leading zero, two sub-LSB bits, and three trailing zeros. The total conversion time is a function of the serial-clock frequency and the amount of idle time between 8-bit transfers. To avoid excessive T/H droop, make sure the total conversion time does not exceed 120Fs. Digital Output In unipolar input mode, the output is straight binary (Figure 17). For bipolar input mode, the output is twos complement (Figure 18). Data is clocked out at the falling edge of SCLK in MSB-first format. Clock Modes The MAX148/MAX149 may use either an external serial clock or the internal clock to perform the successiveapproximation conversion. In both clock modes, the external clock shifts data in and out of the MAX148/MAX149. ______________________________________________________________________________________ 11 MAX148/MAX149 Table 3. Channel Selection in Differential Mode (SGL/DIF = 0) MAX148/MAX149 +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs CS tCSH tCSS tCL tCSH tCH SCLK tDS tDH DIN tDV tDO tTR DOUT Figure 7. Detailed Serial-Interface Timing CS tSDV tSTR SSRTB tSSTRB tSSTRB SCLK PD0 CLOCKED IN Figure 8. External Clock Mode SSTRB Detailed Timing The T/H acquires the input signal as the last three bits of the control byte are clocked into DIN. Bits PD1 and PD0 of the control byte program the clock mode. Figures 7–10 show the timing characteristics common to both modes. and DOUT go into a high-impedance state when CS goes high; after the next CS falling edge, SSTRB outputs a logic-low. Figure 8 shows the SSTRB timing in external clock mode. External Clock In external clock mode, the external clock not only shifts data in and out, but it also drives the analog-to-digital conversion steps. SSTRB pulses high for one clock period after the last bit of the control byte. Successive- approximation bit decisions are made and appear at DOUT on each of the next 12 SCLK falling edges (Figure 6). SSTRB The conversion must complete in some minimum time, or droop on the sample-and-hold capacitors may degrade conversion results. Use internal clock mode if the serialclock frequency is less than 100kHz, or if serial-clock interruptions could cause the conversion interval to exceed 120Fs. 12 ������������������������������������������������������������������������������������� +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs MAX148/MAX149 CS SCLK 1 3 4 5 6 7 8 9 10 11 12 18 19 20 21 22 23 24 SGL/ SEL2 SEL1 SEL0 UNI/ BIP DIF PD1 PD0 DIN SSTRB 2 START tCONV B9 MSB B8 DOUT AD STATE IDLE ACQUISITION 1.5Fs CONVERSION 7.5Fs MAX B0 LSB S1 B7 FILLED WITH S0 ZEROS IDLE (fSCLK = 2MHz)(SHDN = UNCONNECTED) Figure 9. Internal Clock Mode Timing CS tCONV tSCK tCSH tCSS SSTRB tSSTRB SCLK tD0 PD0 CLOCK IN DOUT NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION. Figure 10. Internal Clock Mode SSTRB Detailed Timing Internal Clock In internal clock mode, the MAX148/MAX149 generate their own conversion clocks internally. This frees the FP from the burden of running the SAR conversion clock and allows the conversion results to be read back at the processor’s convenience, at any clock rate from 0 to 2MHz. SSTRB goes low at the start of the conversion and then goes high when the conversion is complete. SSTRB is low for a maximum of 7.5Fs (SHDN = unconnected), during which time SCLK should remain low for best noise performance. An internal register stores data when the conversion is in progress. SCLK clocks the data out of this register at any time after the conversion is complete. After SSTRB goes high, the next falling clock edge produces the MSB of the conversion at DOUT, followed by the remaining bits in MSB-first format (Figure 9). CS does not need to be held low once a conversion is started. Pulling CS high prevents data from being clocked into the MAX148/MAX149 and three-states DOUT, but it does not adversely affect an internal clock mode conversion already in progress. When internal clock mode is selected, SSTRB does not go into a high-impedance state when CS goes high. Figure 10 shows the SSTRB timing in internal clock mode. In this mode, data can be shifted in and out of the MAX148/MAX149 at clock rates exceeding 2.0MHz if the minimum acquisition time (tACQ) is kept above 1.5Fs. Data Framing The falling edge of CS does not start a conversion. The first logic high clocked into DIN is interpreted as a start bit and defines the first bit of the control byte. A conversion starts on SCLK’s falling edge, after the eighth bit of ______________________________________________________________________________________ 13 MAX148/MAX149 +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs Table 4. Typical Power-Up Delay Times REFERENCE BUFFER REFERENCEBUFFER COMPENSATION MODE VREF CAPACITOR (µF) POWER-DOWN MODE Enabled Internal — Enabled Internal — Enabled External Enabled POWER-UP DELAY (µs) MAXIMUM SAMPLING RATE (ksps) Fast 5 26 Full 300 26 4.7 Fast See Figure 14c 133 External 4.7 Full See Figure 14c 133 Disabled — — Fast 2 133 Disabled — — Full 2 133 the control byte (the PD0 bit) is clocked into DIN. The start bit is defined as follows: The first high bit clocked into DIN with CS low any time the converter is idle; e.g., after VDD is applied. OR The first high bit clocked into DIN after bit 3 of a conversion in progress is clocked onto the DOUT pin. If CS is toggled before the current conversion is complete, the next high bit clocked into DIN is recognized as a start bit; the current conversion is terminated, and a new one is started. The fastest the MAX148/MAX149 can run with CS held low between conversions is 15 clocks per conversion. Figure 11a shows the serial-interface timing necessary to perform a conversion every 15 SCLK cycles in external clock mode. If CS is tied low and SCLK is continuous, guarantee a start bit by first clocking in 16 zeros. Most microcontrollers (FCs) require that conversions occur in multiples of 8 SCLK clocks; 16 clocks per conversion is typically the fastest that a FC can drive the MAX148/MAX149. Figure 11b shows the serialinterface timing necessary to perform a conversion every 16 SCLK cycles in external clock mode. Applications Information Power-On Reset When power is first applied, and if SHDN is not pulled low, internal power-on reset circuitry activates the MAX148/MAX149 in internal clock mode, ready to convert with SSTRB = high. After the power supplies stabilize, the internal reset time is 10Fs, and no conversions should be performed during this phase. SSTRB is high on power-up and, if CS is low, the first logical 1 on DIN is interpreted as a start bit. Until a conversion takes place, DOUT shifts out zeros. Also see Table 4. Reference-Buffer Compensation In addition to its shutdown function, SHDN selects internal or external compensation. The compensation affects both power-up time and maximum conversion speed. The 100kHz minimum clock rate is limited by droop on the sample-and-hold and is independent of the compensation used. Unconnect SHDN to select external compensation. The Typical Operating Circuit uses a 4.7FF capacitor at VREF. A 4.7FF value ensures reference-buffer stability and allows converter operation at the 2MHz full clock speed. External compensation increases power-up time (see the Choosing Power-Down Mode section and Table 4). Pull SHDN high to select internal compensation. Internal compensation requires no external capacitor at VREF and allows for the shortest power-up times. The maximum clock rate is 2MHz in internal clock mode and 400kHz in external clock mode. Choosing Power-Down Mode You can save power by placing the converter in a lowcurrent shutdown state between conversions. Select full power-down mode or fast power-down mode via bits 1 and 0 of the DIN control byte with SHDN high or unconnected (Tables 1 and 5). In both software power-down modes, the serial interface remains operational, but the ADC does not convert. Pull SHDN low at any time to shut down the converter completely. SHDN overrides bits 1 and 0 of the control byte. Full power-down mode turns off all chip functions that draw quiescent current, reducing supply current to 2FA (typ). Fast power-down mode turns off all circuitry except the bandgap reference. With fast power-down mode, the supply current is 30FA. Power-up time can be shortened to 5Fs in internal compensation mode. Table 4 shows how the choice of reference-buffer compensation and power-down mode affects both power-up 14 ������������������������������������������������������������������������������������� +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs 1 8 15 1 8 15 1 SCLK DIN S CONTROL BYTE 0 DOUT S CONTROL BYTE 1 S CONTROL BYTE 2 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0 CONVERSION RESULT 0 CONVERSION RESULT 1 SSTRB Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing CS 1 8 16 1 8 16 SCLK DIN S CONTROL BYTE 0 S B9 DOUT B8 B7 B6 B5 B4 B3 B2 CONTROL BYTE 1 B1 B0 S1 S0 B9 B8 B7 B6 CONVERSION RESULT 1 CONVERSION RESULT 0 Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing EXTERNAL CLOCK MODE EXTERNAL SHDN SETS SOFTWARE POWER-DOWN SETS EXTERNAL CLOCK MODE DIN DOUT MODE S X X X X X 1 1 SX X XX X 0 0 10 + 2 DATA BITS SETS EXTERNAL CLOCK MODE S XX XXX 1 1 10 + 2 DATA BITS VALID DATA POWERED UP POWERED UP INVALID DATA HARDWARE POWER-DOWN POWERED UP SOFTWARE POWER-DOWN Figure 12a. Timing Diagram Power-Down Modes, External Clock delay and maximum sample rate. In external compensation mode, power-up time is 20ms with a 4.7FF compensation capacitor when the capacitor is initially fully discharged. From fast power-down, startup time can be eliminated by using low-leakage capacitors that do not discharge more than ½ LSB while shut down. In powerdown, leakage currents at VREF cause droop on the reference bypass capacitor. Figures 12a and 12b show the various power-down sequences in both external and internal clock modes. ______________________________________________________________________________________ 15 MAX148/MAX149 CS INTERNAL CLOCK MODE SETS INTERNAL CLOCK MODE SETS POWER-DOWN 5XXXXX00 SXXXXX10 DIN S DATA VALID DOUT DATA VALID SSTRB CONVERSION CONVERSION MODE POWER-DOWN POWERED OFF POWERED UP Figure 12b. Timing Diagram Power-Down Modes, Internal Clock PD1 PD0 DEVICE MODE 0 0 Full Power-Down 0 1 Fast Power-Down 1 0 Internal Clock 1 1 External Clock Table 6. Hard-Wired Power-Down and Internal Clock Frequency SHDN STATE DEVICE MODE REFERENCE BUFFER COMPENSATION INTERNAL CLOCK FREQUENCY 1 Enabled Internal 225kHz Unconnected Enabled External 1.8MHz 0 PowerDown — — AVERAGE SUPPLY CURRENT vs. CONVERSION RATE (USING FULLPD) AVERAGE SUPPLY CURRENT vs. CONVERSION RATE WITH EXTERNAL REFERENCE VREF = VDD = 3.0V RLOAD = ∞ CODE = 1010101000 1000 100 8 CHANNELS 10 1 CHANNEL 1 100 AVERAGE SUPPLY CURRENT (µA) MAX148/9-F13 10,000 MAX148/9-F14A Table 5. Software Power-Down and Clock Mode AVERAGE SUPPLY CURRENT (µA) MAX148/MAX149 +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs RLOAD = ∞ CODE = 1010101000 8 CHANNELS 10 1 CHANNEL 1 0.1 0.1 1 10 100 1k 10k 100k 1M CONVERSION RATE (Hz) Figure 13. Average Supply Current vs. Conversion Rate with External Reference 0.01 0.1 1 10 100 1k CONVERSION RATE (Hz) Figure 14a. MAX149 Supply Current vs. Conversion Rate, FULLPD 16 ������������������������������������������������������������������������������������� +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs MAX148/9-F14B AVERAGE SUPPLY CURRENT (µA) 10,000 RLOAD = ∞ CODE = 1010101000 1000 8 CHANNELS 1 CHANNEL 100 0 1 0.1 1 10 100 1k 10k 100k 1M CONVERSION RATE (Hz) Figure 14b. MAX149 Supply Current vs. Conversion Rate, FASTPD TYPICAL REFERENCE-BUFFER POWER-UP DELAY vs. TIME IN SHUTDOWN POWER-UP DELAY (ms) MAX148/9-F14C 2.0 1.5 1.0 0.5 0 0.001 0.01 0.1 1 10 TIME IN SHUTDOWN (s) Figure 14c. Typical Reference-Buffer Power-Up Delay vs. Time in Shutdown Software Power-Down Software power-down is activated using bits PD1 and PD0 of the control byte. As shown in Table 5, PD1 and PD0 also specify the clock mode. When software shutdown is asserted, the ADC operates in the last specified clock mode until the conversion is complete. Then the ADC powers down into a low quiescent-current state. In internal clock mode, the interface remains active and conversion results may be clocked out after the MAX148/MAX149 enter a software power-down. The first logical 1 on DIN is interpreted as a start bit and powers up the MAX148/MAX149. Following the start bit, the data input word or control byte also determines clock mode and power-down states. For example, if the DIN word contains PD1 = 1, then the chip remains powered up. If PD0 = PD1 = 0, a power-down resumes after one conversion. Hardware Power-Down Pulling SHDN low places the converter in hardware power-down (Table 6). Unlike software power-down mode, the conversion is not completed; it stops coincidentally with SHDN being brought low. SHDN also controls the clock frequency in internal clock mode. Leaving SHDN unconnected sets the internal clock frequency to 1.8MHz. When returning to normal operation with SHDN unconnected, there is a tRC delay of approximately 2MI x CL, where CL is the capacitive loading on the SHDN pin. Pulling SHDN high sets internal clock frequency to 225kHz. This feature eases the settling-time requirement for the reference voltage. With an external reference, the MAX148/MAX149 can be considered fully powered up within 2Fs of actively pulling SHDN high. Power-Down Sequencing The MAX148/MAX149 auto power-down modes can save considerable power when operating at less than maximum sample rates. Figures 13, 14a, and 14b show the average supply current as a function of the sampling rate. The following discussion illustrates the various power-down sequences. Lowest Power at Up to 500 Conversions/Channel/Second The following examples show two different power-down sequences. Other combinations of clock rates, compensation modes, and power-down modes may give lowest power consumption in other applications. Figure 14a depicts the MAX149 power consumption for one or eight channel conversions utilizing full powerdown mode and internal-reference compensation. A 0.01FF bypass capacitor at REFADJ forms an RC filter with the internal 20kI reference resistor with a 0.2ms time constant. To achieve full 10-bit accuracy, 8 time constants or 1.6ms are required after power-up. Waiting this 1.6ms in FASTPD mode instead of in full power-up can reduce power consumption by a factor of 10 or more. This is achieved by using the sequence shown in Figure 15. ______________________________________________________________________________________ 17 MAX148/MAX149 AVERAGE SUPPLY CURRENT vs. CONVERSION RATE (USING FASTPD) MAX148/MAX149 +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs COMPLETE CONVERSION SEQUENCE 1.6ms WAIT DIN 1 (ZEROS) 00 FULLPD 1 0 1 FASTPD CH1 (ZEROS) CH7 1 1 1 1 0 0 1 FULLPD NOPD 0 1 FASTPD 1.21V 0 REFADJ H = RC = 20kI x CREFADJ 2.50V 0 VREF tBUFFEN = 75Fs Figure 15. MAX149 FULLPD/FASTPD Power-Up Sequence +3.3V OUTPUT CODE 24kI MAX149 510kI 100kI 12 REFADJ TRANSITION 11...111 FULL-SCALE TRANSITION 11...110 11...101 0.01µF FS = VREF + COM ZS = COM Figure 16. MAX149 Reference-Adjust Circuit 1 LSB = VREF 1024 00...011 Lowest Power at Higher Throughputs Figure 14b shows the power consumption with externalreference compensation in fast power-down, with one and eight channels converted. The external 4.7FF compensation requires a 75Fs wait after power-up with one dummy conversion. This graph shows fast multichannel conversion with the lowest power consumption possible. Full power-down mode may provide increased power savings in applications where the MAX148/MAX149 are inactive for long periods of time, but where intermittent bursts of high-speed conversions are required. Internal and External References The MAX149 can be used with an internal or external reference voltage, whereas an external reference is required for the MAX148. An external reference can be connected directly at VREF or at the REFADJ pin. An internal buffer is designed to provide 2.5V at VREF for both the MAX149 and the MAX148. The MAX149’s internally trimmed 1.21V reference is buffered with a 2.06 gain. The MAX148’s REFADJ pin is also buffered with a 2.00 gain to scale an external 1.25V reference at REFADJ to 2.5V at VREF. 00...010 00...001 00...000 0 (COM) 1 2 FS 3 INPUT VOLTAGE (LSB) FS - 3/2 LSB Figure 17. Unipolar Transfer Function, Full Scale (FS) = VREF + COM, Zero Scale (ZS) = COM Internal Reference (MAX149) The MAX149’s full-scale range with the internal reference is 2.5V with unipolar inputs and Q1.25V with bipolar inputs. The internal reference voltage is adjustable to Q1.5% with the circuit in Figure 16. External Reference With both the MAX149 and MAX148, an external reference can be placed at either the input (REFADJ) or the output (VREF) of the internal reference-buffer amplifier. The REFADJ input impedance is typically 20kI for the MAX149, and higher than 100kI for the MAX148. At VREF, the DC input resistance is a minimum of 18kI. During conversion, an external reference at VREF must 18 ������������������������������������������������������������������������������������� +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs UNIPOLAR MODE BIPOLAR MODE Full Scale Zero Scale Positive Full Scale Zero Scale Negative Full Scale VREF + COM COM VREF/2 + COM COM -VREF/2 + COM OUTPUT CODE VREF + COM 2 011 . . . 111 FS = 011 . . . 110 ZS = COM 000 . . . 010 000 . . . 001 -FS = -VREF + COM 2 1LSB = 000 . . . 000 SUPPLIES +3V VREF 1024 +3V GND +3V DGND R* = 10Ω 111 . . . 111 111 . . . 110 111 . . . 101 VDD AGND COM DGND DIGITAL CIRCUITRY 100 . . . 001 MAX148 MAX149 100 . . . 000 - FS COM* +FS - 1LSB *OPTIONAL INPUT VOLTAGE (LSB) *COM ≥ VREF/2 Figure 18. Bipolar Transfer Function, Full Scale (FS) = VREF/2 + COM, Zero Scale (ZS) = COM deliver up to 350FA DC load current and have 10I or less output impedance. If the reference has a higher output impedance or is noisy, bypass it close to the VREF pin with a 4.7FF capacitor. Using the REFADJ input makes buffering the external reference unnecessary. To use the direct VREF input, disable the internal buffer by tying REFADJ to VDD. In power-down, the input bias current to REFADJ is typically 25FA (MAX149) with REFADJ tied to VDD. Pull REFADJ to AGND to minimize the input bias current in power-down. Figure 19. Power-Supply Grounding Connection Transfer Function Table 7 shows the full-scale voltage ranges for unipolar and bipolar modes. The external reference must have a temperature coefficient of 20ppm/NC or less to achieve accuracy to within 1 LSB over the 0NC to +70NC commercial temperature range. Figure 17 depicts the nominal, unipolar input/output (I/O) transfer function, and Figure 18 shows the bipolar input/output transfer function. Code transitions occur halfway between successive-integer LSB values. Output coding is binary, with 1 LSB = 2.44mV (2.500V/1024) for unipolar operation, and 1 LSB = 2.44mV [(2.500V/2 -2.500V/2)/1024] for bipolar operation. ______________________________________________________________________________________ 19 MAX148/MAX149 Table 7. Full Scale and Zero Scale MAX148/MAX149 +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs +3V +3V 0.1µF ANALOG INPUTS 1µF VDD 20 (POWER SUPPLIES) SCLK 19 SCK CS 18 PCS0 DIN 17 MOSI CH4 SSTRB 16 6 CH5 DOUT 15 7 CH6 DGND 14 8 CH7 AGND 13 9 COM REFADJ 12 10 SHDN VREF 11 1 CH0 2 CH1 3 4 CH2 MAX148 MAX149 CH3 5 MC683XX MISO (GND) 0.1µF +2.5V Figure 20. MAX148/MAX149 QSPI Connections, External Reference Layout, Grounding, and Bypassing XF CLKX For best performance, use PCBs. Wire-wrap boards are not recommended. Board layout should ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the ADC package. CS SCLK TMS320LC3x MAX148 MAX149 CLKR DX DIN DR DOUT FSR SSTRB Figure 21. MAX148/MAX149-to-TMS320 Serial Interface Figure 19 shows the recommended system ground connections. Establish a single-point analog ground (star ground point) at AGND, separate from the logic ground. Connect all other analog grounds and DGND to the star ground. No other digital system ground should be connected to this ground. For lowest-noise operation, the ground return to the star ground’s power supply should be low impedance and as short as possible. High-frequency noise in the VDD power supply may affect the high-speed comparator in the ADC. Bypass the supply to the star ground with 0.1FF and 1FF capacitors close to pin 20 of the MAX148/MAX149. Minimize capacitor lead lengths for best supply-noise rejection. If the power supply is very noisy, a 10I resistor can be connected as a lowpass filter (Figure 19). 20 ������������������������������������������������������������������������������������� 8-string WLED Driver with Integrated Step-up Regulator and SMBus/PWM Dimming Capability SCLK DIN START SEL2 SEL1 SEL0 UNI/BIP SGL/DIF PD1 PD0 HIGH IMPEDANCE SSTRB DOUT MSB B8 S1 S0 HIGH IMPEDANCE Figure 22. TMS320 Serial-Interface Timing Diagram High-Speed Digital Interfacing with QSPI The MAX148/MAX149 can interface with QSPI using the circuit in Figure 20 (fSCLK = 2.0MHz, CPOL = 0, CPHA = 0). This QSPI circuit can be programmed to do a conversion on each of the eight channels. The result is stored in memory without taxing the CPU, since QSPI incorporates its own microsequencer. The MAX148/MAX149 are QSPI compatible up to the maximum external clock frequency of 2MHz. TMS320LC3x Interface Figure 21 shows an application circuit to interface the MAX148/MAX149 to the TMS320 in external clock mode. The timing diagram for this interface circuit is shown in Figure 22. Use the following steps to initiate a conversion in the MAX148/MAX149 and to read the results: 1) The TMS320 should be configured with CLKX (transmit clock) as an active-high output clock and CLKR (TMS320 receive clock) as an active-high input clock. CLKX and CLKR on the TMS320 are tied together with the MAX148/MAX149’s SCLK input. 2) The MAX148/MAX149’s CS pin is driven low by the TMS320’s XF_ I/O port to enable data to be clocked into the MAX148/MAX149’s DIN. 3) An 8-bit word (1XXXXX11) should be written to the MAX148/MAX149 to initiate a conversion and place the device into external clock mode. See Table 1 to select the proper XXXXX bit values for your specific application. 4) The MAX148/MAX149’s SSTRB output is monitored through the TMS320’s FSR input. A falling edge on the SSTRB output indicates that the conversion is in progress and data is ready to be received from the MAX148/MAX149. 5) The TMS320 reads in one data bit on each of the next 16 rising edges of SCLK. These data bits represent the 10 + 2-bit conversion result followed by 4 trailing bits, which should be ignored. 6) Pull CS high to disable the MAX148/MAX149 until the next conversion is initiated. ______________________________________________________________________________________ 21 MAX148/MAX149 CS MAX148/MAX149 +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs Ordering Information (continued) Pin Configuration TEMP RANGE PINPACKAGE INL (LSB) MAX148AEPP -40°C to +85°C 20 Plastic DIP ±1/2 MAX148BEPP -40°C to +85°C 20 Plastic DIP ±1 CHO 1 11 VDD MAX148AEAP -40°C to +85°C 20 SSOP ±1/2 CH1 2 12 SCLK MAX148BEAP -40°C to +85°C 20 SSOP ±1 3 MAX148AMJP -55°C to +125°C 20 CERDIP* ±1/2 CH2 MAX148BMJP -55°C to +125°C 20 CERDIP* ±1 CH3 4 MAX149ACPP 0°C to +70°C 20 Plastic DIP ±1/2 CH4 5 MAX149BCPP 0°C to +70°C 20 Plastic DIP ±1 CH5 6 16 DOUT MAX149ACAP 0°C to +70°C ±1/2 CH6 7 17 DGND MAX149BCAP 0°C to +70°C 20 SSOP 20 Plastic DIP CH7 8 18 AGND MAX149AEPP -40°C to +85°C 20 Plastic DIP ±1/2 COM 9 19 REFADJ PART† TOP VIEW ±1 MAX149BEPP -40°C to +85°C 20 Plastic DIP ±1 MAX149AEAP -40°C to +85°C 20 SSOP ±1/2 MAX149BEAP -40°C to +85°C 20 SSOP ±1 MAX149AMJP -55°C to +125°C 20 CERDIP* ±1/2 MAX149BMAP/PR -55°C to +125°C 20 SSOP ±1 MAX149BMJP -55°C to +125°C 20 CERDIP* ±1 †Contact factory for availability of alternate surface-mount package. Specify lead-free by placing + by the part number when ordering. *Contact factory for availability of CERDIP package, and for processing to MIL-STD-883B. Not available in lead-free. 13 CS MAX148 MAX149 SHDN 10 14 DIN 15 SSTRB 20 VREF DIP/SSOP Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 20 Plastic Dip P20-4 21-0043 20 SSOP A20-1 21-0056 20 CERDIP J20-2 21-0045 22 ������������������������������������������������������������������������������������� +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs REVISION NUMBER REVISION DATE 3 5/09 DESCRIPTION Revised Ordering Information, Electrical Characteristics table, Pin Description, Figure 9, added ruggedized plastic information. PAGES CHANGED 1–4, 7, 13, 14, 16, 17, 22–23 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products 23 Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX148/MAX149 Revision History